2 * Toshiba TC6393XB SoC support
4 * Copyright(c) 2005-2006 Chris Humbert
5 * Copyright(c) 2005 Dirk Opfer
6 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
7 * Copyright(c) 2007 Dmitry Baryshkov
9 * Based on code written by Sharp/Lineo for 2.4 kernels
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mfd/tc6393xb.h>
27 #include <linux/gpio.h>
28 #include <linux/slab.h>
30 #define SCR_REVID 0x08 /* b Revision ID */
31 #define SCR_ISR 0x50 /* b Interrupt Status */
32 #define SCR_IMR 0x52 /* b Interrupt Mask */
33 #define SCR_IRR 0x54 /* b Interrupt Routing */
34 #define SCR_GPER 0x60 /* w GP Enable */
35 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
36 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
37 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
38 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
39 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
40 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
41 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
42 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
43 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
44 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
45 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
46 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
47 #define SCR_CCR 0x98 /* w Clock Control */
48 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
49 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
50 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
51 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
52 #define SCR_FER 0xe0 /* b Function Enable */
53 #define SCR_MCR 0xe4 /* w Mode Control */
54 #define SCR_CONFIG 0xfc /* b Configuration Control */
55 #define SCR_DEBUG 0xff /* b Debug */
57 #define SCR_CCR_CK32K BIT(0)
58 #define SCR_CCR_USBCK BIT(1)
59 #define SCR_CCR_UNK1 BIT(4)
60 #define SCR_CCR_MCLK_MASK (7 << 8)
61 #define SCR_CCR_MCLK_OFF (0 << 8)
62 #define SCR_CCR_MCLK_12 (1 << 8)
63 #define SCR_CCR_MCLK_24 (2 << 8)
64 #define SCR_CCR_MCLK_48 (3 << 8)
65 #define SCR_CCR_HCLK_MASK (3 << 12)
66 #define SCR_CCR_HCLK_24 (0 << 12)
67 #define SCR_CCR_HCLK_48 (1 << 12)
69 #define SCR_FER_USBEN BIT(0) /* USB host enable */
70 #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
71 #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
73 #define SCR_MCR_RDY_MASK (3 << 0)
74 #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
75 #define SCR_MCR_RDY_TRISTATE (1 << 0)
76 #define SCR_MCR_RDY_PUSHPULL (2 << 0)
77 #define SCR_MCR_RDY_UNK BIT(2)
78 #define SCR_MCR_RDY_EN BIT(3)
79 #define SCR_MCR_INT_MASK (3 << 4)
80 #define SCR_MCR_INT_OPENDRAIN (0 << 4)
81 #define SCR_MCR_INT_TRISTATE (1 << 4)
82 #define SCR_MCR_INT_PUSHPULL (2 << 4)
83 #define SCR_MCR_INT_UNK BIT(6)
84 #define SCR_MCR_INT_EN BIT(7)
85 /* bits 8 - 16 are unknown */
87 #define TC_GPIO_BIT(i) (1 << (i & 0x7))
89 /*--------------------------------------------------------------------------*/
94 struct gpio_chip gpio;
96 struct clk *clk; /* 3,6 Mhz */
98 spinlock_t lock; /* protects RMW cycles */
108 struct resource rscr;
109 struct resource *iomem;
121 /*--------------------------------------------------------------------------*/
123 static int tc6393xb_nand_enable(struct platform_device *nand)
125 struct platform_device *dev = to_platform_device(nand->dev.parent);
126 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
129 spin_lock_irqsave(&tc6393xb->lock, flags);
132 dev_dbg(&dev->dev, "SMD buffer on\n");
133 tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
135 spin_unlock_irqrestore(&tc6393xb->lock, flags);
140 static struct resource __devinitdata tc6393xb_nand_resources[] = {
144 .flags = IORESOURCE_MEM,
149 .flags = IORESOURCE_MEM,
152 .start = IRQ_TC6393_NAND,
153 .end = IRQ_TC6393_NAND,
154 .flags = IORESOURCE_IRQ,
158 static struct resource tc6393xb_mmc_resources[] = {
162 .flags = IORESOURCE_MEM,
165 .start = IRQ_TC6393_MMC,
166 .end = IRQ_TC6393_MMC,
167 .flags = IORESOURCE_IRQ,
171 static const struct resource tc6393xb_ohci_resources[] = {
175 .flags = IORESOURCE_MEM,
180 .flags = IORESOURCE_MEM,
185 .flags = IORESOURCE_MEM,
190 .flags = IORESOURCE_MEM,
193 .start = IRQ_TC6393_OHCI,
194 .end = IRQ_TC6393_OHCI,
195 .flags = IORESOURCE_IRQ,
199 static struct resource __devinitdata tc6393xb_fb_resources[] = {
203 .flags = IORESOURCE_MEM,
208 .flags = IORESOURCE_MEM,
213 .flags = IORESOURCE_MEM,
216 .start = IRQ_TC6393_FB,
217 .end = IRQ_TC6393_FB,
218 .flags = IORESOURCE_IRQ,
222 static int tc6393xb_ohci_enable(struct platform_device *dev)
224 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
229 spin_lock_irqsave(&tc6393xb->lock, flags);
231 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
232 ccr |= SCR_CCR_USBCK;
233 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
235 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
236 fer |= SCR_FER_USBEN;
237 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
239 spin_unlock_irqrestore(&tc6393xb->lock, flags);
244 static int tc6393xb_ohci_disable(struct platform_device *dev)
246 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
251 spin_lock_irqsave(&tc6393xb->lock, flags);
253 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
254 fer &= ~SCR_FER_USBEN;
255 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
257 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
258 ccr &= ~SCR_CCR_USBCK;
259 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
261 spin_unlock_irqrestore(&tc6393xb->lock, flags);
266 static int tc6393xb_fb_enable(struct platform_device *dev)
268 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
272 spin_lock_irqsave(&tc6393xb->lock, flags);
274 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
275 ccr &= ~SCR_CCR_MCLK_MASK;
276 ccr |= SCR_CCR_MCLK_48;
277 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
279 spin_unlock_irqrestore(&tc6393xb->lock, flags);
284 static int tc6393xb_fb_disable(struct platform_device *dev)
286 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
290 spin_lock_irqsave(&tc6393xb->lock, flags);
292 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
293 ccr &= ~SCR_CCR_MCLK_MASK;
294 ccr |= SCR_CCR_MCLK_OFF;
295 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
297 spin_unlock_irqrestore(&tc6393xb->lock, flags);
302 int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
304 struct platform_device *dev = to_platform_device(fb->dev.parent);
305 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
309 spin_lock_irqsave(&tc6393xb->lock, flags);
311 fer = ioread8(tc6393xb->scr + SCR_FER);
313 fer |= SCR_FER_SLCDEN;
315 fer &= ~SCR_FER_SLCDEN;
316 iowrite8(fer, tc6393xb->scr + SCR_FER);
318 spin_unlock_irqrestore(&tc6393xb->lock, flags);
322 EXPORT_SYMBOL(tc6393xb_lcd_set_power);
324 int tc6393xb_lcd_mode(struct platform_device *fb,
325 const struct fb_videomode *mode) {
326 struct platform_device *dev = to_platform_device(fb->dev.parent);
327 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
330 spin_lock_irqsave(&tc6393xb->lock, flags);
332 iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
333 iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
335 spin_unlock_irqrestore(&tc6393xb->lock, flags);
339 EXPORT_SYMBOL(tc6393xb_lcd_mode);
341 static int tc6393xb_mmc_enable(struct platform_device *mmc)
343 struct platform_device *dev = to_platform_device(mmc->dev.parent);
344 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
346 tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
347 tc6393xb_mmc_resources[0].start & 0xfffe);
352 static int tc6393xb_mmc_resume(struct platform_device *mmc)
354 struct platform_device *dev = to_platform_device(mmc->dev.parent);
355 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
357 tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
358 tc6393xb_mmc_resources[0].start & 0xfffe);
363 static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
365 struct platform_device *dev = to_platform_device(mmc->dev.parent);
366 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
368 tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
371 static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
373 struct platform_device *dev = to_platform_device(mmc->dev.parent);
374 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
376 tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
379 static struct tmio_mmc_data tc6393xb_mmc_data = {
381 .set_pwr = tc6393xb_mmc_pwr,
382 .set_clk_div = tc6393xb_mmc_clk_div,
385 static struct mfd_cell __devinitdata tc6393xb_cells[] = {
386 [TC6393XB_CELL_NAND] = {
388 .enable = tc6393xb_nand_enable,
389 .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
390 .resources = tc6393xb_nand_resources,
392 [TC6393XB_CELL_MMC] = {
394 .enable = tc6393xb_mmc_enable,
395 .resume = tc6393xb_mmc_resume,
396 .mfd_data = &tc6393xb_mmc_data,
397 .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
398 .resources = tc6393xb_mmc_resources,
400 [TC6393XB_CELL_OHCI] = {
402 .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
403 .resources = tc6393xb_ohci_resources,
404 .enable = tc6393xb_ohci_enable,
405 .suspend = tc6393xb_ohci_disable,
406 .resume = tc6393xb_ohci_enable,
407 .disable = tc6393xb_ohci_disable,
409 [TC6393XB_CELL_FB] = {
411 .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
412 .resources = tc6393xb_fb_resources,
413 .enable = tc6393xb_fb_enable,
414 .suspend = tc6393xb_fb_disable,
415 .resume = tc6393xb_fb_enable,
416 .disable = tc6393xb_fb_disable,
420 /*--------------------------------------------------------------------------*/
422 static int tc6393xb_gpio_get(struct gpio_chip *chip,
425 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
427 /* XXX: does dsr also represent inputs? */
428 return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
429 & TC_GPIO_BIT(offset);
432 static void __tc6393xb_gpio_set(struct gpio_chip *chip,
433 unsigned offset, int value)
435 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
438 dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
440 dsr |= TC_GPIO_BIT(offset);
442 dsr &= ~TC_GPIO_BIT(offset);
444 tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
447 static void tc6393xb_gpio_set(struct gpio_chip *chip,
448 unsigned offset, int value)
450 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
453 spin_lock_irqsave(&tc6393xb->lock, flags);
455 __tc6393xb_gpio_set(chip, offset, value);
457 spin_unlock_irqrestore(&tc6393xb->lock, flags);
460 static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
463 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
467 spin_lock_irqsave(&tc6393xb->lock, flags);
469 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
470 doecr &= ~TC_GPIO_BIT(offset);
471 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
473 spin_unlock_irqrestore(&tc6393xb->lock, flags);
478 static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
479 unsigned offset, int value)
481 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
485 spin_lock_irqsave(&tc6393xb->lock, flags);
487 __tc6393xb_gpio_set(chip, offset, value);
489 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
490 doecr |= TC_GPIO_BIT(offset);
491 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
493 spin_unlock_irqrestore(&tc6393xb->lock, flags);
498 static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
500 tc6393xb->gpio.label = "tc6393xb";
501 tc6393xb->gpio.base = gpio_base;
502 tc6393xb->gpio.ngpio = 16;
503 tc6393xb->gpio.set = tc6393xb_gpio_set;
504 tc6393xb->gpio.get = tc6393xb_gpio_get;
505 tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
506 tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
508 return gpiochip_add(&tc6393xb->gpio);
511 /*--------------------------------------------------------------------------*/
514 tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
516 struct tc6393xb *tc6393xb = irq_get_handler_data(irq);
518 unsigned int i, irq_base;
520 irq_base = tc6393xb->irq_base;
522 while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
523 ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
524 for (i = 0; i < TC6393XB_NR_IRQS; i++) {
526 generic_handle_irq(irq_base + i);
530 static void tc6393xb_irq_ack(struct irq_data *data)
534 static void tc6393xb_irq_mask(struct irq_data *data)
536 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
540 spin_lock_irqsave(&tc6393xb->lock, flags);
541 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
542 imr |= 1 << (data->irq - tc6393xb->irq_base);
543 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
544 spin_unlock_irqrestore(&tc6393xb->lock, flags);
547 static void tc6393xb_irq_unmask(struct irq_data *data)
549 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
553 spin_lock_irqsave(&tc6393xb->lock, flags);
554 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
555 imr &= ~(1 << (data->irq - tc6393xb->irq_base));
556 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
557 spin_unlock_irqrestore(&tc6393xb->lock, flags);
560 static struct irq_chip tc6393xb_chip = {
562 .irq_ack = tc6393xb_irq_ack,
563 .irq_mask = tc6393xb_irq_mask,
564 .irq_unmask = tc6393xb_irq_unmask,
567 static void tc6393xb_attach_irq(struct platform_device *dev)
569 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
570 unsigned int irq, irq_base;
572 irq_base = tc6393xb->irq_base;
574 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
575 irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
576 irq_set_chip_data(irq, tc6393xb);
577 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
580 irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
581 irq_set_handler_data(tc6393xb->irq, tc6393xb);
582 irq_set_chained_handler(tc6393xb->irq, tc6393xb_irq);
585 static void tc6393xb_detach_irq(struct platform_device *dev)
587 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
588 unsigned int irq, irq_base;
590 irq_set_chained_handler(tc6393xb->irq, NULL);
591 irq_set_handler_data(tc6393xb->irq, NULL);
593 irq_base = tc6393xb->irq_base;
595 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
596 set_irq_flags(irq, 0);
597 irq_set_chip(irq, NULL);
598 irq_set_chip_data(irq, NULL);
602 /*--------------------------------------------------------------------------*/
604 static int __devinit tc6393xb_probe(struct platform_device *dev)
606 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
607 struct tc6393xb *tc6393xb;
608 struct resource *iomem, *rscr;
611 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
615 tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
621 spin_lock_init(&tc6393xb->lock);
623 platform_set_drvdata(dev, tc6393xb);
625 ret = platform_get_irq(dev, 0);
631 tc6393xb->iomem = iomem;
632 tc6393xb->irq_base = tcpd->irq_base;
634 tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
635 if (IS_ERR(tc6393xb->clk)) {
636 ret = PTR_ERR(tc6393xb->clk);
640 rscr = &tc6393xb->rscr;
641 rscr->name = "tc6393xb-core";
642 rscr->start = iomem->start;
643 rscr->end = iomem->start + 0xff;
644 rscr->flags = IORESOURCE_MEM;
646 ret = request_resource(iomem, rscr);
648 goto err_request_scr;
650 tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
651 if (!tc6393xb->scr) {
656 ret = clk_enable(tc6393xb->clk);
660 ret = tcpd->enable(dev);
664 iowrite8(0, tc6393xb->scr + SCR_FER);
665 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
666 iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
667 tc6393xb->scr + SCR_CCR);
668 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
669 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
670 BIT(15), tc6393xb->scr + SCR_MCR);
671 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
672 iowrite8(0, tc6393xb->scr + SCR_IRR);
673 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
675 printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
676 tmio_ioread8(tc6393xb->scr + SCR_REVID),
677 (unsigned long) iomem->start, tc6393xb->irq);
679 tc6393xb->gpio.base = -1;
681 if (tcpd->gpio_base >= 0) {
682 ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
687 tc6393xb_attach_irq(dev);
690 ret = tcpd->setup(dev);
695 tc6393xb_cells[TC6393XB_CELL_NAND].mfd_data = tcpd->nand_data;
696 tc6393xb_cells[TC6393XB_CELL_FB].mfd_data = tcpd->fb_data;
698 ret = mfd_add_devices(&dev->dev, dev->id,
699 tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
700 iomem, tcpd->irq_base);
709 tc6393xb_detach_irq(dev);
712 if (tc6393xb->gpio.base != -1)
713 temp = gpiochip_remove(&tc6393xb->gpio);
716 clk_disable(tc6393xb->clk);
718 iounmap(tc6393xb->scr);
720 release_resource(&tc6393xb->rscr);
722 clk_put(tc6393xb->clk);
730 static int __devexit tc6393xb_remove(struct platform_device *dev)
732 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
733 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
736 mfd_remove_devices(&dev->dev);
741 tc6393xb_detach_irq(dev);
743 if (tc6393xb->gpio.base != -1) {
744 ret = gpiochip_remove(&tc6393xb->gpio);
746 dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
751 ret = tcpd->disable(dev);
752 clk_disable(tc6393xb->clk);
753 iounmap(tc6393xb->scr);
754 release_resource(&tc6393xb->rscr);
755 platform_set_drvdata(dev, NULL);
756 clk_put(tc6393xb->clk);
763 static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
765 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
766 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
769 tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
770 tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
772 for (i = 0; i < 3; i++) {
773 tc6393xb->suspend_state.gpo_dsr[i] =
774 ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
775 tc6393xb->suspend_state.gpo_doecr[i] =
776 ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
777 tc6393xb->suspend_state.gpi_bcr[i] =
778 ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
780 ret = tcpd->suspend(dev);
781 clk_disable(tc6393xb->clk);
786 static int tc6393xb_resume(struct platform_device *dev)
788 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
789 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
793 clk_enable(tc6393xb->clk);
795 ret = tcpd->resume(dev);
799 if (!tcpd->resume_restore)
802 iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
803 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
804 iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
805 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
806 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
807 BIT(15), tc6393xb->scr + SCR_MCR);
808 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
809 iowrite8(0, tc6393xb->scr + SCR_IRR);
810 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
812 for (i = 0; i < 3; i++) {
813 iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
814 tc6393xb->scr + SCR_GPO_DSR(i));
815 iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
816 tc6393xb->scr + SCR_GPO_DOECR(i));
817 iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
818 tc6393xb->scr + SCR_GPI_BCR(i));
824 #define tc6393xb_suspend NULL
825 #define tc6393xb_resume NULL
828 static struct platform_driver tc6393xb_driver = {
829 .probe = tc6393xb_probe,
830 .remove = __devexit_p(tc6393xb_remove),
831 .suspend = tc6393xb_suspend,
832 .resume = tc6393xb_resume,
836 .owner = THIS_MODULE,
840 static int __init tc6393xb_init(void)
842 return platform_driver_register(&tc6393xb_driver);
845 static void __exit tc6393xb_exit(void)
847 platform_driver_unregister(&tc6393xb_driver);
850 subsys_initcall(tc6393xb_init);
851 module_exit(tc6393xb_exit);
853 MODULE_LICENSE("GPL v2");
854 MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
855 MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
856 MODULE_ALIAS("platform:tc6393xb");