2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/kthread.h>
34 #include <linux/slab.h>
36 #include <linux/i2c/twl.h>
41 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
42 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
43 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
44 * SIH modules are more traditional IRQ components, which support per-IRQ
45 * enable/disable and trigger controls; they do most of the work.
47 * These chips are designed to support IRQ handling from two different
48 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
49 * and mask registers in the PIH and SIH modules.
51 * We set up IRQs starting at a platform-specified base, always starting
52 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
53 * base + 0 .. base + 7 PIH
54 * base + 8 .. base + 15 SIH for PWR_INT
55 * base + 16 .. base + 33 SIH for GPIO
58 /* PIH register offsets */
59 #define REG_PIH_ISR_P1 0x01
60 #define REG_PIH_ISR_P2 0x02
61 #define REG_PIH_SIR 0x03 /* for testing */
64 /* Linux could (eventually) use either IRQ line */
69 u8 module; /* module id */
70 u8 control_offset; /* for SIH_CTRL */
73 u8 bits; /* valid in isr/imr */
74 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
77 u8 bytes_edr; /* bytelen of EDR */
79 u8 irq_lines; /* number of supported irq lines */
81 /* SIR ignored -- set interrupt, for testing only */
86 /* + 2 bytes padding */
89 static const struct sih *sih_modules;
90 static int nr_sih_modules;
92 #define SIH_INITIALIZER(modname, nbits) \
93 .module = TWL4030_MODULE_ ## modname, \
94 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
96 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
97 .edr_offset = TWL4030_ ## modname ## _EDR, \
98 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
101 .isr_offset = TWL4030_ ## modname ## _ISR1, \
102 .imr_offset = TWL4030_ ## modname ## _IMR1, \
105 .isr_offset = TWL4030_ ## modname ## _ISR2, \
106 .imr_offset = TWL4030_ ## modname ## _IMR2, \
109 /* register naming policies are inconsistent ... */
110 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
111 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
112 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
115 /* Order in this table matches order in PIH_ISR. That is,
116 * BIT(n) in PIH_ISR is sih_modules[n].
118 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
119 static const struct sih sih_modules_twl4030[6] = {
122 .module = TWL4030_MODULE_GPIO,
123 .control_offset = REG_GPIO_SIH_CTRL,
125 .bits = TWL4030_GPIO_MAX,
127 /* Note: *all* of these IRQs default to no-trigger */
128 .edr_offset = REG_GPIO_EDR1,
132 .isr_offset = REG_GPIO_ISR1A,
133 .imr_offset = REG_GPIO_IMR1A,
135 .isr_offset = REG_GPIO_ISR1B,
136 .imr_offset = REG_GPIO_IMR1B,
142 SIH_INITIALIZER(KEYPAD_KEYP, 4)
146 .module = TWL4030_MODULE_INTERRUPTS,
147 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
151 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
152 /* Note: most of these IRQs default to no-trigger */
156 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
157 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
159 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
160 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
165 SIH_INITIALIZER(MADC, 4)
168 /* USB doesn't use the same SIH organization */
174 SIH_INITIALIZER(INT_PWR, 8)
176 /* there are no SIH modules #6 or #7 ... */
179 static const struct sih sih_modules_twl5031[8] = {
182 .module = TWL4030_MODULE_GPIO,
183 .control_offset = REG_GPIO_SIH_CTRL,
185 .bits = TWL4030_GPIO_MAX,
187 /* Note: *all* of these IRQs default to no-trigger */
188 .edr_offset = REG_GPIO_EDR1,
192 .isr_offset = REG_GPIO_ISR1A,
193 .imr_offset = REG_GPIO_IMR1A,
195 .isr_offset = REG_GPIO_ISR1B,
196 .imr_offset = REG_GPIO_IMR1B,
202 SIH_INITIALIZER(KEYPAD_KEYP, 4)
206 .module = TWL5031_MODULE_INTERRUPTS,
207 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
210 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
211 /* Note: most of these IRQs default to no-trigger */
215 .isr_offset = TWL5031_INTERRUPTS_BCIISR1,
216 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
218 .isr_offset = TWL5031_INTERRUPTS_BCIISR2,
219 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
224 SIH_INITIALIZER(MADC, 4)
227 /* USB doesn't use the same SIH organization */
233 SIH_INITIALIZER(INT_PWR, 8)
237 * ECI/DBI doesn't use the same SIH organization.
238 * For example, it supports only one interrupt output line.
239 * That is, the interrupts are seen on both INT1 and INT2 lines.
242 .module = TWL5031_MODULE_ACCESSORY,
247 .isr_offset = TWL5031_ACIIDR_LSB,
248 .imr_offset = TWL5031_ACIIMR_LSB,
253 /* Audio accessory */
255 .module = TWL5031_MODULE_ACCESSORY,
256 .control_offset = TWL5031_ACCSIHCTRL,
259 .edr_offset = TWL5031_ACCEDR1,
260 /* Note: most of these IRQs default to no-trigger */
264 .isr_offset = TWL5031_ACCISR1,
265 .imr_offset = TWL5031_ACCIMR1,
267 .isr_offset = TWL5031_ACCISR2,
268 .imr_offset = TWL5031_ACCIMR2,
273 #undef TWL4030_MODULE_KEYPAD_KEYP
274 #undef TWL4030_MODULE_INT_PWR
275 #undef TWL4030_INT_PWR_EDR
277 /*----------------------------------------------------------------------*/
279 static unsigned twl4030_irq_base;
281 static struct completion irq_event;
284 * This thread processes interrupts reported by the Primary Interrupt Handler.
286 static int twl4030_irq_thread(void *data)
288 long irq = (long)data;
289 static unsigned i2c_errors;
290 static const unsigned max_i2c_errors = 100;
293 current->flags |= PF_NOFREEZE;
295 while (!kthread_should_stop()) {
300 /* Wait for IRQ, then read PIH irq status (also blocking) */
301 wait_for_completion_interruptible(&irq_event);
303 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr,
306 pr_warning("twl4030: I2C error %d reading PIH ISR\n",
308 if (++i2c_errors >= max_i2c_errors) {
309 printk(KERN_ERR "Maximum I2C error count"
310 " exceeded. Terminating %s.\n",
314 complete(&irq_event);
318 /* these handlers deal with the relevant SIH irq status */
320 for (module_irq = twl4030_irq_base;
322 pih_isr >>= 1, module_irq++) {
324 struct irq_desc *d = irq_to_desc(module_irq);
327 pr_err("twl4030: Invalid SIH IRQ: %d\n",
332 /* These can't be masked ... always warn
333 * if we get any surprises.
335 if (d->status & IRQ_DISABLED)
336 note_interrupt(module_irq, d,
339 d->handle_irq(module_irq, d);
351 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
352 * This is a chained interrupt, so there is no desc->action method for it.
353 * Now we need to query the interrupt controller in the twl4030 to determine
354 * which module is generating the interrupt request. However, we can't do i2c
355 * transactions in interrupt context, so we must defer that work to a kernel
356 * thread. All we do here is acknowledge and mask the interrupt and wakeup
359 static irqreturn_t handle_twl4030_pih(int irq, void *devid)
361 /* Acknowledge, clear *AND* mask the interrupt... */
362 disable_irq_nosync(irq);
366 /*----------------------------------------------------------------------*/
369 * twl4030_init_sih_modules() ... start from a known state where no
370 * IRQs will be coming in, and where we can quickly enable them then
371 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
373 * NOTE: we don't touch EDR registers here; they stay with hardware
374 * defaults or whatever the last value was. Note that when both EDR
375 * bits for an IRQ are clear, that's as if its IMR bit is set...
377 static int twl4030_init_sih_modules(unsigned line)
379 const struct sih *sih;
384 /* line 0 == int1_n signal; line 1 == int2_n signal */
390 /* disable all interrupts on our line */
391 memset(buf, 0xff, sizeof buf);
393 for (i = 0; i < nr_sih_modules; i++, sih++) {
395 /* skip USB -- it's funky */
399 /* Not all the SIH modules support multiple interrupt lines */
400 if (sih->irq_lines <= line)
403 status = twl_i2c_write(sih->module, buf,
404 sih->mask[line].imr_offset, sih->bytes_ixr);
406 pr_err("twl4030: err %d initializing %s %s\n",
407 status, sih->name, "IMR");
409 /* Maybe disable "exclusive" mode; buffer second pending irq;
410 * set Clear-On-Read (COR) bit.
412 * NOTE that sometimes COR polarity is documented as being
413 * inverted: for MADC, COR=1 means "clear on write".
414 * And for PWR_INT it's not documented...
417 status = twl_i2c_write_u8(sih->module,
418 TWL4030_SIH_CTRL_COR_MASK,
419 sih->control_offset);
421 pr_err("twl4030: err %d initializing %s %s\n",
422 status, sih->name, "SIH_CTRL");
427 for (i = 0; i < nr_sih_modules; i++, sih++) {
435 /* Not all the SIH modules support multiple interrupt lines */
436 if (sih->irq_lines <= line)
439 /* Clear pending interrupt status. Either the read was
440 * enough, or we need to write those bits. Repeat, in
441 * case an IRQ is pending (PENDDIS=0) ... that's not
442 * uncommon with PWR_INT.PWRON.
444 for (j = 0; j < 2; j++) {
445 status = twl_i2c_read(sih->module, rxbuf,
446 sih->mask[line].isr_offset, sih->bytes_ixr);
448 pr_err("twl4030: err %d initializing %s %s\n",
449 status, sih->name, "ISR");
452 status = twl_i2c_write(sih->module, buf,
453 sih->mask[line].isr_offset,
455 /* else COR=1 means read sufficed.
456 * (for most SIH modules...)
464 static inline void activate_irq(int irq)
467 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
468 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
470 set_irq_flags(irq, IRQF_VALID);
472 /* same effect on other architectures */
473 set_irq_noprobe(irq);
477 /*----------------------------------------------------------------------*/
479 static DEFINE_SPINLOCK(sih_agent_lock);
481 static struct workqueue_struct *wq;
485 const struct sih *sih;
488 bool imr_change_pending;
489 struct work_struct mask_work;
492 struct work_struct edge_work;
495 static void twl4030_sih_do_mask(struct work_struct *work)
497 struct sih_agent *agent;
498 const struct sih *sih;
505 agent = container_of(work, struct sih_agent, mask_work);
507 /* see what work we have */
508 spin_lock_irq(&sih_agent_lock);
509 if (agent->imr_change_pending) {
511 /* byte[0] gets overwritten as we write ... */
512 imr.word = cpu_to_le32(agent->imr << 8);
513 agent->imr_change_pending = false;
516 spin_unlock_irq(&sih_agent_lock);
520 /* write the whole mask ... simpler than subsetting it */
521 status = twl_i2c_write(sih->module, imr.bytes,
522 sih->mask[irq_line].imr_offset, sih->bytes_ixr);
524 pr_err("twl4030: %s, %s --> %d\n", __func__,
528 static void twl4030_sih_do_edge(struct work_struct *work)
530 struct sih_agent *agent;
531 const struct sih *sih;
536 agent = container_of(work, struct sih_agent, edge_work);
538 /* see what work we have */
539 spin_lock_irq(&sih_agent_lock);
540 edge_change = agent->edge_change;
541 agent->edge_change = 0;
542 sih = edge_change ? agent->sih : NULL;
543 spin_unlock_irq(&sih_agent_lock);
547 /* Read, reserving first byte for write scratch. Yes, this
548 * could be cached for some speedup ... but be careful about
549 * any processor on the other IRQ line, EDR registers are
552 status = twl_i2c_read(sih->module, bytes + 1,
553 sih->edr_offset, sih->bytes_edr);
555 pr_err("twl4030: %s, %s --> %d\n", __func__,
560 /* Modify only the bits we know must change */
561 while (edge_change) {
562 int i = fls(edge_change) - 1;
563 struct irq_desc *d = irq_to_desc(i + agent->irq_base);
564 int byte = 1 + (i >> 2);
565 int off = (i & 0x3) * 2;
568 pr_err("twl4030: Invalid IRQ: %d\n",
569 i + agent->irq_base);
573 bytes[byte] &= ~(0x03 << off);
575 raw_spin_lock_irq(&d->lock);
576 if (d->status & IRQ_TYPE_EDGE_RISING)
577 bytes[byte] |= BIT(off + 1);
578 if (d->status & IRQ_TYPE_EDGE_FALLING)
579 bytes[byte] |= BIT(off + 0);
580 raw_spin_unlock_irq(&d->lock);
582 edge_change &= ~BIT(i);
586 status = twl_i2c_write(sih->module, bytes,
587 sih->edr_offset, sih->bytes_edr);
589 pr_err("twl4030: %s, %s --> %d\n", __func__,
593 /*----------------------------------------------------------------------*/
596 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
597 * which can't perform the underlying I2C operations (because they sleep).
598 * So we must hand them off to a thread (workqueue) and cope with asynch
599 * completion, potentially including some re-ordering, of these requests.
602 static void twl4030_sih_mask(unsigned irq)
604 struct sih_agent *sih = get_irq_chip_data(irq);
607 spin_lock_irqsave(&sih_agent_lock, flags);
608 sih->imr |= BIT(irq - sih->irq_base);
609 sih->imr_change_pending = true;
610 queue_work(wq, &sih->mask_work);
611 spin_unlock_irqrestore(&sih_agent_lock, flags);
614 static void twl4030_sih_unmask(unsigned irq)
616 struct sih_agent *sih = get_irq_chip_data(irq);
619 spin_lock_irqsave(&sih_agent_lock, flags);
620 sih->imr &= ~BIT(irq - sih->irq_base);
621 sih->imr_change_pending = true;
622 queue_work(wq, &sih->mask_work);
623 spin_unlock_irqrestore(&sih_agent_lock, flags);
626 static int twl4030_sih_set_type(unsigned irq, unsigned trigger)
628 struct sih_agent *sih = get_irq_chip_data(irq);
629 struct irq_desc *desc = irq_to_desc(irq);
633 pr_err("twl4030: Invalid IRQ: %d\n", irq);
637 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
640 spin_lock_irqsave(&sih_agent_lock, flags);
641 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
642 desc->status &= ~IRQ_TYPE_SENSE_MASK;
643 desc->status |= trigger;
644 sih->edge_change |= BIT(irq - sih->irq_base);
645 queue_work(wq, &sih->edge_work);
647 spin_unlock_irqrestore(&sih_agent_lock, flags);
651 static struct irq_chip twl4030_sih_irq_chip = {
653 .mask = twl4030_sih_mask,
654 .unmask = twl4030_sih_unmask,
655 .set_type = twl4030_sih_set_type,
658 /*----------------------------------------------------------------------*/
660 static inline int sih_read_isr(const struct sih *sih)
668 /* FIXME need retry-on-error ... */
671 status = twl_i2c_read(sih->module, isr.bytes,
672 sih->mask[irq_line].isr_offset, sih->bytes_ixr);
674 return (status < 0) ? status : le32_to_cpu(isr.word);
678 * Generic handler for SIH interrupts ... we "know" this is called
679 * in task context, with IRQs enabled.
681 static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
683 struct sih_agent *agent = get_irq_data(irq);
684 const struct sih *sih = agent->sih;
687 /* reading ISR acks the IRQs, using clear-on-read mode */
689 isr = sih_read_isr(sih);
693 pr_err("twl4030: %s SIH, read ISR error %d\n",
695 /* REVISIT: recover; eventually mask it all, etc */
705 generic_handle_irq(agent->irq_base + irq);
707 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
712 static unsigned twl4030_irq_next;
714 /* returns the first IRQ used by this SIH bank,
717 int twl4030_sih_setup(int module)
720 const struct sih *sih = NULL;
721 struct sih_agent *agent;
723 int status = -EINVAL;
724 unsigned irq_base = twl4030_irq_next;
726 /* only support modules with standard clear-on-read for now */
727 for (sih_mod = 0, sih = sih_modules;
728 sih_mod < nr_sih_modules;
730 if (sih->module == module && sih->set_cor) {
731 if (!WARN((irq_base + sih->bits) > NR_IRQS,
732 "irq %d for %s too big\n",
733 irq_base + sih->bits,
742 agent = kzalloc(sizeof *agent, GFP_KERNEL);
748 agent->irq_base = irq_base;
751 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask);
752 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge);
754 for (i = 0; i < sih->bits; i++) {
757 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip,
759 set_irq_chip_data(irq, agent);
764 twl4030_irq_next += i;
766 /* replace generic PIH handler (handle_simple_irq) */
767 irq = sih_mod + twl4030_irq_base;
768 set_irq_data(irq, agent);
769 set_irq_chained_handler(irq, handle_twl4030_sih);
771 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
772 irq, irq_base, twl4030_irq_next - 1);
777 /* FIXME need a call to reverse twl4030_sih_setup() ... */
780 /*----------------------------------------------------------------------*/
782 /* FIXME pass in which interrupt line we'll use ... */
783 #define twl_irq_line 0
785 int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
787 static struct irq_chip twl4030_irq_chip;
791 struct task_struct *task;
794 * Mask and clear all TWL4030 interrupts since initially we do
795 * not have any TWL4030 module interrupt handlers present
797 status = twl4030_init_sih_modules(twl_irq_line);
801 wq = create_singlethread_workqueue("twl4030-irqchip");
803 pr_err("twl4030: workqueue FAIL\n");
807 twl4030_irq_base = irq_base;
809 /* install an irq handler for each of the SIH modules;
810 * clone dummy irq_chip since PIH can't *do* anything
812 twl4030_irq_chip = dummy_irq_chip;
813 twl4030_irq_chip.name = "twl4030";
815 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
817 for (i = irq_base; i < irq_end; i++) {
818 set_irq_chip_and_handler(i, &twl4030_irq_chip,
822 twl4030_irq_next = i;
823 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
824 irq_num, irq_base, twl4030_irq_next - 1);
826 /* ... and the PWR_INT module ... */
827 status = twl4030_sih_setup(TWL4030_MODULE_INT);
829 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
833 /* install an irq handler to demultiplex the TWL4030 interrupt */
836 init_completion(&irq_event);
838 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED,
839 "TWL4030-PIH", &irq_event);
841 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
845 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num,
848 pr_err("twl4030: could not create irq %d thread!\n", irq_num);
849 status = PTR_ERR(task);
854 free_irq(irq_num, &irq_event);
856 /* clean up twl4030_sih_setup */
858 for (i = irq_base; i < irq_end; i++)
859 set_irq_chip_and_handler(i, NULL, NULL);
860 destroy_workqueue(wq);
865 int twl4030_exit_irq(void)
867 /* FIXME undo twl_init_irq() */
868 if (twl4030_irq_base) {
869 pr_err("twl4030: can't yet clean up IRQs?\n");
875 int twl4030_init_chip_irq(const char *chip)
877 if (!strcmp(chip, "twl5031")) {
878 sih_modules = sih_modules_twl5031;
879 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
881 sih_modules = sih_modules_twl4030;
882 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);