2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
4 * Copyright 2009 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/irq.h>
19 #include <linux/mfd/core.h>
20 #include <linux/interrupt.h>
22 #include <linux/mfd/wm831x/core.h>
23 #include <linux/mfd/wm831x/pdata.h>
24 #include <linux/mfd/wm831x/gpio.h>
25 #include <linux/mfd/wm831x/irq.h>
27 #include <linux/delay.h>
29 struct wm831x_irq_data {
35 static struct wm831x_irq_data wm831x_irqs[] = {
36 [WM831X_IRQ_TEMP_THW] = {
37 .primary = WM831X_TEMP_INT,
39 .mask = WM831X_TEMP_THW_EINT,
41 [WM831X_IRQ_GPIO_1] = {
42 .primary = WM831X_GP_INT,
44 .mask = WM831X_GP1_EINT,
46 [WM831X_IRQ_GPIO_2] = {
47 .primary = WM831X_GP_INT,
49 .mask = WM831X_GP2_EINT,
51 [WM831X_IRQ_GPIO_3] = {
52 .primary = WM831X_GP_INT,
54 .mask = WM831X_GP3_EINT,
56 [WM831X_IRQ_GPIO_4] = {
57 .primary = WM831X_GP_INT,
59 .mask = WM831X_GP4_EINT,
61 [WM831X_IRQ_GPIO_5] = {
62 .primary = WM831X_GP_INT,
64 .mask = WM831X_GP5_EINT,
66 [WM831X_IRQ_GPIO_6] = {
67 .primary = WM831X_GP_INT,
69 .mask = WM831X_GP6_EINT,
71 [WM831X_IRQ_GPIO_7] = {
72 .primary = WM831X_GP_INT,
74 .mask = WM831X_GP7_EINT,
76 [WM831X_IRQ_GPIO_8] = {
77 .primary = WM831X_GP_INT,
79 .mask = WM831X_GP8_EINT,
81 [WM831X_IRQ_GPIO_9] = {
82 .primary = WM831X_GP_INT,
84 .mask = WM831X_GP9_EINT,
86 [WM831X_IRQ_GPIO_10] = {
87 .primary = WM831X_GP_INT,
89 .mask = WM831X_GP10_EINT,
91 [WM831X_IRQ_GPIO_11] = {
92 .primary = WM831X_GP_INT,
94 .mask = WM831X_GP11_EINT,
96 [WM831X_IRQ_GPIO_12] = {
97 .primary = WM831X_GP_INT,
99 .mask = WM831X_GP12_EINT,
101 [WM831X_IRQ_GPIO_13] = {
102 .primary = WM831X_GP_INT,
104 .mask = WM831X_GP13_EINT,
106 [WM831X_IRQ_GPIO_14] = {
107 .primary = WM831X_GP_INT,
109 .mask = WM831X_GP14_EINT,
111 [WM831X_IRQ_GPIO_15] = {
112 .primary = WM831X_GP_INT,
114 .mask = WM831X_GP15_EINT,
116 [WM831X_IRQ_GPIO_16] = {
117 .primary = WM831X_GP_INT,
119 .mask = WM831X_GP16_EINT,
122 .primary = WM831X_ON_PIN_INT,
124 .mask = WM831X_ON_PIN_EINT,
126 [WM831X_IRQ_PPM_SYSLO] = {
127 .primary = WM831X_PPM_INT,
129 .mask = WM831X_PPM_SYSLO_EINT,
131 [WM831X_IRQ_PPM_PWR_SRC] = {
132 .primary = WM831X_PPM_INT,
134 .mask = WM831X_PPM_PWR_SRC_EINT,
136 [WM831X_IRQ_PPM_USB_CURR] = {
137 .primary = WM831X_PPM_INT,
139 .mask = WM831X_PPM_USB_CURR_EINT,
141 [WM831X_IRQ_WDOG_TO] = {
142 .primary = WM831X_WDOG_INT,
144 .mask = WM831X_WDOG_TO_EINT,
146 [WM831X_IRQ_RTC_PER] = {
147 .primary = WM831X_RTC_INT,
149 .mask = WM831X_RTC_PER_EINT,
151 [WM831X_IRQ_RTC_ALM] = {
152 .primary = WM831X_RTC_INT,
154 .mask = WM831X_RTC_ALM_EINT,
156 [WM831X_IRQ_CHG_BATT_HOT] = {
157 .primary = WM831X_CHG_INT,
159 .mask = WM831X_CHG_BATT_HOT_EINT,
161 [WM831X_IRQ_CHG_BATT_COLD] = {
162 .primary = WM831X_CHG_INT,
164 .mask = WM831X_CHG_BATT_COLD_EINT,
166 [WM831X_IRQ_CHG_BATT_FAIL] = {
167 .primary = WM831X_CHG_INT,
169 .mask = WM831X_CHG_BATT_FAIL_EINT,
171 [WM831X_IRQ_CHG_OV] = {
172 .primary = WM831X_CHG_INT,
174 .mask = WM831X_CHG_OV_EINT,
176 [WM831X_IRQ_CHG_END] = {
177 .primary = WM831X_CHG_INT,
179 .mask = WM831X_CHG_END_EINT,
181 [WM831X_IRQ_CHG_TO] = {
182 .primary = WM831X_CHG_INT,
184 .mask = WM831X_CHG_TO_EINT,
186 [WM831X_IRQ_CHG_MODE] = {
187 .primary = WM831X_CHG_INT,
189 .mask = WM831X_CHG_MODE_EINT,
191 [WM831X_IRQ_CHG_START] = {
192 .primary = WM831X_CHG_INT,
194 .mask = WM831X_CHG_START_EINT,
196 [WM831X_IRQ_TCHDATA] = {
197 .primary = WM831X_TCHDATA_INT,
199 .mask = WM831X_TCHDATA_EINT,
201 [WM831X_IRQ_TCHPD] = {
202 .primary = WM831X_TCHPD_INT,
204 .mask = WM831X_TCHPD_EINT,
206 [WM831X_IRQ_AUXADC_DATA] = {
207 .primary = WM831X_AUXADC_INT,
209 .mask = WM831X_AUXADC_DATA_EINT,
211 [WM831X_IRQ_AUXADC_DCOMP1] = {
212 .primary = WM831X_AUXADC_INT,
214 .mask = WM831X_AUXADC_DCOMP1_EINT,
216 [WM831X_IRQ_AUXADC_DCOMP2] = {
217 .primary = WM831X_AUXADC_INT,
219 .mask = WM831X_AUXADC_DCOMP2_EINT,
221 [WM831X_IRQ_AUXADC_DCOMP3] = {
222 .primary = WM831X_AUXADC_INT,
224 .mask = WM831X_AUXADC_DCOMP3_EINT,
226 [WM831X_IRQ_AUXADC_DCOMP4] = {
227 .primary = WM831X_AUXADC_INT,
229 .mask = WM831X_AUXADC_DCOMP4_EINT,
232 .primary = WM831X_CS_INT,
234 .mask = WM831X_CS1_EINT,
237 .primary = WM831X_CS_INT,
239 .mask = WM831X_CS2_EINT,
241 [WM831X_IRQ_HC_DC1] = {
242 .primary = WM831X_HC_INT,
244 .mask = WM831X_HC_DC1_EINT,
246 [WM831X_IRQ_HC_DC2] = {
247 .primary = WM831X_HC_INT,
249 .mask = WM831X_HC_DC2_EINT,
251 [WM831X_IRQ_UV_LDO1] = {
252 .primary = WM831X_UV_INT,
254 .mask = WM831X_UV_LDO1_EINT,
256 [WM831X_IRQ_UV_LDO2] = {
257 .primary = WM831X_UV_INT,
259 .mask = WM831X_UV_LDO2_EINT,
261 [WM831X_IRQ_UV_LDO3] = {
262 .primary = WM831X_UV_INT,
264 .mask = WM831X_UV_LDO3_EINT,
266 [WM831X_IRQ_UV_LDO4] = {
267 .primary = WM831X_UV_INT,
269 .mask = WM831X_UV_LDO4_EINT,
271 [WM831X_IRQ_UV_LDO5] = {
272 .primary = WM831X_UV_INT,
274 .mask = WM831X_UV_LDO5_EINT,
276 [WM831X_IRQ_UV_LDO6] = {
277 .primary = WM831X_UV_INT,
279 .mask = WM831X_UV_LDO6_EINT,
281 [WM831X_IRQ_UV_LDO7] = {
282 .primary = WM831X_UV_INT,
284 .mask = WM831X_UV_LDO7_EINT,
286 [WM831X_IRQ_UV_LDO8] = {
287 .primary = WM831X_UV_INT,
289 .mask = WM831X_UV_LDO8_EINT,
291 [WM831X_IRQ_UV_LDO9] = {
292 .primary = WM831X_UV_INT,
294 .mask = WM831X_UV_LDO9_EINT,
296 [WM831X_IRQ_UV_LDO10] = {
297 .primary = WM831X_UV_INT,
299 .mask = WM831X_UV_LDO10_EINT,
301 [WM831X_IRQ_UV_DC1] = {
302 .primary = WM831X_UV_INT,
304 .mask = WM831X_UV_DC1_EINT,
306 [WM831X_IRQ_UV_DC2] = {
307 .primary = WM831X_UV_INT,
309 .mask = WM831X_UV_DC2_EINT,
311 [WM831X_IRQ_UV_DC3] = {
312 .primary = WM831X_UV_INT,
314 .mask = WM831X_UV_DC3_EINT,
316 [WM831X_IRQ_UV_DC4] = {
317 .primary = WM831X_UV_INT,
319 .mask = WM831X_UV_DC4_EINT,
323 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
325 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
328 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
331 return &wm831x_irqs[irq - wm831x->irq_base];
334 static void wm831x_irq_lock(struct irq_data *data)
336 struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
338 mutex_lock(&wm831x->irq_lock);
341 static void wm831x_irq_sync_unlock(struct irq_data *data)
343 struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
346 for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
347 if (wm831x->gpio_update[i]) {
348 wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
349 WM831X_GPN_INT_MODE | WM831X_GPN_POL,
350 wm831x->gpio_update[i]);
351 wm831x->gpio_update[i] = 0;
355 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
356 /* If there's been a change in the mask write it back
357 * to the hardware. */
358 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
359 dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
360 WM831X_INTERRUPT_STATUS_1_MASK + i,
361 wm831x->irq_masks_cur[i]);
363 wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
364 wm831x_reg_write(wm831x,
365 WM831X_INTERRUPT_STATUS_1_MASK + i,
366 wm831x->irq_masks_cur[i]);
370 mutex_unlock(&wm831x->irq_lock);
373 static void wm831x_irq_enable(struct irq_data *data)
375 struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
376 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
379 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
382 static void wm831x_irq_disable(struct irq_data *data)
384 struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
385 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
388 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
391 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
393 struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
396 irq = data->irq - wm831x->irq_base;
398 if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
399 /* Ignore internal-only IRQs */
400 if (irq >= 0 && irq < WM831X_NUM_IRQS)
406 /* Rebase the IRQ into the GPIO range so we've got a sensible array
409 irq -= WM831X_IRQ_GPIO_1;
411 /* We set the high bit to flag that we need an update; don't
412 * do the update here as we can be called with the bus lock
416 case IRQ_TYPE_EDGE_BOTH:
417 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
418 wm831x->gpio_level[irq] = false;
420 case IRQ_TYPE_EDGE_RISING:
421 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
422 wm831x->gpio_level[irq] = false;
424 case IRQ_TYPE_EDGE_FALLING:
425 wm831x->gpio_update[irq] = 0x10000;
426 wm831x->gpio_level[irq] = false;
428 case IRQ_TYPE_LEVEL_HIGH:
429 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
430 wm831x->gpio_level[irq] = true;
439 static struct irq_chip wm831x_irq_chip = {
441 .irq_bus_lock = wm831x_irq_lock,
442 .irq_bus_sync_unlock = wm831x_irq_sync_unlock,
443 .irq_disable = wm831x_irq_disable,
444 .irq_enable = wm831x_irq_enable,
445 .irq_set_type = wm831x_irq_set_type,
448 /* The processing of the primary interrupt occurs in a thread so that
449 * we can interact with the device over I2C or SPI. */
450 static irqreturn_t wm831x_irq_thread(int irq, void *data)
452 struct wm831x *wm831x = data;
454 int primary, status_addr, ret;
455 int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
456 int read[WM831X_NUM_IRQ_REGS] = { 0 };
459 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
461 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
466 /* The touch interrupts are visible in the primary register as
467 * an optimisation; open code this to avoid complicating the
468 * main handling loop and so we can also skip iterating the
471 if (primary & WM831X_TCHPD_INT)
472 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
473 if (primary & WM831X_TCHDATA_INT)
474 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
475 primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
477 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
478 int offset = wm831x_irqs[i].reg - 1;
480 if (!(primary & wm831x_irqs[i].primary))
483 status = &status_regs[offset];
485 /* Hopefully there should only be one register to read
486 * each time otherwise we ought to do a block read. */
488 status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
490 *status = wm831x_reg_read(wm831x, status_addr);
493 "Failed to read IRQ status: %d\n",
500 /* Ignore any bits that we don't think are masked */
501 *status &= ~wm831x->irq_masks_cur[offset];
503 /* Acknowledge now so we don't miss
504 * notifications while we handle.
506 wm831x_reg_write(wm831x, status_addr, *status);
509 if (*status & wm831x_irqs[i].mask)
510 handle_nested_irq(wm831x->irq_base + i);
512 /* Simulate an edge triggered IRQ by polling the input
513 * status. This is sucky but improves interoperability.
515 if (primary == WM831X_GP_INT &&
516 wm831x->gpio_level[i - WM831X_IRQ_GPIO_1]) {
517 ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
518 while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
519 handle_nested_irq(wm831x->irq_base + i);
520 ret = wm831x_reg_read(wm831x,
530 int wm831x_irq_init(struct wm831x *wm831x, int irq)
532 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
535 mutex_init(&wm831x->irq_lock);
537 /* Mask the individual interrupt sources */
538 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
539 wm831x->irq_masks_cur[i] = 0xffff;
540 wm831x->irq_masks_cache[i] = 0xffff;
541 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
545 /* Try to dynamically allocate IRQs if no base is specified */
546 if (!pdata || !pdata->irq_base)
547 wm831x->irq_base = -1;
549 wm831x->irq_base = pdata->irq_base;
551 wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0,
553 if (wm831x->irq_base < 0) {
554 dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
556 wm831x->irq_base = 0;
560 if (pdata && pdata->irq_cmos)
565 wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
568 /* Try to flag /IRQ as a wake source; there are a number of
569 * unconditional wake sources in the PMIC so this isn't
570 * conditional but we don't actually care *too* much if it
573 ret = enable_irq_wake(irq);
575 dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
581 /* Register them with genirq */
582 for (cur_irq = wm831x->irq_base;
583 cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
585 irq_set_chip_data(cur_irq, wm831x);
586 irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
588 irq_set_nested_thread(cur_irq, 1);
590 /* ARM needs us to explicitly flag the IRQ as valid
591 * and will set them noprobe when we do so. */
593 set_irq_flags(cur_irq, IRQF_VALID);
595 irq_set_noprobe(cur_irq);
600 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
601 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
604 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
609 dev_warn(wm831x->dev,
610 "No interrupt specified - functionality limited\n");
613 /* Enable top level interrupts, we mask at secondary level */
614 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
619 void wm831x_irq_exit(struct wm831x *wm831x)
622 free_irq(wm831x->irq, wm831x);