2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
13 #include <linux/interrupt.h>
14 #include <linux/semaphore.h>
15 #include <linux/device.h>
16 #include <linux/types.h>
17 #include <linux/cdev.h>
18 #include <linux/pid.h>
20 #include <linux/pci.h>
22 #include <asm/cputable.h>
25 #include <misc/cxl-base.h>
28 #include <uapi/misc/cxl.h>
30 extern uint cxl_verbose;
35 * Bump version each time a user API change is made, whether it is
36 * backwards compatible ot not.
38 #define CXL_API_VERSION 3
39 #define CXL_API_VERSION_COMPATIBLE 1
42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
44 * At the end of the day, I'm not married to using typedef here, but it might
45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
48 * I'm quite happy if these are changed back to #defines before upstreaming, it
49 * should be little more than a regexp search+replace operation in this file.
60 #define cxl_reg_off(reg) \
63 /* Memory maps. Ref CXL Appendix A */
65 /* PSL Privilege 1 Memory Map */
66 /* Configuration and Control area - CAIA 1&2 */
67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
70 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
73 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
74 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
76 /* PSL Lookaside Buffer Management Area - CAIA 1 */
77 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
78 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
79 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
80 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
81 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
82 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
84 /* 0x00C0:7EFF Implementation dependent area */
85 /* PSL registers - CAIA 1 */
86 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
87 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
88 static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
89 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
96 /* XSL registers (Mellanox CX4) */
97 static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
98 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
99 static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
100 static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
101 /* PSL registers - CAIA 2 */
102 static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
103 static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
104 static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
105 static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};
106 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
107 static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
108 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
109 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
110 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
111 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
112 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
113 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
114 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
115 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
116 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
117 static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
119 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
120 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
122 /* PSL Slice Privilege 1 Memory Map */
123 /* Configuration Area - CAIA 1&2 */
124 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
125 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
126 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
127 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
128 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
129 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
130 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
131 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
132 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
133 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
134 /* Pointer Area - CAIA 1&2 */
135 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
136 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
137 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
138 /* Control Area - CAIA 1&2 */
139 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
140 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
141 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
142 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
143 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
144 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
145 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
146 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
147 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
148 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
149 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
150 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
152 /* PSL Slice Privilege 2 Memory Map */
153 /* Configuration and Control Area - CAIA 1&2 */
154 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
155 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
156 /* Configuration and Control Area - CAIA 1 */
157 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
158 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
159 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
160 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
161 /* Configuration and Control Area - CAIA 1 */
162 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
163 /* Segment Lookaside Buffer Management - CAIA 1 */
164 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
165 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
166 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
167 /* Interrupt Registers - CAIA 1&2 */
168 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
169 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
170 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
171 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
172 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
173 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
174 /* AFU Registers - CAIA 1&2 */
175 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
176 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
177 /* Work Element Descriptor - CAIA 1&2 */
178 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
179 /* 0x0C0:FFF Implementation Dependent Area */
181 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
182 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
183 #define CXL_PSL_SPAP_Size_Shift 4
184 #define CXL_PSL_SPAP_V 0x0000000000000001ULL
186 /****** CXL_PSL_Control ****************************************************/
187 #define CXL_PSL_Control_tb (0x1ull << (63-63))
188 #define CXL_PSL_Control_Fr (0x1ull << (63-31))
189 #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
190 #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
192 /****** CXL_PSL_DLCNTL *****************************************************/
193 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
194 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
195 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
196 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
197 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
198 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
200 /****** CXL_PSL_SR_An ******************************************************/
201 #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
202 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
203 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
204 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
205 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
206 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
207 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
208 #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
209 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
210 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
211 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
212 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
213 #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
214 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
215 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
217 /****** CXL_PSL_ID_An ****************************************************/
218 #define CXL_PSL_ID_An_F (1ull << (63-31))
219 #define CXL_PSL_ID_An_L (1ull << (63-30))
221 /****** CXL_PSL_SERR_An ****************************************************/
222 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
223 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
224 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
225 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
226 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
227 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
228 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
229 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
230 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
231 #define CXL_PSL_SERR_An_IRQS ( \
232 CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
233 CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
234 CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
235 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
236 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
237 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
238 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
239 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
240 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
241 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
242 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
243 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
244 #define CXL_PSL_SERR_An_IRQ_MASKS ( \
245 CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
246 CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
247 CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
249 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
251 /****** CXL_PSL_SCNTL_An ****************************************************/
252 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
253 /* Programming Modes: */
254 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
255 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
256 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
257 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
258 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
259 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
260 /* Purge Status (ro) */
261 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
262 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
263 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
265 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
266 /* Suspend Status (ro) */
267 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
268 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
269 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
270 /* Suspend Control */
271 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
273 /* AFU Slice Enable Status (ro) */
274 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
275 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
276 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
277 /* AFU Slice Enable */
278 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
279 /* AFU Slice Reset status (ro) */
280 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
281 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
282 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
283 /* AFU Slice Reset */
284 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
286 /****** CXL_SSTP0/1_An ******************************************************/
287 /* These top bits are for the segment that CONTAINS the segment table */
288 #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
289 #define CXL_SSTP0_An_KS (1ull << (63-2))
290 #define CXL_SSTP0_An_KP (1ull << (63-3))
291 #define CXL_SSTP0_An_N (1ull << (63-4))
292 #define CXL_SSTP0_An_L (1ull << (63-5))
293 #define CXL_SSTP0_An_C (1ull << (63-6))
294 #define CXL_SSTP0_An_TA (1ull << (63-7))
295 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
296 /* And finally, the virtual address & size of the segment table: */
297 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
298 #define CXL_SSTP0_An_SegTableSize_MASK \
299 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
300 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
301 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
302 #define CXL_SSTP1_An_V (1ull << (63-63))
304 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
306 #define CXL_SLBIE_C PPC_BIT(36) /* Class */
307 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
308 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
309 #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
311 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
312 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
314 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
315 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */
317 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
318 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
319 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
320 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
322 /****** CXL_PSL_AFUSEL ******************************************************/
323 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
325 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
326 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
327 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
328 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
329 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
330 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
331 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
332 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
333 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
334 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
335 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
336 #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
337 #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
338 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
339 #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
340 #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
342 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
343 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
344 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
345 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
346 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
347 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
348 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
350 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
351 * Status (0:7) Encoding
353 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
354 #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */
355 #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */
356 #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */
357 #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */
358 #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */
359 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */
361 /****** CXL_PSL_TFC_An ******************************************************/
362 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
363 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
364 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
365 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
367 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
368 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
369 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
370 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
371 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
372 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
373 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
375 /* cxl_process_element->software_status */
376 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
377 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
378 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
379 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
381 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
382 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
383 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
384 * of the hang pulse frequency.
386 #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
388 /* SPA->sw_command_status */
389 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
390 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
391 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
392 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
393 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
394 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
395 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
396 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
397 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
398 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
399 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
400 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
401 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
402 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
403 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
404 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
406 #define CXL_MAX_SLICES 4
407 #define MAX_AFU_MMIO_REGS 3
409 #define CXL_MODE_TIME_SLICED 0x4
410 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
412 #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
413 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
414 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
416 enum cxl_context_status {
422 enum prefault_modes {
430 CXL_AFU_MASTER_ATTRS,
439 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
440 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
442 struct cxl_afu_native {
443 void __iomem *p1n_mmio;
444 void __iomem *afu_desc_mmio;
445 irq_hw_number_t psl_hwirq;
446 unsigned int psl_virq;
447 struct mutex spa_mutex;
449 * Only the first part of the SPA is used for the process element
450 * linked list. The only other part that software needs to worry about
451 * is sw_command_status, which we store a separate pointer to.
452 * Everything else in the SPA is only used by hardware
454 struct cxl_process_element *spa;
455 __be64 *sw_command_status;
456 unsigned int spa_size;
462 struct cxl_afu_guest {
463 struct cxl_afu *parent;
465 phys_addr_t p2n_phys;
469 struct delayed_work work_err;
474 struct cxl_afu_native *native;
475 struct cxl_afu_guest *guest;
476 irq_hw_number_t serr_hwirq;
477 unsigned int serr_virq;
480 void __iomem *p2n_mmio;
481 phys_addr_t psn_phys;
486 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
487 struct device *chardev_s, *chardev_m, *chardev_d;
488 struct idr contexts_idr;
489 struct dentry *debugfs;
490 struct mutex contexts_lock;
491 spinlock_t afu_cntl_lock;
493 /* -1: AFU deconfigured/locked, >= 0: number of readers */
494 atomic_t configured_state;
496 /* AFU error buffer fields and bin attribute for sysfs */
497 u64 eb_len, eb_offset;
498 struct bin_attribute attr_eb;
500 /* pointer to the vphb */
501 struct pci_controller *phb;
506 int max_procs_virtualised;
513 struct list_head crs;
514 enum prefault_modes prefault_mode;
521 struct cxl_irq_name {
522 struct list_head list;
527 irq_hw_number_t offset;
528 irq_hw_number_t range;
529 unsigned long *bitmap;
533 * This is a cxl context. If the PSL is in dedicated mode, there will be one
534 * of these per AFU. If in AFU directed there can be lots of these.
539 /* Problem state MMIO */
540 phys_addr_t psn_phys;
543 /* Used to unmap any mmaps when force detaching */
544 struct address_space *mapping;
545 struct mutex mapping_lock;
546 struct page *ff_page;
550 spinlock_t sste_lock; /* Protects segment table entries */
551 struct cxl_sste *sstp;
553 unsigned int sst_size, sst_lru;
555 wait_queue_head_t wq;
556 /* use mm context associated with this pid for ds faults */
558 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
559 /* Only used in PR mode */
562 /* driver private data */
565 unsigned long *irq_bitmap; /* Accessed from IRQ context */
566 struct cxl_irq_ranges irqs;
567 struct list_head irq_names;
573 * This status and it's lock pretects start and detach context
574 * from racing. It also prevents detach from racing with
577 enum cxl_context_status status;
578 struct mutex status_mutex;
581 /* XXX: Is it possible to need multiple work items at once? */
582 struct work_struct fault_work;
586 struct cxl_process_element *elem;
589 * pe is the process element handle, assigned by this driver when the
590 * context is initialized.
592 * external_pe is the PE shown outside of cxl.
593 * On bare-metal, pe=external_pe, because we decide what the handle is.
594 * In a guest, we only find out about the pe used by pHyp when the
595 * context is attached, and that's the value we want to report outside
608 bool pending_afu_err;
610 /* Used by AFU drivers for driver specific event delivery */
611 struct cxl_afu_driver_ops *afu_driver_ops;
612 atomic_t afu_driver_events;
617 * Only used when more interrupts are allocated via
618 * pci_enable_msix_range than are supported in the default context, to
619 * use additional contexts to overcome the limitation. i.e. Mellanox
622 struct list_head extra_irq_contexts;
624 struct mm_struct *mm;
629 struct cxl_service_layer_ops {
630 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
631 int (*invalidate_all)(struct cxl *adapter);
632 int (*afu_regs_init)(struct cxl_afu *afu);
633 int (*sanitise_afu_regs)(struct cxl_afu *afu);
634 int (*register_serr_irq)(struct cxl_afu *afu);
635 void (*release_serr_irq)(struct cxl_afu *afu);
636 irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
637 irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
638 int (*activate_dedicated_process)(struct cxl_afu *afu);
639 int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
640 int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
641 void (*update_dedicated_ivtes)(struct cxl_context *ctx);
642 void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
643 void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
644 void (*psl_irq_dump_registers)(struct cxl_context *ctx);
645 void (*err_irq_dump_registers)(struct cxl *adapter);
646 void (*debugfs_stop_trace)(struct cxl *adapter);
647 void (*write_timebase_ctrl)(struct cxl *adapter);
648 u64 (*timebase_read)(struct cxl *adapter);
650 bool needs_reset_before_disable;
656 void __iomem *p1_mmio;
657 void __iomem *p2_mmio;
658 irq_hw_number_t err_hwirq;
659 unsigned int err_virq;
661 const struct cxl_service_layer_ops *sl_ops;
665 struct platform_device *pdev;
668 irq_hw_number_t irq_base_offset;
669 struct irq_avail *irq_avail;
670 spinlock_t irq_alloc_lock;
675 u16 subsystem_vendor;
680 struct cxl_native *native;
681 struct cxl_guest *guest;
682 spinlock_t afu_list_lock;
683 struct cxl_afu *afu[CXL_MAX_SLICES];
685 struct dentry *trace;
686 struct dentry *psl_err_chk;
687 struct dentry *debugfs;
689 struct bin_attribute cxl_attr;
700 bool user_image_loaded;
701 bool perst_loads_image;
702 bool perst_select_user;
703 bool perst_same_image;
704 bool psl_timebase_synced;
707 * number of contexts mapped on to this card. Possible values are:
708 * >0: Number of contexts mapped and new one can be mapped.
709 * 0: No active contexts and new ones can be mapped.
710 * -1: No contexts mapped and new ones cannot be mapped.
712 atomic_t contexts_num;
715 int cxl_pci_alloc_one_irq(struct cxl *adapter);
716 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
717 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
718 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
719 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
720 int cxl_update_image_control(struct cxl *adapter);
721 int cxl_pci_reset(struct cxl *adapter);
722 void cxl_pci_release_afu(struct device *dev);
723 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
725 /* common == phyp + powernv - CAIA 1&2 */
726 struct cxl_process_element_common {
749 /* just powernv - CAIA 1&2 */
750 struct cxl_process_element {
754 __be64 sdr; /* CAIA 1 */
755 u8 reserved1[8]; /* CAIA 2 */
759 __be16 ivte_offsets[4];
760 __be16 ivte_ranges[4];
762 struct cxl_process_element_common common;
763 __be32 software_state;
766 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
768 struct pci_dev *pdev;
770 if (cpu_has_feature(CPU_FTR_HVMODE)) {
771 pdev = to_pci_dev(cxl->dev.parent);
772 return !pci_channel_offline(pdev);
777 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
779 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
780 return cxl->native->p1_mmio + cxl_reg_off(reg);
783 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
785 if (likely(cxl_adapter_link_ok(cxl, NULL)))
786 out_be64(_cxl_p1_addr(cxl, reg), val);
789 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
791 if (likely(cxl_adapter_link_ok(cxl, NULL)))
792 return in_be64(_cxl_p1_addr(cxl, reg));
797 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
799 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
800 return afu->native->p1n_mmio + cxl_reg_off(reg);
803 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
805 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
806 out_be64(_cxl_p1n_addr(afu, reg), val);
809 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
811 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
812 return in_be64(_cxl_p1n_addr(afu, reg));
817 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
819 return afu->p2n_mmio + cxl_reg_off(reg);
822 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
824 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
825 out_be64(_cxl_p2n_addr(afu, reg), val);
828 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
830 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
831 return in_be64(_cxl_p2n_addr(afu, reg));
836 static inline bool cxl_is_power8(void)
838 if ((pvr_version_is(PVR_POWER8E)) ||
839 (pvr_version_is(PVR_POWER8NVL)) ||
840 (pvr_version_is(PVR_POWER8)))
845 static inline bool cxl_is_power9(void)
847 /* intermediate solution */
848 if (!cxl_is_power8() &&
849 (cpu_has_feature(CPU_FTRS_POWER9) ||
850 cpu_has_feature(CPU_FTR_POWER9_DD1)))
855 static inline bool cxl_is_psl8(struct cxl_afu *afu)
857 if (afu->adapter->caia_major == 1)
862 static inline bool cxl_is_psl9(struct cxl_afu *afu)
864 if (afu->adapter->caia_major == 2)
869 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
870 loff_t off, size_t count);
872 /* Internal functions wrapped in cxl_base to allow PHB to call them */
873 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
874 void _cxl_pci_disable_device(struct pci_dev *dev);
875 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
876 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
877 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
880 void (*cxl_slbia)(struct mm_struct *mm);
881 bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
882 void (*cxl_pci_disable_device)(struct pci_dev *dev);
883 int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
884 int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
885 void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
887 struct module *owner;
889 int register_cxl_calls(struct cxl_calls *calls);
890 void unregister_cxl_calls(struct cxl_calls *calls);
891 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
893 void cxl_remove_adapter_nr(struct cxl *adapter);
895 void cxl_release_spa(struct cxl_afu *afu);
897 dev_t cxl_get_dev(void);
898 int cxl_file_init(void);
899 void cxl_file_exit(void);
900 int cxl_register_adapter(struct cxl *adapter);
901 int cxl_register_afu(struct cxl_afu *afu);
902 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
903 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
904 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
905 void cxl_chardev_afu_remove(struct cxl_afu *afu);
907 void cxl_context_detach_all(struct cxl_afu *afu);
908 void cxl_context_free(struct cxl_context *ctx);
909 void cxl_context_detach(struct cxl_context *ctx);
911 int cxl_sysfs_adapter_add(struct cxl *adapter);
912 void cxl_sysfs_adapter_remove(struct cxl *adapter);
913 int cxl_sysfs_afu_add(struct cxl_afu *afu);
914 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
915 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
916 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
918 struct cxl *cxl_alloc_adapter(void);
919 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
920 int cxl_afu_select_best_mode(struct cxl_afu *afu);
922 int cxl_native_register_psl_irq(struct cxl_afu *afu);
923 void cxl_native_release_psl_irq(struct cxl_afu *afu);
924 int cxl_native_register_psl_err_irq(struct cxl *adapter);
925 void cxl_native_release_psl_err_irq(struct cxl *adapter);
926 int cxl_native_register_serr_irq(struct cxl_afu *afu);
927 void cxl_native_release_serr_irq(struct cxl_afu *afu);
928 int afu_register_irqs(struct cxl_context *ctx, u32 count);
929 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
930 void afu_irq_name_free(struct cxl_context *ctx);
932 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
933 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
934 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
935 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
936 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
937 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
938 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
939 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
941 #ifdef CONFIG_DEBUG_FS
943 int cxl_debugfs_init(void);
944 void cxl_debugfs_exit(void);
945 int cxl_debugfs_adapter_add(struct cxl *adapter);
946 void cxl_debugfs_adapter_remove(struct cxl *adapter);
947 int cxl_debugfs_afu_add(struct cxl_afu *afu);
948 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
949 void cxl_stop_trace_psl9(struct cxl *cxl);
950 void cxl_stop_trace_psl8(struct cxl *cxl);
951 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
952 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
953 void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
954 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
955 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
957 #else /* CONFIG_DEBUG_FS */
959 static inline int __init cxl_debugfs_init(void)
964 static inline void cxl_debugfs_exit(void)
968 static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
973 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
977 static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
982 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
986 static inline void cxl_stop_trace_psl9(struct cxl *cxl)
990 static inline void cxl_stop_trace_psl8(struct cxl *cxl)
994 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
999 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
1004 static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,
1009 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
1013 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
1017 #endif /* CONFIG_DEBUG_FS */
1019 void cxl_handle_fault(struct work_struct *work);
1020 void cxl_prefault(struct cxl_context *ctx, u64 wed);
1022 struct cxl *get_cxl_adapter(int num);
1023 int cxl_alloc_sst(struct cxl_context *ctx);
1024 void cxl_dump_debug_buffer(void *addr, size_t size);
1026 void init_cxl_native(void);
1028 struct cxl_context *cxl_context_alloc(void);
1029 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
1030 void cxl_context_set_mapping(struct cxl_context *ctx,
1031 struct address_space *mapping);
1032 void cxl_context_free(struct cxl_context *ctx);
1033 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1034 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
1035 irq_handler_t handler, void *cookie, const char *name);
1036 void cxl_unmap_irq(unsigned int virq, void *cookie);
1037 int __detach_context(struct cxl_context *ctx);
1040 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
1042 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1043 * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1044 * PSL_TID_An register in the lower 32 bits.
1046 struct cxl_irq_info {
1054 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1057 void cxl_assign_psn_space(struct cxl_context *ctx);
1058 int cxl_invalidate_all_psl9(struct cxl *adapter);
1059 int cxl_invalidate_all_psl8(struct cxl *adapter);
1060 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1061 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1062 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1063 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1064 void *cookie, irq_hw_number_t *dest_hwirq,
1065 unsigned int *dest_virq, const char *name);
1067 int cxl_check_error(struct cxl_afu *afu);
1068 int cxl_afu_slbia(struct cxl_afu *afu);
1069 int cxl_data_cache_flush(struct cxl *adapter);
1070 int cxl_afu_disable(struct cxl_afu *afu);
1071 int cxl_psl_purge(struct cxl_afu *afu);
1073 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1074 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1075 void cxl_native_err_irq_dump_regs(struct cxl *adapter);
1076 int cxl_pci_vphb_add(struct cxl_afu *afu);
1077 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1078 void cxl_release_mapping(struct cxl_context *ctx);
1080 extern struct pci_driver cxl_pci_driver;
1081 extern struct platform_driver cxl_of_driver;
1082 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1084 int afu_open(struct inode *inode, struct file *file);
1085 int afu_release(struct inode *inode, struct file *file);
1086 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1087 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1088 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
1089 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1090 extern const struct file_operations afu_fops;
1092 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1093 void cxl_guest_remove_adapter(struct cxl *adapter);
1094 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1095 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1096 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1097 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1098 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1099 void cxl_guest_remove_afu(struct cxl_afu *afu);
1100 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1101 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1102 int cxl_guest_add_chardev(struct cxl *adapter);
1103 void cxl_guest_remove_chardev(struct cxl *adapter);
1104 void cxl_guest_reload_module(struct cxl *adapter);
1105 int cxl_of_probe(struct platform_device *pdev);
1107 struct cxl_backend_ops {
1108 struct module *module;
1109 int (*adapter_reset)(struct cxl *adapter);
1110 int (*alloc_one_irq)(struct cxl *adapter);
1111 void (*release_one_irq)(struct cxl *adapter, int hwirq);
1112 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1113 struct cxl *adapter, unsigned int num);
1114 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1115 struct cxl *adapter);
1116 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1118 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1119 u64 dsisr, u64 errstat);
1120 irqreturn_t (*psl_interrupt)(int irq, void *data);
1121 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1122 void (*irq_wait)(struct cxl_context *ctx);
1123 int (*attach_process)(struct cxl_context *ctx, bool kernel,
1125 int (*detach_process)(struct cxl_context *ctx);
1126 void (*update_ivtes)(struct cxl_context *ctx);
1127 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1128 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1129 void (*release_afu)(struct device *dev);
1130 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1131 loff_t off, size_t count);
1132 int (*afu_check_and_enable)(struct cxl_afu *afu);
1133 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1134 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1135 int (*afu_reset)(struct cxl_afu *afu);
1136 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1137 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1138 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1139 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1140 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1141 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1142 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1143 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1145 extern const struct cxl_backend_ops cxl_native_ops;
1146 extern const struct cxl_backend_ops cxl_guest_ops;
1147 extern const struct cxl_backend_ops *cxl_ops;
1149 /* check if the given pci_dev is on the the cxl vphb bus */
1150 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1152 /* decode AFU error bits in the PSL register PSL_SERR_An */
1153 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1156 * Increments the number of attached contexts on an adapter.
1157 * In case an adapter_context_lock is taken the return -EBUSY.
1159 int cxl_adapter_context_get(struct cxl *adapter);
1161 /* Decrements the number of attached contexts on an adapter */
1162 void cxl_adapter_context_put(struct cxl *adapter);
1164 /* If no active contexts then prevents contexts from being attached */
1165 int cxl_adapter_context_lock(struct cxl *adapter);
1167 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1168 void cxl_adapter_context_unlock(struct cxl *adapter);
1170 /* Increases the reference count to "struct mm_struct" */
1171 void cxl_context_mm_count_get(struct cxl_context *ctx);
1173 /* Decrements the reference count to "struct mm_struct" */
1174 void cxl_context_mm_count_put(struct cxl_context *ctx);