drivers/misc/cxl/native.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/spinlock.h>
  11 #include <linux/sched.h>
  12 #include <linux/sched/clock.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/mm.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/delay.h>
  18 #include <asm/synch.h>
  19 #include <misc/cxl-base.h>
  20
  21 #include "cxl.h"
  22 #include "trace.h"
  23
  24 static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
  25                        u64 result, u64 mask, bool enabled)
  26 {
  27         u64 AFU_Cntl;
  28         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
  29         int rc = 0;
  30
  31         spin_lock(&afu->afu_cntl_lock);
  32         pr_devel("AFU command starting: %llx\n", command);
  33
  34         trace_cxl_afu_ctrl(afu, command);
  35
  36         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  37         cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command);
  38
  39         AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  40         while ((AFU_Cntl & mask) != result) {
  41                 if (time_after_eq(jiffies, timeout)) {
  42                         dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
  43                         rc = -EBUSY;
  44                         goto out;
  45                 }
  46
  47                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
  48                         afu->enabled = enabled;
  49                         rc = -EIO;
  50                         goto out;
  51                 }
  52
  53                 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
  54                                      AFU_Cntl | command);
  55                 cpu_relax();
  56                 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
  57         }
  58
  59         if (AFU_Cntl & CXL_AFU_Cntl_An_RA) {
  60                 /*
  61                  * Workaround for a bug in the XSL used in the Mellanox CX4
  62                  * that fails to clear the RA bit after an AFU reset,
  63                  * preventing subsequent AFU resets from working.
  64                  */
  65                 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
  66         }
  67
  68         pr_devel("AFU command complete: %llx\n", command);
  69         afu->enabled = enabled;
  70 out:
  71         trace_cxl_afu_ctrl_done(afu, command, rc);
  72         spin_unlock(&afu->afu_cntl_lock);
  73
  74         return rc;
  75 }
  76
  77 static int afu_enable(struct cxl_afu *afu)
  78 {
  79         pr_devel("AFU enable request\n");
  80
  81         return afu_control(afu, CXL_AFU_Cntl_An_E, 0,
  82                            CXL_AFU_Cntl_An_ES_Enabled,
  83                            CXL_AFU_Cntl_An_ES_MASK, true);
  84 }
  85
  86 int cxl_afu_disable(struct cxl_afu *afu)
  87 {
  88         pr_devel("AFU disable request\n");
  89
  90         return afu_control(afu, 0, CXL_AFU_Cntl_An_E,
  91                            CXL_AFU_Cntl_An_ES_Disabled,
  92                            CXL_AFU_Cntl_An_ES_MASK, false);
  93 }
  94
  95 /* This will disable as well as reset */
  96 static int native_afu_reset(struct cxl_afu *afu)
  97 {
  98         int rc;
  99         u64 serr;
 100
 101         pr_devel("AFU reset request\n");
 102
 103         rc = afu_control(afu, CXL_AFU_Cntl_An_RA, 0,
 104                            CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
 105                            CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
 106                            false);
 107
 108         /* Re-enable any masked interrupts */
 109         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 110         serr &= ~CXL_PSL_SERR_An_IRQ_MASKS;
 111         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
 112
 113
 114         return rc;
 115 }
 116
 117 static int native_afu_check_and_enable(struct cxl_afu *afu)
 118 {
 119         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 120                 WARN(1, "Refusing to enable afu while link down!\n");
 121                 return -EIO;
 122         }
 123         if (afu->enabled)
 124                 return 0;
 125         return afu_enable(afu);
 126 }
 127
 128 int cxl_psl_purge(struct cxl_afu *afu)
 129 {
 130         u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 131         u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 132         u64 dsisr, dar;
 133         u64 start, end;
 134         u64 trans_fault = 0x0ULL;
 135         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 136         int rc = 0;
 137
 138         trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
 139
 140         pr_devel("PSL purge request\n");
 141
 142         if (cxl_is_psl8(afu))
 143                 trans_fault = CXL_PSL_DSISR_TRANS;
 144         if (cxl_is_psl9(afu))
 145                 trans_fault = CXL_PSL9_DSISR_An_TF;
 146
 147         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 148                 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
 149                 rc = -EIO;
 150                 goto out;
 151         }
 152
 153         if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 154                 WARN(1, "psl_purge request while AFU not disabled!\n");
 155                 cxl_afu_disable(afu);
 156         }
 157
 158         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 159                        PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
 160         start = local_clock();
 161         PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 162         while ((PSL_CNTL &  CXL_PSL_SCNTL_An_Ps_MASK)
 163                         == CXL_PSL_SCNTL_An_Ps_Pending) {
 164                 if (time_after_eq(jiffies, timeout)) {
 165                         dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
 166                         rc = -EBUSY;
 167                         goto out;
 168                 }
 169                 if (!cxl_ops->link_ok(afu->adapter, afu)) {
 170                         rc = -EIO;
 171                         goto out;
 172                 }
 173
 174                 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 175                 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx  PSL_DSISR: 0x%016llx\n",
 176                                      PSL_CNTL, dsisr);
 177
 178                 if (dsisr & trans_fault) {
 179                         dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
 180                         dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n",
 181                                    dsisr, dar);
 182                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 183                 } else if (dsisr) {
 184                         dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n",
 185                                    dsisr);
 186                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 187                 } else {
 188                         cpu_relax();
 189                 }
 190                 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
 191         }
 192         end = local_clock();
 193         pr_devel("PSL purged in %lld ns\n", end - start);
 194
 195         cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
 196                        PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
 197 out:
 198         trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
 199         return rc;
 200 }
 201
 202 static int spa_max_procs(int spa_size)
 203 {
 204         /*
 205          * From the CAIA:
 206          *    end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
 207          * Most of that junk is really just an overly-complicated way of saying
 208          * the last 256 bytes are __aligned(128), so it's really:
 209          *    end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
 210          * and
 211          *    end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
 212          * so
 213          *    sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
 214          * Ignore the alignment (which is safe in this case as long as we are
 215          * careful with our rounding) and solve for n:
 216          */
 217         return ((spa_size / 8) - 96) / 17;
 218 }
 219
 220 static int cxl_alloc_spa(struct cxl_afu *afu, int mode)
 221 {
 222         unsigned spa_size;
 223
 224         /* Work out how many pages to allocate */
 225         afu->native->spa_order = -1;
 226         do {
 227                 afu->native->spa_order++;
 228                 spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
 229
 230                 if (spa_size > 0x100000) {
 231                         dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
 232                                         afu->native->spa_max_procs, afu->native->spa_size);
 233                         if (mode != CXL_MODE_DEDICATED)
 234                                 afu->num_procs = afu->native->spa_max_procs;
 235                         break;
 236                 }
 237
 238                 afu->native->spa_size = spa_size;
 239                 afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
 240         } while (afu->native->spa_max_procs < afu->num_procs);
 241
 242         if (!(afu->native->spa = (struct cxl_process_element *)
 243               __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
 244                 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
 245                 return -ENOMEM;
 246         }
 247         pr_devel("spa pages: %i afu->spa_max_procs: %i   afu->num_procs: %i\n",
 248                  1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
 249
 250         return 0;
 251 }
 252
 253 static void attach_spa(struct cxl_afu *afu)
 254 {
 255         u64 spap;
 256
 257         afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
 258                                             ((afu->native->spa_max_procs + 3) * 128));
 259
 260         spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
 261         spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
 262         spap |= CXL_PSL_SPAP_V;
 263         pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n",
 264                 afu->native->spa, afu->native->spa_max_procs,
 265                 afu->native->sw_command_status, spap);
 266         cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
 267 }
 268
 269 static inline void detach_spa(struct cxl_afu *afu)
 270 {
 271         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
 272 }
 273
 274 void cxl_release_spa(struct cxl_afu *afu)
 275 {
 276         if (afu->native->spa) {
 277                 free_pages((unsigned long) afu->native->spa,
 278                         afu->native->spa_order);
 279                 afu->native->spa = NULL;
 280         }
 281 }
 282
 283 /*
 284  * Invalidation of all ERAT entries is no longer required by CAIA2. Use
 285  * only for debug.
 286  */
 287 int cxl_invalidate_all_psl9(struct cxl *adapter)
 288 {
 289         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 290         u64 ierat;
 291
 292         pr_devel("CXL adapter - invalidation of all ERAT entries\n");
 293
 294         /* Invalidates all ERAT entries for Radix or HPT */
 295         ierat = CXL_XSL9_IERAT_IALL;
 296         if (radix_enabled())
 297                 ierat |= CXL_XSL9_IERAT_INVR;
 298         cxl_p1_write(adapter, CXL_XSL9_IERAT, ierat);
 299
 300         while (cxl_p1_read(adapter, CXL_XSL9_IERAT) & CXL_XSL9_IERAT_IINPROG) {
 301                 if (time_after_eq(jiffies, timeout)) {
 302                         dev_warn(&adapter->dev,
 303                         "WARNING: CXL adapter invalidation of all ERAT entries timed out!\n");
 304                         return -EBUSY;
 305                 }
 306                 if (!cxl_ops->link_ok(adapter, NULL))
 307                         return -EIO;
 308                 cpu_relax();
 309         }
 310         return 0;
 311 }
 312
 313 int cxl_invalidate_all_psl8(struct cxl *adapter)
 314 {
 315         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 316
 317         pr_devel("CXL adapter wide TLBIA & SLBIA\n");
 318
 319         cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
 320
 321         cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
 322         while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
 323                 if (time_after_eq(jiffies, timeout)) {
 324                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
 325                         return -EBUSY;
 326                 }
 327                 if (!cxl_ops->link_ok(adapter, NULL))
 328                         return -EIO;
 329                 cpu_relax();
 330         }
 331
 332         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
 333         while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
 334                 if (time_after_eq(jiffies, timeout)) {
 335                         dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
 336                         return -EBUSY;
 337                 }
 338                 if (!cxl_ops->link_ok(adapter, NULL))
 339                         return -EIO;
 340                 cpu_relax();
 341         }
 342         return 0;
 343 }
 344
 345 int cxl_data_cache_flush(struct cxl *adapter)
 346 {
 347         u64 reg;
 348         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 349
 350         pr_devel("Flushing data cache\n");
 351
 352         reg = cxl_p1_read(adapter, CXL_PSL_Control);
 353         reg |= CXL_PSL_Control_Fr;
 354         cxl_p1_write(adapter, CXL_PSL_Control, reg);
 355
 356         reg = cxl_p1_read(adapter, CXL_PSL_Control);
 357         while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) {
 358                 if (time_after_eq(jiffies, timeout)) {
 359                         dev_warn(&adapter->dev, "WARNING: cache flush timed out!\n");
 360                         return -EBUSY;
 361                 }
 362
 363                 if (!cxl_ops->link_ok(adapter, NULL)) {
 364                         dev_warn(&adapter->dev, "WARNING: link down when flushing cache\n");
 365                         return -EIO;
 366                 }
 367                 cpu_relax();
 368                 reg = cxl_p1_read(adapter, CXL_PSL_Control);
 369         }
 370
 371         reg &= ~CXL_PSL_Control_Fr;
 372         cxl_p1_write(adapter, CXL_PSL_Control, reg);
 373         return 0;
 374 }
 375
 376 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
 377 {
 378         int rc;
 379
 380         /* 1. Disable SSTP by writing 0 to SSTP1[V] */
 381         cxl_p2n_write(afu, CXL_SSTP1_An, 0);
 382
 383         /* 2. Invalidate all SLB entries */
 384         if ((rc = cxl_afu_slbia(afu)))
 385                 return rc;
 386
 387         /* 3. Set SSTP0_An */
 388         cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
 389
 390         /* 4. Set SSTP1_An */
 391         cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
 392
 393         return 0;
 394 }
 395
 396 /* Using per slice version may improve performance here. (ie. SLBIA_An) */
 397 static void slb_invalid(struct cxl_context *ctx)
 398 {
 399         struct cxl *adapter = ctx->afu->adapter;
 400         u64 slbia;
 401
 402         WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
 403
 404         cxl_p1_write(adapter, CXL_PSL_LBISEL,
 405                         ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
 406                         be32_to_cpu(ctx->elem->lpid));
 407         cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
 408
 409         while (1) {
 410                 if (!cxl_ops->link_ok(adapter, NULL))
 411                         break;
 412                 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
 413                 if (!(slbia & CXL_TLB_SLB_P))
 414                         break;
 415                 cpu_relax();
 416         }
 417 }
 418
 419 static int do_process_element_cmd(struct cxl_context *ctx,
 420                                   u64 cmd, u64 pe_state)
 421 {
 422         u64 state;
 423         unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
 424         int rc = 0;
 425
 426         trace_cxl_llcmd(ctx, cmd);
 427
 428         WARN_ON(!ctx->afu->enabled);
 429
 430         ctx->elem->software_state = cpu_to_be32(pe_state);
 431         smp_wmb();
 432         *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
 433         smp_mb();
 434         cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
 435         while (1) {
 436                 if (time_after_eq(jiffies, timeout)) {
 437                         dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
 438                         rc = -EBUSY;
 439                         goto out;
 440                 }
 441                 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 442                         dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
 443                         rc = -EIO;
 444                         goto out;
 445                 }
 446                 state = be64_to_cpup(ctx->afu->native->sw_command_status);
 447                 if (state == ~0ULL) {
 448                         pr_err("cxl: Error adding process element to AFU\n");
 449                         rc = -1;
 450                         goto out;
 451                 }
 452                 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK  | CXL_SPA_SW_LINK_MASK)) ==
 453                     (cmd | (cmd >> 16) | ctx->pe))
 454                         break;
 455                 /*
 456                  * The command won't finish in the PSL if there are
 457                  * outstanding DSIs.  Hence we need to yield here in
 458                  * case there are outstanding DSIs that we need to
 459                  * service.  Tuning possiblity: we could wait for a
 460                  * while before sched
 461                  */
 462                 schedule();
 463
 464         }
 465 out:
 466         trace_cxl_llcmd_done(ctx, cmd, rc);
 467         return rc;
 468 }
 469
 470 static int add_process_element(struct cxl_context *ctx)
 471 {
 472         int rc = 0;
 473
 474         mutex_lock(&ctx->afu->native->spa_mutex);
 475         pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
 476         if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
 477                 ctx->pe_inserted = true;
 478         pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
 479         mutex_unlock(&ctx->afu->native->spa_mutex);
 480         return rc;
 481 }
 482
 483 static int terminate_process_element(struct cxl_context *ctx)
 484 {
 485         int rc = 0;
 486
 487         /* fast path terminate if it's already invalid */
 488         if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
 489                 return rc;
 490
 491         mutex_lock(&ctx->afu->native->spa_mutex);
 492         pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
 493         /* We could be asked to terminate when the hw is down. That
 494          * should always succeed: it's not running if the hw has gone
 495          * away and is being reset.
 496          */
 497         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 498                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
 499                                             CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
 500         ctx->elem->software_state = 0;  /* Remove Valid bit */
 501         pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
 502         mutex_unlock(&ctx->afu->native->spa_mutex);
 503         return rc;
 504 }
 505
 506 static int remove_process_element(struct cxl_context *ctx)
 507 {
 508         int rc = 0;
 509
 510         mutex_lock(&ctx->afu->native->spa_mutex);
 511         pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
 512
 513         /* We could be asked to remove when the hw is down. Again, if
 514          * the hw is down, the PE is gone, so we succeed.
 515          */
 516         if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
 517                 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
 518
 519         if (!rc)
 520                 ctx->pe_inserted = false;
 521         if (cxl_is_power8())
 522                 slb_invalid(ctx);
 523         pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
 524         mutex_unlock(&ctx->afu->native->spa_mutex);
 525
 526         return rc;
 527 }
 528
 529 void cxl_assign_psn_space(struct cxl_context *ctx)
 530 {
 531         if (!ctx->afu->pp_size || ctx->master) {
 532                 ctx->psn_phys = ctx->afu->psn_phys;
 533                 ctx->psn_size = ctx->afu->adapter->ps_size;
 534         } else {
 535                 ctx->psn_phys = ctx->afu->psn_phys +
 536                         (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
 537                 ctx->psn_size = ctx->afu->pp_size;
 538         }
 539 }
 540
 541 static int activate_afu_directed(struct cxl_afu *afu)
 542 {
 543         int rc;
 544
 545         dev_info(&afu->dev, "Activating AFU directed mode\n");
 546
 547         afu->num_procs = afu->max_procs_virtualised;
 548         if (afu->native->spa == NULL) {
 549                 if (cxl_alloc_spa(afu, CXL_MODE_DIRECTED))
 550                         return -ENOMEM;
 551         }
 552         attach_spa(afu);
 553
 554         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
 555         if (cxl_is_power8())
 556                 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 557         cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
 558
 559         afu->current_mode = CXL_MODE_DIRECTED;
 560
 561         if ((rc = cxl_chardev_m_afu_add(afu)))
 562                 return rc;
 563
 564         if ((rc = cxl_sysfs_afu_m_add(afu)))
 565                 goto err;
 566
 567         if ((rc = cxl_chardev_s_afu_add(afu)))
 568                 goto err1;
 569
 570         return 0;
 571 err1:
 572         cxl_sysfs_afu_m_remove(afu);
 573 err:
 574         cxl_chardev_afu_remove(afu);
 575         return rc;
 576 }
 577
 578 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 579 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
 580 #else
 581 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
 582 #endif
 583
 584 static u64 calculate_sr(struct cxl_context *ctx)
 585 {
 586         u64 sr = 0;
 587
 588         set_endian(sr);
 589         if (ctx->master)
 590                 sr |= CXL_PSL_SR_An_MP;
 591         if (mfspr(SPRN_LPCR) & LPCR_TC)
 592                 sr |= CXL_PSL_SR_An_TC;
 593         if (ctx->kernel) {
 594                 if (!ctx->real_mode)
 595                         sr |= CXL_PSL_SR_An_R;
 596                 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
 597         } else {
 598                 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
 599                 if (radix_enabled())
 600                         sr |= CXL_PSL_SR_An_HV;
 601                 else
 602                         sr &= ~(CXL_PSL_SR_An_HV);
 603                 if (!test_tsk_thread_flag(current, TIF_32BIT))
 604                         sr |= CXL_PSL_SR_An_SF;
 605         }
 606         if (cxl_is_psl9(ctx->afu)) {
 607                 if (radix_enabled())
 608                         sr |= CXL_PSL_SR_An_XLAT_ror;
 609                 else
 610                         sr |= CXL_PSL_SR_An_XLAT_hpt;
 611         }
 612         return sr;
 613 }
 614
 615 static void update_ivtes_directed(struct cxl_context *ctx)
 616 {
 617         bool need_update = (ctx->status == STARTED);
 618         int r;
 619
 620         if (need_update) {
 621                 WARN_ON(terminate_process_element(ctx));
 622                 WARN_ON(remove_process_element(ctx));
 623         }
 624
 625         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 626                 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
 627                 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
 628         }
 629
 630         /*
 631          * Theoretically we could use the update llcmd, instead of a
 632          * terminate/remove/add (or if an atomic update was required we could
 633          * do a suspend/update/resume), however it seems there might be issues
 634          * with the update llcmd on some cards (including those using an XSL on
 635          * an ASIC) so for now it's safest to go with the commands that are
 636          * known to work. In the future if we come across a situation where the
 637          * card may be performing transactions using the same PE while we are
 638          * doing this update we might need to revisit this.
 639          */
 640         if (need_update)
 641                 WARN_ON(add_process_element(ctx));
 642 }
 643
 644 static int process_element_entry_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 645 {
 646         u32 pid;
 647
 648         cxl_assign_psn_space(ctx);
 649
 650         ctx->elem->ctxtime = 0; /* disable */
 651         ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
 652         ctx->elem->haurp = 0; /* disable */
 653
 654         if (ctx->kernel)
 655                 pid = 0;
 656         else {
 657                 if (ctx->mm == NULL) {
 658                         pr_devel("%s: unable to get mm for pe=%d pid=%i\n",
 659                                 __func__, ctx->pe, pid_nr(ctx->pid));
 660                         return -EINVAL;
 661                 }
 662                 pid = ctx->mm->context.id;
 663         }
 664
 665         ctx->elem->common.tid = 0;
 666         ctx->elem->common.pid = cpu_to_be32(pid);
 667
 668         ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
 669
 670         ctx->elem->common.csrp = 0; /* disable */
 671
 672         cxl_prefault(ctx, wed);
 673
 674         /*
 675          * Ensure we have the multiplexed PSL interrupt set up to take faults
 676          * for kernel contexts that may not have allocated any AFU IRQs at all:
 677          */
 678         if (ctx->irqs.range[0] == 0) {
 679                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 680                 ctx->irqs.range[0] = 1;
 681         }
 682
 683         ctx->elem->common.amr = cpu_to_be64(amr);
 684         ctx->elem->common.wed = cpu_to_be64(wed);
 685
 686         return 0;
 687 }
 688
 689 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 690 {
 691         int result;
 692
 693         /* fill the process element entry */
 694         result = process_element_entry_psl9(ctx, wed, amr);
 695         if (result)
 696                 return result;
 697
 698         update_ivtes_directed(ctx);
 699
 700         /* first guy needs to enable */
 701         result = cxl_ops->afu_check_and_enable(ctx->afu);
 702         if (result)
 703                 return result;
 704
 705         return add_process_element(ctx);
 706 }
 707
 708 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 709 {
 710         u32 pid;
 711         int result;
 712
 713         cxl_assign_psn_space(ctx);
 714
 715         ctx->elem->ctxtime = 0; /* disable */
 716         ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
 717         ctx->elem->haurp = 0; /* disable */
 718         ctx->elem->u.sdr = cpu_to_be64(mfspr(SPRN_SDR1));
 719
 720         pid = current->pid;
 721         if (ctx->kernel)
 722                 pid = 0;
 723         ctx->elem->common.tid = 0;
 724         ctx->elem->common.pid = cpu_to_be32(pid);
 725
 726         ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
 727
 728         ctx->elem->common.csrp = 0; /* disable */
 729         ctx->elem->common.u.psl8.aurp0 = 0; /* disable */
 730         ctx->elem->common.u.psl8.aurp1 = 0; /* disable */
 731
 732         cxl_prefault(ctx, wed);
 733
 734         ctx->elem->common.u.psl8.sstp0 = cpu_to_be64(ctx->sstp0);
 735         ctx->elem->common.u.psl8.sstp1 = cpu_to_be64(ctx->sstp1);
 736
 737         /*
 738          * Ensure we have the multiplexed PSL interrupt set up to take faults
 739          * for kernel contexts that may not have allocated any AFU IRQs at all:
 740          */
 741         if (ctx->irqs.range[0] == 0) {
 742                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 743                 ctx->irqs.range[0] = 1;
 744         }
 745
 746         update_ivtes_directed(ctx);
 747
 748         ctx->elem->common.amr = cpu_to_be64(amr);
 749         ctx->elem->common.wed = cpu_to_be64(wed);
 750
 751         /* first guy needs to enable */
 752         if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
 753                 return result;
 754
 755         return add_process_element(ctx);
 756 }
 757
 758 static int deactivate_afu_directed(struct cxl_afu *afu)
 759 {
 760         dev_info(&afu->dev, "Deactivating AFU directed mode\n");
 761
 762         afu->current_mode = 0;
 763         afu->num_procs = 0;
 764
 765         cxl_sysfs_afu_m_remove(afu);
 766         cxl_chardev_afu_remove(afu);
 767
 768         /*
 769          * The CAIA section 2.2.1 indicates that the procedure for starting and
 770          * stopping an AFU in AFU directed mode is AFU specific, which is not
 771          * ideal since this code is generic and with one exception has no
 772          * knowledge of the AFU. This is in contrast to the procedure for
 773          * disabling a dedicated process AFU, which is documented to just
 774          * require a reset. The architecture does indicate that both an AFU
 775          * reset and an AFU disable should result in the AFU being disabled and
 776          * we do both followed by a PSL purge for safety.
 777          *
 778          * Notably we used to have some issues with the disable sequence on PSL
 779          * cards, which is why we ended up using this heavy weight procedure in
 780          * the first place, however a bug was discovered that had rendered the
 781          * disable operation ineffective, so it is conceivable that was the
 782          * sole explanation for those difficulties. Careful regression testing
 783          * is recommended if anyone attempts to remove or reorder these
 784          * operations.
 785          *
 786          * The XSL on the Mellanox CX4 behaves a little differently from the
 787          * PSL based cards and will time out an AFU reset if the AFU is still
 788          * enabled. That card is special in that we do have a means to identify
 789          * it from this code, so in that case we skip the reset and just use a
 790          * disable/purge to avoid the timeout and corresponding noise in the
 791          * kernel log.
 792          */
 793         if (afu->adapter->native->sl_ops->needs_reset_before_disable)
 794                 cxl_ops->afu_reset(afu);
 795         cxl_afu_disable(afu);
 796         cxl_psl_purge(afu);
 797
 798         return 0;
 799 }
 800
 801 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu)
 802 {
 803         dev_info(&afu->dev, "Activating dedicated process mode\n");
 804
 805         /*
 806          * If XSL is set to dedicated mode (Set in PSL_SCNTL reg), the
 807          * XSL and AFU are programmed to work with a single context.
 808          * The context information should be configured in the SPA area
 809          * index 0 (so PSL_SPAP must be configured before enabling the
 810          * AFU).
 811          */
 812         afu->num_procs = 1;
 813         if (afu->native->spa == NULL) {
 814                 if (cxl_alloc_spa(afu, CXL_MODE_DEDICATED))
 815                         return -ENOMEM;
 816         }
 817         attach_spa(afu);
 818
 819         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
 820         cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
 821
 822         afu->current_mode = CXL_MODE_DEDICATED;
 823
 824         return cxl_chardev_d_afu_add(afu);
 825 }
 826
 827 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu)
 828 {
 829         dev_info(&afu->dev, "Activating dedicated process mode\n");
 830
 831         cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
 832
 833         cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
 834         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);    /* disable */
 835         cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
 836         cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
 837         cxl_p1n_write(afu, CXL_HAURP_An, 0);       /* disable */
 838         cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
 839
 840         cxl_p2n_write(afu, CXL_CSRP_An, 0);        /* disable */
 841         cxl_p2n_write(afu, CXL_AURP0_An, 0);       /* disable */
 842         cxl_p2n_write(afu, CXL_AURP1_An, 0);       /* disable */
 843
 844         afu->current_mode = CXL_MODE_DEDICATED;
 845         afu->num_procs = 1;
 846
 847         return cxl_chardev_d_afu_add(afu);
 848 }
 849
 850 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx)
 851 {
 852         int r;
 853
 854         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 855                 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
 856                 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
 857         }
 858 }
 859
 860 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx)
 861 {
 862         struct cxl_afu *afu = ctx->afu;
 863
 864         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
 865                        (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
 866                        (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
 867                        (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
 868                         ((u64)ctx->irqs.offset[3] & 0xffff));
 869         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
 870                        (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
 871                        (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
 872                        (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
 873                         ((u64)ctx->irqs.range[3] & 0xffff));
 874 }
 875
 876 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr)
 877 {
 878         struct cxl_afu *afu = ctx->afu;
 879         int result;
 880
 881         /* fill the process element entry */
 882         result = process_element_entry_psl9(ctx, wed, amr);
 883         if (result)
 884                 return result;
 885
 886         if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
 887                 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
 888
 889         result = cxl_ops->afu_reset(afu);
 890         if (result)
 891                 return result;
 892
 893         return afu_enable(afu);
 894 }
 895
 896 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr)
 897 {
 898         struct cxl_afu *afu = ctx->afu;
 899         u64 pid;
 900         int rc;
 901
 902         pid = (u64)current->pid << 32;
 903         if (ctx->kernel)
 904                 pid = 0;
 905         cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
 906
 907         cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
 908
 909         if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
 910                 return rc;
 911
 912         cxl_prefault(ctx, wed);
 913
 914         if (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes)
 915                 afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
 916
 917         cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
 918
 919         /* master only context for dedicated */
 920         cxl_assign_psn_space(ctx);
 921
 922         if ((rc = cxl_ops->afu_reset(afu)))
 923                 return rc;
 924
 925         cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
 926
 927         return afu_enable(afu);
 928 }
 929
 930 static int deactivate_dedicated_process(struct cxl_afu *afu)
 931 {
 932         dev_info(&afu->dev, "Deactivating dedicated process mode\n");
 933
 934         afu->current_mode = 0;
 935         afu->num_procs = 0;
 936
 937         cxl_chardev_afu_remove(afu);
 938
 939         return 0;
 940 }
 941
 942 static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
 943 {
 944         if (mode == CXL_MODE_DIRECTED)
 945                 return deactivate_afu_directed(afu);
 946         if (mode == CXL_MODE_DEDICATED)
 947                 return deactivate_dedicated_process(afu);
 948         return 0;
 949 }
 950
 951 static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
 952 {
 953         if (!mode)
 954                 return 0;
 955         if (!(mode & afu->modes_supported))
 956                 return -EINVAL;
 957
 958         if (!cxl_ops->link_ok(afu->adapter, afu)) {
 959                 WARN(1, "Device link is down, refusing to activate!\n");
 960                 return -EIO;
 961         }
 962
 963         if (mode == CXL_MODE_DIRECTED)
 964                 return activate_afu_directed(afu);
 965         if ((mode == CXL_MODE_DEDICATED) &&
 966             (afu->adapter->native->sl_ops->activate_dedicated_process))
 967                 return afu->adapter->native->sl_ops->activate_dedicated_process(afu);
 968
 969         return -EINVAL;
 970 }
 971
 972 static int native_attach_process(struct cxl_context *ctx, bool kernel,
 973                                 u64 wed, u64 amr)
 974 {
 975         if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
 976                 WARN(1, "Device link is down, refusing to attach process!\n");
 977                 return -EIO;
 978         }
 979
 980         ctx->kernel = kernel;
 981         if ((ctx->afu->current_mode == CXL_MODE_DIRECTED) &&
 982             (ctx->afu->adapter->native->sl_ops->attach_afu_directed))
 983                 return ctx->afu->adapter->native->sl_ops->attach_afu_directed(ctx, wed, amr);
 984
 985         if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
 986             (ctx->afu->adapter->native->sl_ops->attach_dedicated_process))
 987                 return ctx->afu->adapter->native->sl_ops->attach_dedicated_process(ctx, wed, amr);
 988
 989         return -EINVAL;
 990 }
 991
 992 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
 993 {
 994         /*
 995          * The CAIA section 2.1.1 indicates that we need to do an AFU reset to
 996          * stop the AFU in dedicated mode (we therefore do not make that
 997          * optional like we do in the afu directed path). It does not indicate
 998          * that we need to do an explicit disable (which should occur
 999          * implicitly as part of the reset) or purge, but we do these as well
1000          * to be on the safe side.
1001          *
1002          * Notably we used to have some issues with the disable sequence
1003          * (before the sequence was spelled out in the architecture) which is
1004          * why we were so heavy weight in the first place, however a bug was
1005          * discovered that had rendered the disable operation ineffective, so
1006          * it is conceivable that was the sole explanation for those
1007          * difficulties. Point is, we should be careful and do some regression
1008          * testing if we ever attempt to remove any part of this procedure.
1009          */
1010         cxl_ops->afu_reset(ctx->afu);
1011         cxl_afu_disable(ctx->afu);
1012         cxl_psl_purge(ctx->afu);
1013         return 0;
1014 }
1015
1016 static void native_update_ivtes(struct cxl_context *ctx)
1017 {
1018         if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
1019                 return update_ivtes_directed(ctx);
1020         if ((ctx->afu->current_mode == CXL_MODE_DEDICATED) &&
1021             (ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes))
1022                 return ctx->afu->adapter->native->sl_ops->update_dedicated_ivtes(ctx);
1023         WARN(1, "native_update_ivtes: Bad mode\n");
1024 }
1025
1026 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
1027 {
1028         if (!ctx->pe_inserted)
1029                 return 0;
1030         if (terminate_process_element(ctx))
1031                 return -1;
1032         if (remove_process_element(ctx))
1033                 return -1;
1034
1035         return 0;
1036 }
1037
1038 static int native_detach_process(struct cxl_context *ctx)
1039 {
1040         trace_cxl_detach(ctx);
1041
1042         if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
1043                 return detach_process_native_dedicated(ctx);
1044
1045         return detach_process_native_afu_directed(ctx);
1046 }
1047
1048 static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
1049 {
1050         /* If the adapter has gone away, we can't get any meaningful
1051          * information.
1052          */
1053         if (!cxl_ops->link_ok(afu->adapter, afu))
1054                 return -EIO;
1055
1056         info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1057         info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
1058         if (cxl_is_power8())
1059                 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
1060         info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1061         info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1062         info->proc_handle = 0;
1063
1064         return 0;
1065 }
1066
1067 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
1068 {
1069         u64 fir1, fir2, serr;
1070
1071         fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
1072         fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR2);
1073
1074         dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1075         dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1076         if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1077                 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1078                 cxl_afu_decode_psl_serr(ctx->afu, serr);
1079         }
1080 }
1081
1082 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx)
1083 {
1084         u64 fir1, fir2, fir_slice, serr, afu_debug;
1085
1086         fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
1087         fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
1088         fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
1089         afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
1090
1091         dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
1092         dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
1093         if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
1094                 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
1095                 cxl_afu_decode_psl_serr(ctx->afu, serr);
1096         }
1097         dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1098         dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1099 }
1100
1101 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
1102                                                 u64 dsisr, u64 errstat)
1103 {
1104
1105         dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
1106
1107         if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers)
1108                 ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx);
1109
1110         if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) {
1111                 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
1112                 ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter);
1113         }
1114
1115         return cxl_ops->ack_irq(ctx, 0, errstat);
1116 }
1117
1118 static bool cxl_is_translation_fault(struct cxl_afu *afu, u64 dsisr)
1119 {
1120         if ((cxl_is_psl8(afu)) && (dsisr & CXL_PSL_DSISR_TRANS))
1121                 return true;
1122
1123         if ((cxl_is_psl9(afu)) && (dsisr & CXL_PSL9_DSISR_An_TF))
1124                 return true;
1125
1126         return false;
1127 }
1128
1129 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
1130 {
1131         if (cxl_is_translation_fault(afu, irq_info->dsisr))
1132                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1133         else
1134                 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1135
1136         return IRQ_HANDLED;
1137 }
1138
1139 static irqreturn_t native_irq_multiplexed(int irq, void *data)
1140 {
1141         struct cxl_afu *afu = data;
1142         struct cxl_context *ctx;
1143         struct cxl_irq_info irq_info;
1144         u64 phreg = cxl_p2n_read(afu, CXL_PSL_PEHandle_An);
1145         int ph, ret = IRQ_HANDLED, res;
1146
1147         /* check if eeh kicked in while the interrupt was in flight */
1148         if (unlikely(phreg == ~0ULL)) {
1149                 dev_warn(&afu->dev,
1150                          "Ignoring slice interrupt(%d) due to fenced card",
1151                          irq);
1152                 return IRQ_HANDLED;
1153         }
1154         /* Mask the pe-handle from register value */
1155         ph = phreg & 0xffff;
1156         if ((res = native_get_irq_info(afu, &irq_info))) {
1157                 WARN(1, "Unable to get CXL IRQ Info: %i\n", res);
1158                 if (afu->adapter->native->sl_ops->fail_irq)
1159                         return afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1160                 return ret;
1161         }
1162
1163         rcu_read_lock();
1164         ctx = idr_find(&afu->contexts_idr, ph);
1165         if (ctx) {
1166                 if (afu->adapter->native->sl_ops->handle_interrupt)
1167                         ret = afu->adapter->native->sl_ops->handle_interrupt(irq, ctx, &irq_info);
1168                 rcu_read_unlock();
1169                 return ret;
1170         }
1171         rcu_read_unlock();
1172
1173         WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
1174                 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
1175                 " with outstanding transactions?)\n", ph, irq_info.dsisr,
1176                 irq_info.dar);
1177         if (afu->adapter->native->sl_ops->fail_irq)
1178                 ret = afu->adapter->native->sl_ops->fail_irq(afu, &irq_info);
1179         return ret;
1180 }
1181
1182 static void native_irq_wait(struct cxl_context *ctx)
1183 {
1184         u64 dsisr;
1185         int timeout = 1000;
1186         int ph;
1187
1188         /*
1189          * Wait until no further interrupts are presented by the PSL
1190          * for this context.
1191          */
1192         while (timeout--) {
1193                 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
1194                 if (ph != ctx->pe)
1195                         return;
1196                 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
1197                 if (cxl_is_psl8(ctx->afu) &&
1198                    ((dsisr & CXL_PSL_DSISR_PENDING) == 0))
1199                         return;
1200                 if (cxl_is_psl9(ctx->afu) &&
1201                    ((dsisr & CXL_PSL9_DSISR_PENDING) == 0))
1202                         return;
1203                 /*
1204                  * We are waiting for the workqueue to process our
1205                  * irq, so need to let that run here.
1206                  */
1207                 msleep(1);
1208         }
1209
1210         dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
1211                  " DSISR %016llx!\n", ph, dsisr);
1212         return;
1213 }
1214
1215 static irqreturn_t native_slice_irq_err(int irq, void *data)
1216 {
1217         struct cxl_afu *afu = data;
1218         u64 errstat, serr, afu_error, dsisr;
1219         u64 fir_slice, afu_debug, irq_mask;
1220
1221         /*
1222          * slice err interrupt is only used with full PSL (no XSL)
1223          */
1224         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1225         errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1226         afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An);
1227         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1228         cxl_afu_decode_psl_serr(afu, serr);
1229
1230         if (cxl_is_power8()) {
1231                 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
1232                 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
1233                 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
1234                 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
1235         }
1236         dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
1237         dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error);
1238         dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr);
1239
1240         /* mask off the IRQ so it won't retrigger until the AFU is reset */
1241         irq_mask = (serr & CXL_PSL_SERR_An_IRQS) >> 32;
1242         serr |= irq_mask;
1243         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1244         dev_info(&afu->dev, "Further such interrupts will be masked until the AFU is reset\n");
1245
1246         return IRQ_HANDLED;
1247 }
1248
1249 void cxl_native_err_irq_dump_regs(struct cxl *adapter)
1250 {
1251         u64 fir1, fir2;
1252
1253         fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
1254         fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
1255
1256         dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
1257 }
1258
1259 static irqreturn_t native_irq_err(int irq, void *data)
1260 {
1261         struct cxl *adapter = data;
1262         u64 err_ivte;
1263
1264         WARN(1, "CXL ERROR interrupt %i\n", irq);
1265
1266         err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
1267         dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
1268
1269         if (adapter->native->sl_ops->debugfs_stop_trace) {
1270                 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
1271                 adapter->native->sl_ops->debugfs_stop_trace(adapter);
1272         }
1273
1274         if (adapter->native->sl_ops->err_irq_dump_registers)
1275                 adapter->native->sl_ops->err_irq_dump_registers(adapter);
1276
1277         return IRQ_HANDLED;
1278 }
1279
1280 int cxl_native_register_psl_err_irq(struct cxl *adapter)
1281 {
1282         int rc;
1283
1284         adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1285                                       dev_name(&adapter->dev));
1286         if (!adapter->irq_name)
1287                 return -ENOMEM;
1288
1289         if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
1290                                        &adapter->native->err_hwirq,
1291                                        &adapter->native->err_virq,
1292                                        adapter->irq_name))) {
1293                 kfree(adapter->irq_name);
1294                 adapter->irq_name = NULL;
1295                 return rc;
1296         }
1297
1298         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff);
1299
1300         return 0;
1301 }
1302
1303 void cxl_native_release_psl_err_irq(struct cxl *adapter)
1304 {
1305         if (adapter->native->err_virq == 0 ||
1306             adapter->native->err_virq !=
1307             irq_find_mapping(NULL, adapter->native->err_hwirq))
1308                 return;
1309
1310         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
1311         cxl_unmap_irq(adapter->native->err_virq, adapter);
1312         cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
1313         kfree(adapter->irq_name);
1314         adapter->native->err_virq = 0;
1315 }
1316
1317 int cxl_native_register_serr_irq(struct cxl_afu *afu)
1318 {
1319         u64 serr;
1320         int rc;
1321
1322         afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
1323                                       dev_name(&afu->dev));
1324         if (!afu->err_irq_name)
1325                 return -ENOMEM;
1326
1327         if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
1328                                        &afu->serr_hwirq,
1329                                        &afu->serr_virq, afu->err_irq_name))) {
1330                 kfree(afu->err_irq_name);
1331                 afu->err_irq_name = NULL;
1332                 return rc;
1333         }
1334
1335         serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1336         if (cxl_is_power8())
1337                 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
1338         if (cxl_is_power9()) {
1339                 /*
1340                  * By default, all errors are masked. So don't set all masks.
1341                  * Slice errors will be transfered.
1342                  */
1343                 serr = (serr & ~0xff0000007fffffffULL) | (afu->serr_hwirq & 0xffff);
1344         }
1345         cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
1346
1347         return 0;
1348 }
1349
1350 void cxl_native_release_serr_irq(struct cxl_afu *afu)
1351 {
1352         if (afu->serr_virq == 0 ||
1353             afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
1354                 return;
1355
1356         cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
1357         cxl_unmap_irq(afu->serr_virq, afu);
1358         cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
1359         kfree(afu->err_irq_name);
1360         afu->serr_virq = 0;
1361 }
1362
1363 int cxl_native_register_psl_irq(struct cxl_afu *afu)
1364 {
1365         int rc;
1366
1367         afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
1368                                       dev_name(&afu->dev));
1369         if (!afu->psl_irq_name)
1370                 return -ENOMEM;
1371
1372         if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
1373                                     afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
1374                                     afu->psl_irq_name))) {
1375                 kfree(afu->psl_irq_name);
1376                 afu->psl_irq_name = NULL;
1377         }
1378         return rc;
1379 }
1380
1381 void cxl_native_release_psl_irq(struct cxl_afu *afu)
1382 {
1383         if (afu->native->psl_virq == 0 ||
1384             afu->native->psl_virq !=
1385             irq_find_mapping(NULL, afu->native->psl_hwirq))
1386                 return;
1387
1388         cxl_unmap_irq(afu->native->psl_virq, afu);
1389         cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
1390         kfree(afu->psl_irq_name);
1391         afu->native->psl_virq = 0;
1392 }
1393
1394 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
1395 {
1396         u64 dsisr;
1397
1398         pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
1399
1400         /* Clear PSL_DSISR[PE] */
1401         dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1402         cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
1403
1404         /* Write 1s to clear error status bits */
1405         cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
1406 }
1407
1408 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1409 {
1410         trace_cxl_psl_irq_ack(ctx, tfc);
1411         if (tfc)
1412                 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1413         if (psl_reset_mask)
1414                 recover_psl_err(ctx->afu, psl_reset_mask);
1415
1416         return 0;
1417 }
1418
1419 int cxl_check_error(struct cxl_afu *afu)
1420 {
1421         return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
1422 }
1423
1424 static bool native_support_attributes(const char *attr_name,
1425                                       enum cxl_attrs type)
1426 {
1427         return true;
1428 }
1429
1430 static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
1431 {
1432         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1433                 return -EIO;
1434         if (unlikely(off >= afu->crs_len))
1435                 return -ERANGE;
1436         *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
1437                 (cr * afu->crs_len) + off);
1438         return 0;
1439 }
1440
1441 static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
1442 {
1443         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1444                 return -EIO;
1445         if (unlikely(off >= afu->crs_len))
1446                 return -ERANGE;
1447         *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1448                 (cr * afu->crs_len) + off);
1449         return 0;
1450 }
1451
1452 static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
1453 {
1454         u64 aligned_off = off & ~0x3L;
1455         u32 val;
1456         int rc;
1457
1458         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1459         if (!rc)
1460                 *out = (val >> ((off & 0x3) * 8)) & 0xffff;
1461         return rc;
1462 }
1463
1464 static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
1465 {
1466         u64 aligned_off = off & ~0x3L;
1467         u32 val;
1468         int rc;
1469
1470         rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1471         if (!rc)
1472                 *out = (val >> ((off & 0x3) * 8)) & 0xff;
1473         return rc;
1474 }
1475
1476 static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
1477 {
1478         if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1479                 return -EIO;
1480         if (unlikely(off >= afu->crs_len))
1481                 return -ERANGE;
1482         out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1483                 (cr * afu->crs_len) + off, in);
1484         return 0;
1485 }
1486
1487 static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
1488 {
1489         u64 aligned_off = off & ~0x3L;
1490         u32 val32, mask, shift;
1491         int rc;
1492
1493         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1494         if (rc)
1495                 return rc;
1496         shift = (off & 0x3) * 8;
1497         WARN_ON(shift == 24);
1498         mask = 0xffff << shift;
1499         val32 = (val32 & ~mask) | (in << shift);
1500
1501         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1502         return rc;
1503 }
1504
1505 static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
1506 {
1507         u64 aligned_off = off & ~0x3L;
1508         u32 val32, mask, shift;
1509         int rc;
1510
1511         rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1512         if (rc)
1513                 return rc;
1514         shift = (off & 0x3) * 8;
1515         mask = 0xff << shift;
1516         val32 = (val32 & ~mask) | (in << shift);
1517
1518         rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1519         return rc;
1520 }
1521
1522 const struct cxl_backend_ops cxl_native_ops = {
1523         .module = THIS_MODULE,
1524         .adapter_reset = cxl_pci_reset,
1525         .alloc_one_irq = cxl_pci_alloc_one_irq,
1526         .release_one_irq = cxl_pci_release_one_irq,
1527         .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1528         .release_irq_ranges = cxl_pci_release_irq_ranges,
1529         .setup_irq = cxl_pci_setup_irq,
1530         .handle_psl_slice_error = native_handle_psl_slice_error,
1531         .psl_interrupt = NULL,
1532         .ack_irq = native_ack_irq,
1533         .irq_wait = native_irq_wait,
1534         .attach_process = native_attach_process,
1535         .detach_process = native_detach_process,
1536         .update_ivtes = native_update_ivtes,
1537         .support_attributes = native_support_attributes,
1538         .link_ok = cxl_adapter_link_ok,
1539         .release_afu = cxl_pci_release_afu,
1540         .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1541         .afu_check_and_enable = native_afu_check_and_enable,
1542         .afu_activate_mode = native_afu_activate_mode,
1543         .afu_deactivate_mode = native_afu_deactivate_mode,
1544         .afu_reset = native_afu_reset,
1545         .afu_cr_read8 = native_afu_cr_read8,
1546         .afu_cr_read16 = native_afu_cr_read16,
1547         .afu_cr_read32 = native_afu_cr_read32,
1548         .afu_cr_read64 = native_afu_cr_read64,
1549         .afu_cr_write8 = native_afu_cr_write8,
1550         .afu_cr_write16 = native_afu_cr_write16,
1551         .afu_cr_write32 = native_afu_cr_write32,
1552         .read_adapter_vpd = cxl_pci_read_adapter_vpd,
1553 };