2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/spinlock.h>
11 #include <linux/sched.h>
12 #include <linux/slab.h>
13 #include <linux/sched.h>
14 #include <linux/mutex.h>
16 #include <linux/uaccess.h>
17 #include <linux/delay.h>
18 #include <asm/synch.h>
19 #include <misc/cxl-base.h>
24 static int afu_control(struct cxl_afu *afu, u64 command,
25 u64 result, u64 mask, bool enabled)
27 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
28 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
31 spin_lock(&afu->afu_cntl_lock);
32 pr_devel("AFU command starting: %llx\n", command);
34 trace_cxl_afu_ctrl(afu, command);
36 cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl | command);
38 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
39 while ((AFU_Cntl & mask) != result) {
40 if (time_after_eq(jiffies, timeout)) {
41 dev_warn(&afu->dev, "WARNING: AFU control timed out!\n");
46 if (!cxl_ops->link_ok(afu->adapter, afu)) {
47 afu->enabled = enabled;
52 pr_devel_ratelimited("AFU control... (0x%016llx)\n",
55 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
57 pr_devel("AFU command complete: %llx\n", command);
58 afu->enabled = enabled;
60 trace_cxl_afu_ctrl_done(afu, command, rc);
61 spin_unlock(&afu->afu_cntl_lock);
66 static int afu_enable(struct cxl_afu *afu)
68 pr_devel("AFU enable request\n");
70 return afu_control(afu, CXL_AFU_Cntl_An_E,
71 CXL_AFU_Cntl_An_ES_Enabled,
72 CXL_AFU_Cntl_An_ES_MASK, true);
75 int cxl_afu_disable(struct cxl_afu *afu)
77 pr_devel("AFU disable request\n");
79 return afu_control(afu, 0, CXL_AFU_Cntl_An_ES_Disabled,
80 CXL_AFU_Cntl_An_ES_MASK, false);
83 /* This will disable as well as reset */
84 static int native_afu_reset(struct cxl_afu *afu)
86 pr_devel("AFU reset request\n");
88 return afu_control(afu, CXL_AFU_Cntl_An_RA,
89 CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled,
90 CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK,
94 static int native_afu_check_and_enable(struct cxl_afu *afu)
96 if (!cxl_ops->link_ok(afu->adapter, afu)) {
97 WARN(1, "Refusing to enable afu while link down!\n");
102 return afu_enable(afu);
105 int cxl_psl_purge(struct cxl_afu *afu)
107 u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
108 u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
111 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
114 trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc);
116 pr_devel("PSL purge request\n");
118 if (!cxl_ops->link_ok(afu->adapter, afu)) {
119 dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n");
124 if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
125 WARN(1, "psl_purge request while AFU not disabled!\n");
126 cxl_afu_disable(afu);
129 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
130 PSL_CNTL | CXL_PSL_SCNTL_An_Pc);
131 start = local_clock();
132 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
133 while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK)
134 == CXL_PSL_SCNTL_An_Ps_Pending) {
135 if (time_after_eq(jiffies, timeout)) {
136 dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n");
140 if (!cxl_ops->link_ok(afu->adapter, afu)) {
145 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
146 pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr);
147 if (dsisr & CXL_PSL_DSISR_TRANS) {
148 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
149 dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar);
150 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
152 dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr);
153 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
157 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An);
160 pr_devel("PSL purged in %lld ns\n", end - start);
162 cxl_p1n_write(afu, CXL_PSL_SCNTL_An,
163 PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc);
165 trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc);
169 static int spa_max_procs(int spa_size)
173 * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255
174 * Most of that junk is really just an overly-complicated way of saying
175 * the last 256 bytes are __aligned(128), so it's really:
176 * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255
178 * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1
180 * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256
181 * Ignore the alignment (which is safe in this case as long as we are
182 * careful with our rounding) and solve for n:
184 return ((spa_size / 8) - 96) / 17;
187 int cxl_alloc_spa(struct cxl_afu *afu)
191 /* Work out how many pages to allocate */
192 afu->native->spa_order = 0;
194 afu->native->spa_order++;
195 spa_size = (1 << afu->native->spa_order) * PAGE_SIZE;
197 if (spa_size > 0x100000) {
198 dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n",
199 afu->native->spa_max_procs, afu->native->spa_size);
200 afu->num_procs = afu->native->spa_max_procs;
204 afu->native->spa_size = spa_size;
205 afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size);
206 } while (afu->native->spa_max_procs < afu->num_procs);
208 if (!(afu->native->spa = (struct cxl_process_element *)
209 __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) {
210 pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n");
213 pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n",
214 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs);
219 static void attach_spa(struct cxl_afu *afu)
223 afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa +
224 ((afu->native->spa_max_procs + 3) * 128));
226 spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr;
227 spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size;
228 spap |= CXL_PSL_SPAP_V;
229 pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n",
230 afu->native->spa, afu->native->spa_max_procs,
231 afu->native->sw_command_status, spap);
232 cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap);
235 static inline void detach_spa(struct cxl_afu *afu)
237 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0);
240 void cxl_release_spa(struct cxl_afu *afu)
242 if (afu->native->spa) {
243 free_pages((unsigned long) afu->native->spa,
244 afu->native->spa_order);
245 afu->native->spa = NULL;
249 int cxl_tlb_slb_invalidate(struct cxl *adapter)
251 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
253 pr_devel("CXL adapter wide TLBIA & SLBIA\n");
255 cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A);
257 cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL);
258 while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) {
259 if (time_after_eq(jiffies, timeout)) {
260 dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n");
263 if (!cxl_ops->link_ok(adapter, NULL))
268 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL);
269 while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) {
270 if (time_after_eq(jiffies, timeout)) {
271 dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n");
274 if (!cxl_ops->link_ok(adapter, NULL))
281 static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1)
285 /* 1. Disable SSTP by writing 0 to SSTP1[V] */
286 cxl_p2n_write(afu, CXL_SSTP1_An, 0);
288 /* 2. Invalidate all SLB entries */
289 if ((rc = cxl_afu_slbia(afu)))
292 /* 3. Set SSTP0_An */
293 cxl_p2n_write(afu, CXL_SSTP0_An, sstp0);
295 /* 4. Set SSTP1_An */
296 cxl_p2n_write(afu, CXL_SSTP1_An, sstp1);
301 /* Using per slice version may improve performance here. (ie. SLBIA_An) */
302 static void slb_invalid(struct cxl_context *ctx)
304 struct cxl *adapter = ctx->afu->adapter;
307 WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex));
309 cxl_p1_write(adapter, CXL_PSL_LBISEL,
310 ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) |
311 be32_to_cpu(ctx->elem->lpid));
312 cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID);
315 if (!cxl_ops->link_ok(adapter, NULL))
317 slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA);
318 if (!(slbia & CXL_TLB_SLB_P))
324 static int do_process_element_cmd(struct cxl_context *ctx,
325 u64 cmd, u64 pe_state)
328 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
331 trace_cxl_llcmd(ctx, cmd);
333 WARN_ON(!ctx->afu->enabled);
335 ctx->elem->software_state = cpu_to_be32(pe_state);
337 *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe);
339 cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe);
341 if (time_after_eq(jiffies, timeout)) {
342 dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n");
346 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
347 dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n");
351 state = be64_to_cpup(ctx->afu->native->sw_command_status);
352 if (state == ~0ULL) {
353 pr_err("cxl: Error adding process element to AFU\n");
357 if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) ==
358 (cmd | (cmd >> 16) | ctx->pe))
361 * The command won't finish in the PSL if there are
362 * outstanding DSIs. Hence we need to yield here in
363 * case there are outstanding DSIs that we need to
364 * service. Tuning possiblity: we could wait for a
371 trace_cxl_llcmd_done(ctx, cmd, rc);
375 static int add_process_element(struct cxl_context *ctx)
379 mutex_lock(&ctx->afu->native->spa_mutex);
380 pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe);
381 if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V)))
382 ctx->pe_inserted = true;
383 pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe);
384 mutex_unlock(&ctx->afu->native->spa_mutex);
388 static int terminate_process_element(struct cxl_context *ctx)
392 /* fast path terminate if it's already invalid */
393 if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V)))
396 mutex_lock(&ctx->afu->native->spa_mutex);
397 pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe);
398 /* We could be asked to terminate when the hw is down. That
399 * should always succeed: it's not running if the hw has gone
400 * away and is being reset.
402 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
403 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE,
404 CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T);
405 ctx->elem->software_state = 0; /* Remove Valid bit */
406 pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe);
407 mutex_unlock(&ctx->afu->native->spa_mutex);
411 static int remove_process_element(struct cxl_context *ctx)
415 mutex_lock(&ctx->afu->native->spa_mutex);
416 pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe);
418 /* We could be asked to remove when the hw is down. Again, if
419 * the hw is down, the PE is gone, so we succeed.
421 if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu))
422 rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0);
425 ctx->pe_inserted = false;
427 pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe);
428 mutex_unlock(&ctx->afu->native->spa_mutex);
434 void cxl_assign_psn_space(struct cxl_context *ctx)
436 if (!ctx->afu->pp_size || ctx->master) {
437 ctx->psn_phys = ctx->afu->psn_phys;
438 ctx->psn_size = ctx->afu->adapter->ps_size;
440 ctx->psn_phys = ctx->afu->psn_phys +
441 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe);
442 ctx->psn_size = ctx->afu->pp_size;
446 static int activate_afu_directed(struct cxl_afu *afu)
450 dev_info(&afu->dev, "Activating AFU directed mode\n");
452 afu->num_procs = afu->max_procs_virtualised;
453 if (afu->native->spa == NULL) {
454 if (cxl_alloc_spa(afu))
459 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU);
460 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
461 cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L);
463 afu->current_mode = CXL_MODE_DIRECTED;
465 if ((rc = cxl_chardev_m_afu_add(afu)))
468 if ((rc = cxl_sysfs_afu_m_add(afu)))
471 if ((rc = cxl_chardev_s_afu_add(afu)))
476 cxl_sysfs_afu_m_remove(afu);
478 cxl_chardev_afu_remove(afu);
482 #ifdef CONFIG_CPU_LITTLE_ENDIAN
483 #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
485 #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
488 static u64 calculate_sr(struct cxl_context *ctx)
494 sr |= CXL_PSL_SR_An_MP;
495 if (mfspr(SPRN_LPCR) & LPCR_TC)
496 sr |= CXL_PSL_SR_An_TC;
499 sr |= CXL_PSL_SR_An_R;
500 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
502 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
503 sr &= ~(CXL_PSL_SR_An_HV);
504 if (!test_tsk_thread_flag(current, TIF_32BIT))
505 sr |= CXL_PSL_SR_An_SF;
510 static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
515 cxl_assign_psn_space(ctx);
517 ctx->elem->ctxtime = 0; /* disable */
518 ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID));
519 ctx->elem->haurp = 0; /* disable */
520 ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
525 ctx->elem->common.tid = 0;
526 ctx->elem->common.pid = cpu_to_be32(pid);
528 ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
530 ctx->elem->common.csrp = 0; /* disable */
531 ctx->elem->common.aurp0 = 0; /* disable */
532 ctx->elem->common.aurp1 = 0; /* disable */
534 cxl_prefault(ctx, wed);
536 ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0);
537 ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1);
540 * Ensure we have the multiplexed PSL interrupt set up to take faults
541 * for kernel contexts that may not have allocated any AFU IRQs at all:
543 if (ctx->irqs.range[0] == 0) {
544 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
545 ctx->irqs.range[0] = 1;
548 for (r = 0; r < CXL_IRQ_RANGES; r++) {
549 ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]);
550 ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]);
553 ctx->elem->common.amr = cpu_to_be64(amr);
554 ctx->elem->common.wed = cpu_to_be64(wed);
556 /* first guy needs to enable */
557 if ((result = cxl_ops->afu_check_and_enable(ctx->afu)))
560 return add_process_element(ctx);
563 static int deactivate_afu_directed(struct cxl_afu *afu)
565 dev_info(&afu->dev, "Deactivating AFU directed mode\n");
567 afu->current_mode = 0;
570 cxl_sysfs_afu_m_remove(afu);
571 cxl_chardev_afu_remove(afu);
573 cxl_ops->afu_reset(afu);
574 cxl_afu_disable(afu);
580 static int activate_dedicated_process(struct cxl_afu *afu)
582 dev_info(&afu->dev, "Activating dedicated process mode\n");
584 cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process);
586 cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */
587 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */
588 cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL);
589 cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID));
590 cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */
591 cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1));
593 cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */
594 cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */
595 cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */
597 afu->current_mode = CXL_MODE_DEDICATED;
600 return cxl_chardev_d_afu_add(afu);
603 static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
605 struct cxl_afu *afu = ctx->afu;
609 pid = (u64)current->pid << 32;
612 cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
614 cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
616 if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
619 cxl_prefault(ctx, wed);
621 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An,
622 (((u64)ctx->irqs.offset[0] & 0xffff) << 48) |
623 (((u64)ctx->irqs.offset[1] & 0xffff) << 32) |
624 (((u64)ctx->irqs.offset[2] & 0xffff) << 16) |
625 ((u64)ctx->irqs.offset[3] & 0xffff));
626 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64)
627 (((u64)ctx->irqs.range[0] & 0xffff) << 48) |
628 (((u64)ctx->irqs.range[1] & 0xffff) << 32) |
629 (((u64)ctx->irqs.range[2] & 0xffff) << 16) |
630 ((u64)ctx->irqs.range[3] & 0xffff));
632 cxl_p2n_write(afu, CXL_PSL_AMR_An, amr);
634 /* master only context for dedicated */
635 cxl_assign_psn_space(ctx);
637 if ((rc = cxl_ops->afu_reset(afu)))
640 cxl_p2n_write(afu, CXL_PSL_WED_An, wed);
642 return afu_enable(afu);
645 static int deactivate_dedicated_process(struct cxl_afu *afu)
647 dev_info(&afu->dev, "Deactivating dedicated process mode\n");
649 afu->current_mode = 0;
652 cxl_chardev_afu_remove(afu);
657 static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode)
659 if (mode == CXL_MODE_DIRECTED)
660 return deactivate_afu_directed(afu);
661 if (mode == CXL_MODE_DEDICATED)
662 return deactivate_dedicated_process(afu);
666 static int native_afu_activate_mode(struct cxl_afu *afu, int mode)
670 if (!(mode & afu->modes_supported))
673 if (!cxl_ops->link_ok(afu->adapter, afu)) {
674 WARN(1, "Device link is down, refusing to activate!\n");
678 if (mode == CXL_MODE_DIRECTED)
679 return activate_afu_directed(afu);
680 if (mode == CXL_MODE_DEDICATED)
681 return activate_dedicated_process(afu);
686 static int native_attach_process(struct cxl_context *ctx, bool kernel,
689 if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) {
690 WARN(1, "Device link is down, refusing to attach process!\n");
694 ctx->kernel = kernel;
695 if (ctx->afu->current_mode == CXL_MODE_DIRECTED)
696 return attach_afu_directed(ctx, wed, amr);
698 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
699 return attach_dedicated(ctx, wed, amr);
704 static inline int detach_process_native_dedicated(struct cxl_context *ctx)
706 cxl_ops->afu_reset(ctx->afu);
707 cxl_afu_disable(ctx->afu);
708 cxl_psl_purge(ctx->afu);
712 static inline int detach_process_native_afu_directed(struct cxl_context *ctx)
714 if (!ctx->pe_inserted)
716 if (terminate_process_element(ctx))
718 if (remove_process_element(ctx))
724 static int native_detach_process(struct cxl_context *ctx)
726 trace_cxl_detach(ctx);
728 if (ctx->afu->current_mode == CXL_MODE_DEDICATED)
729 return detach_process_native_dedicated(ctx);
731 return detach_process_native_afu_directed(ctx);
734 static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info)
738 /* If the adapter has gone away, we can't get any meaningful
741 if (!cxl_ops->link_ok(afu->adapter, afu))
744 info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
745 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An);
746 info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An);
747 pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An);
748 info->pid = pidtid >> 32;
749 info->tid = pidtid & 0xffffffff;
750 info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An);
751 info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
752 info->proc_handle = 0;
757 static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx,
758 u64 dsisr, u64 errstat)
760 u64 fir1, fir2, fir_slice, serr, afu_debug;
762 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
763 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
764 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
765 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
766 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
768 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat);
769 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
770 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
771 dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
772 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
773 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
775 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
776 cxl_stop_trace(ctx->afu->adapter);
778 return cxl_ops->ack_irq(ctx, 0, errstat);
781 static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
783 if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
784 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
786 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
791 static irqreturn_t native_irq_multiplexed(int irq, void *data)
793 struct cxl_afu *afu = data;
794 struct cxl_context *ctx;
795 struct cxl_irq_info irq_info;
796 int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff;
799 if ((ret = native_get_irq_info(afu, &irq_info))) {
800 WARN(1, "Unable to get CXL IRQ Info: %i\n", ret);
801 return fail_psl_irq(afu, &irq_info);
805 ctx = idr_find(&afu->contexts_idr, ph);
807 ret = cxl_irq(irq, ctx, &irq_info);
813 WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR"
814 " %016llx\n(Possible AFU HW issue - was a term/remove acked"
815 " with outstanding transactions?)\n", ph, irq_info.dsisr,
817 return fail_psl_irq(afu, &irq_info);
820 void native_irq_wait(struct cxl_context *ctx)
827 * Wait until no further interrupts are presented by the PSL
831 ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff;
834 dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An);
835 if ((dsisr & CXL_PSL_DSISR_PENDING) == 0)
838 * We are waiting for the workqueue to process our
839 * irq, so need to let that run here.
844 dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i"
845 " DSISR %016llx!\n", ph, dsisr);
849 static irqreturn_t native_slice_irq_err(int irq, void *data)
851 struct cxl_afu *afu = data;
852 u64 fir_slice, errstat, serr, afu_debug;
854 WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq);
856 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
857 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
858 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
859 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
860 dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr);
861 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice);
862 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat);
863 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug);
865 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
870 static irqreturn_t native_irq_err(int irq, void *data)
872 struct cxl *adapter = data;
873 u64 fir1, fir2, err_ivte;
875 WARN(1, "CXL ERROR interrupt %i\n", irq);
877 err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
878 dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte);
880 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
881 cxl_stop_trace(adapter);
883 fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
884 fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
886 dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
891 int cxl_native_register_psl_err_irq(struct cxl *adapter)
895 adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
896 dev_name(&adapter->dev));
897 if (!adapter->irq_name)
900 if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter,
901 &adapter->native->err_hwirq,
902 &adapter->native->err_virq,
903 adapter->irq_name))) {
904 kfree(adapter->irq_name);
905 adapter->irq_name = NULL;
909 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff);
914 void cxl_native_release_psl_err_irq(struct cxl *adapter)
916 if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq))
919 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
920 cxl_unmap_irq(adapter->native->err_virq, adapter);
921 cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq);
922 kfree(adapter->irq_name);
925 int cxl_native_register_serr_irq(struct cxl_afu *afu)
930 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
931 dev_name(&afu->dev));
932 if (!afu->err_irq_name)
935 if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu,
937 &afu->serr_virq, afu->err_irq_name))) {
938 kfree(afu->err_irq_name);
939 afu->err_irq_name = NULL;
943 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
944 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
945 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
950 void cxl_native_release_serr_irq(struct cxl_afu *afu)
952 if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq))
955 cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
956 cxl_unmap_irq(afu->serr_virq, afu);
957 cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq);
958 kfree(afu->err_irq_name);
961 int cxl_native_register_psl_irq(struct cxl_afu *afu)
965 afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
966 dev_name(&afu->dev));
967 if (!afu->psl_irq_name)
970 if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed,
971 afu, &afu->native->psl_hwirq, &afu->native->psl_virq,
972 afu->psl_irq_name))) {
973 kfree(afu->psl_irq_name);
974 afu->psl_irq_name = NULL;
979 void cxl_native_release_psl_irq(struct cxl_afu *afu)
981 if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq))
984 cxl_unmap_irq(afu->native->psl_virq, afu);
985 cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq);
986 kfree(afu->psl_irq_name);
989 static void recover_psl_err(struct cxl_afu *afu, u64 errstat)
993 pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat);
995 /* Clear PSL_DSISR[PE] */
996 dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
997 cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE);
999 /* Write 1s to clear error status bits */
1000 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat);
1003 static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask)
1005 trace_cxl_psl_irq_ack(ctx, tfc);
1007 cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc);
1009 recover_psl_err(ctx->afu, psl_reset_mask);
1014 int cxl_check_error(struct cxl_afu *afu)
1016 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
1019 static bool native_support_attributes(const char *attr_name,
1020 enum cxl_attrs type)
1025 static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
1027 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1029 if (unlikely(off >= afu->crs_len))
1031 *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
1032 (cr * afu->crs_len) + off);
1036 static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out)
1038 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1040 if (unlikely(off >= afu->crs_len))
1042 *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1043 (cr * afu->crs_len) + off);
1047 static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out)
1049 u64 aligned_off = off & ~0x3L;
1053 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1055 *out = (val >> ((off & 0x3) * 8)) & 0xffff;
1059 static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out)
1061 u64 aligned_off = off & ~0x3L;
1065 rc = native_afu_cr_read32(afu, cr, aligned_off, &val);
1067 *out = (val >> ((off & 0x3) * 8)) & 0xff;
1071 static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in)
1073 if (unlikely(!cxl_ops->link_ok(afu->adapter, afu)))
1075 if (unlikely(off >= afu->crs_len))
1077 out_le32(afu->native->afu_desc_mmio + afu->crs_offset +
1078 (cr * afu->crs_len) + off, in);
1082 static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in)
1084 u64 aligned_off = off & ~0x3L;
1085 u32 val32, mask, shift;
1088 rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1091 shift = (off & 0x3) * 8;
1092 WARN_ON(shift == 24);
1093 mask = 0xffff << shift;
1094 val32 = (val32 & ~mask) | (in << shift);
1096 rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1100 static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in)
1102 u64 aligned_off = off & ~0x3L;
1103 u32 val32, mask, shift;
1106 rc = native_afu_cr_read32(afu, cr, aligned_off, &val32);
1109 shift = (off & 0x3) * 8;
1110 mask = 0xff << shift;
1111 val32 = (val32 & ~mask) | (in << shift);
1113 rc = native_afu_cr_write32(afu, cr, aligned_off, val32);
1117 const struct cxl_backend_ops cxl_native_ops = {
1118 .module = THIS_MODULE,
1119 .adapter_reset = cxl_pci_reset,
1120 .alloc_one_irq = cxl_pci_alloc_one_irq,
1121 .release_one_irq = cxl_pci_release_one_irq,
1122 .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1123 .release_irq_ranges = cxl_pci_release_irq_ranges,
1124 .setup_irq = cxl_pci_setup_irq,
1125 .handle_psl_slice_error = native_handle_psl_slice_error,
1126 .psl_interrupt = NULL,
1127 .ack_irq = native_ack_irq,
1128 .irq_wait = native_irq_wait,
1129 .attach_process = native_attach_process,
1130 .detach_process = native_detach_process,
1131 .support_attributes = native_support_attributes,
1132 .link_ok = cxl_adapter_link_ok,
1133 .release_afu = cxl_pci_release_afu,
1134 .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1135 .afu_check_and_enable = native_afu_check_and_enable,
1136 .afu_activate_mode = native_afu_activate_mode,
1137 .afu_deactivate_mode = native_afu_deactivate_mode,
1138 .afu_reset = native_afu_reset,
1139 .afu_cr_read8 = native_afu_cr_read8,
1140 .afu_cr_read16 = native_afu_cr_read16,
1141 .afu_cr_read32 = native_afu_cr_read32,
1142 .afu_cr_read64 = native_afu_cr_read64,
1143 .afu_cr_write8 = native_afu_cr_write8,
1144 .afu_cr_write16 = native_afu_cr_write16,
1145 .afu_cr_write32 = native_afu_cr_write32,
1146 .read_adapter_vpd = cxl_pci_read_adapter_vpd,