drivers/misc/cxl/pci.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/pci_regs.h>
  11 #include <linux/pci_ids.h>
  12 #include <linux/device.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/sort.h>
  17 #include <linux/pci.h>
  18 #include <linux/of.h>
  19 #include <linux/delay.h>
  20 #include <asm/opal.h>
  21 #include <asm/msi_bitmap.h>
  22 #include <asm/pci-bridge.h> /* for struct pci_controller */
  23 #include <asm/pnv-pci.h>
  24 #include <asm/io.h>
  25
  26 #include "cxl.h"
  27
  28
  29 #define CXL_PCI_VSEC_ID 0x1280
  30 #define CXL_VSEC_MIN_SIZE 0x80
  31
  32 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest)                   \
  33         {                                                       \
  34                 pci_read_config_word(dev, vsec + 0x6, dest);    \
  35                 *dest >>= 4;                                    \
  36         }
  37 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
  38         pci_read_config_byte(dev, vsec + 0x8, dest)
  39
  40 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
  41         pci_read_config_byte(dev, vsec + 0x9, dest)
  42 #define CXL_STATUS_SECOND_PORT  0x80
  43 #define CXL_STATUS_MSI_X_FULL   0x40
  44 #define CXL_STATUS_MSI_X_SINGLE 0x20
  45 #define CXL_STATUS_FLASH_RW     0x08
  46 #define CXL_STATUS_FLASH_RO     0x04
  47 #define CXL_STATUS_LOADABLE_AFU 0x02
  48 #define CXL_STATUS_LOADABLE_PSL 0x01
  49 /* If we see these features we won't try to use the card */
  50 #define CXL_UNSUPPORTED_FEATURES \
  51         (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
  52
  53 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
  54         pci_read_config_byte(dev, vsec + 0xa, dest)
  55 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
  56         pci_write_config_byte(dev, vsec + 0xa, val)
  57 #define CXL_VSEC_PROTOCOL_MASK   0xe0
  58 #define CXL_VSEC_PROTOCOL_1024TB 0x80
  59 #define CXL_VSEC_PROTOCOL_512TB  0x40
  60 #define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8 uses this */
  61 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
  62
  63 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
  64         pci_read_config_word(dev, vsec + 0xc, dest)
  65 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
  66         pci_read_config_byte(dev, vsec + 0xe, dest)
  67 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
  68         pci_read_config_byte(dev, vsec + 0xf, dest)
  69 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
  70         pci_read_config_word(dev, vsec + 0x10, dest)
  71
  72 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
  73         pci_read_config_byte(dev, vsec + 0x13, dest)
  74 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
  75         pci_write_config_byte(dev, vsec + 0x13, val)
  76 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
  77 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
  78 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
  79
  80 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
  81         pci_read_config_dword(dev, vsec + 0x20, dest)
  82 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
  83         pci_read_config_dword(dev, vsec + 0x24, dest)
  84 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
  85         pci_read_config_dword(dev, vsec + 0x28, dest)
  86 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
  87         pci_read_config_dword(dev, vsec + 0x2c, dest)
  88
  89
  90 /* This works a little different than the p1/p2 register accesses to make it
  91  * easier to pull out individual fields */
  92 #define AFUD_READ(afu, off)             in_be64(afu->afu_desc_mmio + off)
  93 #define EXTRACT_PPC_BIT(val, bit)       (!!(val & PPC_BIT(bit)))
  94 #define EXTRACT_PPC_BITS(val, bs, be)   ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
  95
  96 #define AFUD_READ_INFO(afu)             AFUD_READ(afu, 0x0)
  97 #define   AFUD_NUM_INTS_PER_PROC(val)   EXTRACT_PPC_BITS(val,  0, 15)
  98 #define   AFUD_NUM_PROCS(val)           EXTRACT_PPC_BITS(val, 16, 31)
  99 #define   AFUD_NUM_CRS(val)             EXTRACT_PPC_BITS(val, 32, 47)
 100 #define   AFUD_MULTIMODE(val)           EXTRACT_PPC_BIT(val, 48)
 101 #define   AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
 102 #define   AFUD_DEDICATED_PROCESS(val)   EXTRACT_PPC_BIT(val, 59)
 103 #define   AFUD_AFU_DIRECTED(val)        EXTRACT_PPC_BIT(val, 61)
 104 #define   AFUD_TIME_SLICED(val)         EXTRACT_PPC_BIT(val, 63)
 105 #define AFUD_READ_CR(afu)               AFUD_READ(afu, 0x20)
 106 #define   AFUD_CR_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 107 #define AFUD_READ_CR_OFF(afu)           AFUD_READ(afu, 0x28)
 108 #define AFUD_READ_PPPSA(afu)            AFUD_READ(afu, 0x30)
 109 #define   AFUD_PPPSA_PP(val)            EXTRACT_PPC_BIT(val, 6)
 110 #define   AFUD_PPPSA_PSA(val)           EXTRACT_PPC_BIT(val, 7)
 111 #define   AFUD_PPPSA_LEN(val)           EXTRACT_PPC_BITS(val, 8, 63)
 112 #define AFUD_READ_PPPSA_OFF(afu)        AFUD_READ(afu, 0x38)
 113 #define AFUD_READ_EB(afu)               AFUD_READ(afu, 0x40)
 114 #define   AFUD_EB_LEN(val)              EXTRACT_PPC_BITS(val, 8, 63)
 115 #define AFUD_READ_EB_OFF(afu)           AFUD_READ(afu, 0x48)
 116
 117 u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off)
 118 {
 119         u64 aligned_off = off & ~0x3L;
 120         u32 val;
 121
 122         val = cxl_afu_cr_read32(afu, cr, aligned_off);
 123         return (val >> ((off & 0x2) * 8)) & 0xffff;
 124 }
 125
 126 u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off)
 127 {
 128         u64 aligned_off = off & ~0x3L;
 129         u32 val;
 130
 131         val = cxl_afu_cr_read32(afu, cr, aligned_off);
 132         return (val >> ((off & 0x3) * 8)) & 0xff;
 133 }
 134
 135 static DEFINE_PCI_DEVICE_TABLE(cxl_pci_tbl) = {
 136         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
 137         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
 138         { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
 139         { PCI_DEVICE_CLASS(0x120000, ~0), },
 140
 141         { }
 142 };
 143 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
 144
 145
 146 /*
 147  * Mostly using these wrappers to avoid confusion:
 148  * priv 1 is BAR2, while priv 2 is BAR0
 149  */
 150 static inline resource_size_t p1_base(struct pci_dev *dev)
 151 {
 152         return pci_resource_start(dev, 2);
 153 }
 154
 155 static inline resource_size_t p1_size(struct pci_dev *dev)
 156 {
 157         return pci_resource_len(dev, 2);
 158 }
 159
 160 static inline resource_size_t p2_base(struct pci_dev *dev)
 161 {
 162         return pci_resource_start(dev, 0);
 163 }
 164
 165 static inline resource_size_t p2_size(struct pci_dev *dev)
 166 {
 167         return pci_resource_len(dev, 0);
 168 }
 169
 170 static int find_cxl_vsec(struct pci_dev *dev)
 171 {
 172         int vsec = 0;
 173         u16 val;
 174
 175         while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
 176                 pci_read_config_word(dev, vsec + 0x4, &val);
 177                 if (val == CXL_PCI_VSEC_ID)
 178                         return vsec;
 179         }
 180         return 0;
 181
 182 }
 183
 184 static void dump_cxl_config_space(struct pci_dev *dev)
 185 {
 186         int vsec;
 187         u32 val;
 188
 189         dev_info(&dev->dev, "dump_cxl_config_space\n");
 190
 191         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
 192         dev_info(&dev->dev, "BAR0: %#.8x\n", val);
 193         pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
 194         dev_info(&dev->dev, "BAR1: %#.8x\n", val);
 195         pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
 196         dev_info(&dev->dev, "BAR2: %#.8x\n", val);
 197         pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
 198         dev_info(&dev->dev, "BAR3: %#.8x\n", val);
 199         pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
 200         dev_info(&dev->dev, "BAR4: %#.8x\n", val);
 201         pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
 202         dev_info(&dev->dev, "BAR5: %#.8x\n", val);
 203
 204         dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
 205                 p1_base(dev), p1_size(dev));
 206         dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
 207                 p1_base(dev), p2_size(dev));
 208         dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
 209                 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
 210
 211         if (!(vsec = find_cxl_vsec(dev)))
 212                 return;
 213
 214 #define show_reg(name, what) \
 215         dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
 216
 217         pci_read_config_dword(dev, vsec + 0x0, &val);
 218         show_reg("Cap ID", (val >> 0) & 0xffff);
 219         show_reg("Cap Ver", (val >> 16) & 0xf);
 220         show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
 221         pci_read_config_dword(dev, vsec + 0x4, &val);
 222         show_reg("VSEC ID", (val >> 0) & 0xffff);
 223         show_reg("VSEC Rev", (val >> 16) & 0xf);
 224         show_reg("VSEC Length", (val >> 20) & 0xfff);
 225         pci_read_config_dword(dev, vsec + 0x8, &val);
 226         show_reg("Num AFUs", (val >> 0) & 0xff);
 227         show_reg("Status", (val >> 8) & 0xff);
 228         show_reg("Mode Control", (val >> 16) & 0xff);
 229         show_reg("Reserved", (val >> 24) & 0xff);
 230         pci_read_config_dword(dev, vsec + 0xc, &val);
 231         show_reg("PSL Rev", (val >> 0) & 0xffff);
 232         show_reg("CAIA Ver", (val >> 16) & 0xffff);
 233         pci_read_config_dword(dev, vsec + 0x10, &val);
 234         show_reg("Base Image Rev", (val >> 0) & 0xffff);
 235         show_reg("Reserved", (val >> 16) & 0x0fff);
 236         show_reg("Image Control", (val >> 28) & 0x3);
 237         show_reg("Reserved", (val >> 30) & 0x1);
 238         show_reg("Image Loaded", (val >> 31) & 0x1);
 239
 240         pci_read_config_dword(dev, vsec + 0x14, &val);
 241         show_reg("Reserved", val);
 242         pci_read_config_dword(dev, vsec + 0x18, &val);
 243         show_reg("Reserved", val);
 244         pci_read_config_dword(dev, vsec + 0x1c, &val);
 245         show_reg("Reserved", val);
 246
 247         pci_read_config_dword(dev, vsec + 0x20, &val);
 248         show_reg("AFU Descriptor Offset", val);
 249         pci_read_config_dword(dev, vsec + 0x24, &val);
 250         show_reg("AFU Descriptor Size", val);
 251         pci_read_config_dword(dev, vsec + 0x28, &val);
 252         show_reg("Problem State Offset", val);
 253         pci_read_config_dword(dev, vsec + 0x2c, &val);
 254         show_reg("Problem State Size", val);
 255
 256         pci_read_config_dword(dev, vsec + 0x30, &val);
 257         show_reg("Reserved", val);
 258         pci_read_config_dword(dev, vsec + 0x34, &val);
 259         show_reg("Reserved", val);
 260         pci_read_config_dword(dev, vsec + 0x38, &val);
 261         show_reg("Reserved", val);
 262         pci_read_config_dword(dev, vsec + 0x3c, &val);
 263         show_reg("Reserved", val);
 264
 265         pci_read_config_dword(dev, vsec + 0x40, &val);
 266         show_reg("PSL Programming Port", val);
 267         pci_read_config_dword(dev, vsec + 0x44, &val);
 268         show_reg("PSL Programming Control", val);
 269
 270         pci_read_config_dword(dev, vsec + 0x48, &val);
 271         show_reg("Reserved", val);
 272         pci_read_config_dword(dev, vsec + 0x4c, &val);
 273         show_reg("Reserved", val);
 274
 275         pci_read_config_dword(dev, vsec + 0x50, &val);
 276         show_reg("Flash Address Register", val);
 277         pci_read_config_dword(dev, vsec + 0x54, &val);
 278         show_reg("Flash Size Register", val);
 279         pci_read_config_dword(dev, vsec + 0x58, &val);
 280         show_reg("Flash Status/Control Register", val);
 281         pci_read_config_dword(dev, vsec + 0x58, &val);
 282         show_reg("Flash Data Port", val);
 283
 284 #undef show_reg
 285 }
 286
 287 static void dump_afu_descriptor(struct cxl_afu *afu)
 288 {
 289         u64 val;
 290
 291 #define show_reg(name, what) \
 292         dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
 293
 294         val = AFUD_READ_INFO(afu);
 295         show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
 296         show_reg("num_of_processes", AFUD_NUM_PROCS(val));
 297         show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
 298         show_reg("req_prog_mode", val & 0xffffULL);
 299
 300         val = AFUD_READ(afu, 0x8);
 301         show_reg("Reserved", val);
 302         val = AFUD_READ(afu, 0x10);
 303         show_reg("Reserved", val);
 304         val = AFUD_READ(afu, 0x18);
 305         show_reg("Reserved", val);
 306
 307         val = AFUD_READ_CR(afu);
 308         show_reg("Reserved", (val >> (63-7)) & 0xff);
 309         show_reg("AFU_CR_len", AFUD_CR_LEN(val));
 310
 311         val = AFUD_READ_CR_OFF(afu);
 312         show_reg("AFU_CR_offset", val);
 313
 314         val = AFUD_READ_PPPSA(afu);
 315         show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
 316         show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
 317
 318         val = AFUD_READ_PPPSA_OFF(afu);
 319         show_reg("PerProcessPSA_offset", val);
 320
 321         val = AFUD_READ_EB(afu);
 322         show_reg("Reserved", (val >> (63-7)) & 0xff);
 323         show_reg("AFU_EB_len", AFUD_EB_LEN(val));
 324
 325         val = AFUD_READ_EB_OFF(afu);
 326         show_reg("AFU_EB_offset", val);
 327
 328 #undef show_reg
 329 }
 330
 331 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
 332 {
 333         struct device_node *np;
 334         const __be32 *prop;
 335         u64 psl_dsnctl;
 336         u64 chipid;
 337
 338         if (!(np = pnv_pci_get_phb_node(dev)))
 339                 return -ENODEV;
 340
 341         while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
 342                 np = of_get_next_parent(np);
 343         if (!np)
 344                 return -ENODEV;
 345         chipid = be32_to_cpup(prop);
 346         of_node_put(np);
 347
 348         /* Tell PSL where to route data to */
 349         psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
 350         cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
 351         cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
 352         /* snoop write mask */
 353         cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
 354         /* set fir_accum */
 355         cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
 356         /* for debugging with trace arrays */
 357         cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
 358
 359         return 0;
 360 }
 361
 362 static int init_implementation_afu_regs(struct cxl_afu *afu)
 363 {
 364         /* read/write masks for this slice */
 365         cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
 366         /* APC read/write masks for this slice */
 367         cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
 368         /* for debugging with trace arrays */
 369         cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
 370         cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
 371
 372         return 0;
 373 }
 374
 375 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
 376                          unsigned int virq)
 377 {
 378         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 379
 380         return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
 381 }
 382
 383 int cxl_update_image_control(struct cxl *adapter)
 384 {
 385         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 386         int rc;
 387         int vsec;
 388         u8 image_state;
 389
 390         if (!(vsec = find_cxl_vsec(dev))) {
 391                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 392                 return -ENODEV;
 393         }
 394
 395         if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
 396                 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
 397                 return rc;
 398         }
 399
 400         if (adapter->perst_loads_image)
 401                 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
 402         else
 403                 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
 404
 405         if (adapter->perst_select_user)
 406                 image_state |= CXL_VSEC_PERST_SELECT_USER;
 407         else
 408                 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
 409
 410         if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
 411                 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
 412                 return rc;
 413         }
 414
 415         return 0;
 416 }
 417
 418 int cxl_alloc_one_irq(struct cxl *adapter)
 419 {
 420         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 421
 422         return pnv_cxl_alloc_hwirqs(dev, 1);
 423 }
 424
 425 void cxl_release_one_irq(struct cxl *adapter, int hwirq)
 426 {
 427         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 428
 429         return pnv_cxl_release_hwirqs(dev, hwirq, 1);
 430 }
 431
 432 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num)
 433 {
 434         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 435
 436         return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
 437 }
 438
 439 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter)
 440 {
 441         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 442
 443         pnv_cxl_release_hwirq_ranges(irqs, dev);
 444 }
 445
 446 static int setup_cxl_bars(struct pci_dev *dev)
 447 {
 448         /* Safety check in case we get backported to < 3.17 without M64 */
 449         if ((p1_base(dev) < 0x100000000ULL) ||
 450             (p2_base(dev) < 0x100000000ULL)) {
 451                 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
 452                 return -ENODEV;
 453         }
 454
 455         /*
 456          * BAR 4/5 has a special meaning for CXL and must be programmed with a
 457          * special value corresponding to the CXL protocol address range.
 458          * For POWER 8 that means bits 48:49 must be set to 10
 459          */
 460         pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
 461         pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
 462
 463         return 0;
 464 }
 465
 466 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
 467 static int switch_card_to_cxl(struct pci_dev *dev)
 468 {
 469         int vsec;
 470         u8 val;
 471         int rc;
 472
 473         dev_info(&dev->dev, "switch card to CXL\n");
 474
 475         if (!(vsec = find_cxl_vsec(dev))) {
 476                 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
 477                 return -ENODEV;
 478         }
 479
 480         if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
 481                 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
 482                 return rc;
 483         }
 484         val &= ~CXL_VSEC_PROTOCOL_MASK;
 485         val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
 486         if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
 487                 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
 488                 return rc;
 489         }
 490         /*
 491          * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
 492          * we must wait 100ms after this mode switch before touching
 493          * PCIe config space.
 494          */
 495         msleep(100);
 496
 497         return 0;
 498 }
 499
 500 static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
 501 {
 502         u64 p1n_base, p2n_base, afu_desc;
 503         const u64 p1n_size = 0x100;
 504         const u64 p2n_size = 0x1000;
 505
 506         p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
 507         p2n_base = p2_base(dev) + (afu->slice * p2n_size);
 508         afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size));
 509         afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size);
 510
 511         if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size)))
 512                 goto err;
 513         if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
 514                 goto err1;
 515         if (afu_desc) {
 516                 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size)))
 517                         goto err2;
 518         }
 519
 520         return 0;
 521 err2:
 522         iounmap(afu->p2n_mmio);
 523 err1:
 524         iounmap(afu->p1n_mmio);
 525 err:
 526         dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
 527         return -ENOMEM;
 528 }
 529
 530 static void cxl_unmap_slice_regs(struct cxl_afu *afu)
 531 {
 532         if (afu->p1n_mmio)
 533                 iounmap(afu->p2n_mmio);
 534         if (afu->p1n_mmio)
 535                 iounmap(afu->p1n_mmio);
 536 }
 537
 538 static void cxl_release_afu(struct device *dev)
 539 {
 540         struct cxl_afu *afu = to_cxl_afu(dev);
 541
 542         pr_devel("cxl_release_afu\n");
 543
 544         kfree(afu);
 545 }
 546
 547 static struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
 548 {
 549         struct cxl_afu *afu;
 550
 551         if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
 552                 return NULL;
 553
 554         afu->adapter = adapter;
 555         afu->dev.parent = &adapter->dev;
 556         afu->dev.release = cxl_release_afu;
 557         afu->slice = slice;
 558         idr_init(&afu->contexts_idr);
 559         mutex_init(&afu->contexts_lock);
 560         spin_lock_init(&afu->afu_cntl_lock);
 561         mutex_init(&afu->spa_mutex);
 562
 563         afu->prefault_mode = CXL_PREFAULT_NONE;
 564         afu->irqs_max = afu->adapter->user_irqs;
 565
 566         return afu;
 567 }
 568
 569 /* Expects AFU struct to have recently been zeroed out */
 570 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
 571 {
 572         u64 val;
 573
 574         val = AFUD_READ_INFO(afu);
 575         afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
 576         afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
 577         afu->crs_num = AFUD_NUM_CRS(val);
 578
 579         if (AFUD_AFU_DIRECTED(val))
 580                 afu->modes_supported |= CXL_MODE_DIRECTED;
 581         if (AFUD_DEDICATED_PROCESS(val))
 582                 afu->modes_supported |= CXL_MODE_DEDICATED;
 583         if (AFUD_TIME_SLICED(val))
 584                 afu->modes_supported |= CXL_MODE_TIME_SLICED;
 585
 586         val = AFUD_READ_PPPSA(afu);
 587         afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
 588         afu->psa = AFUD_PPPSA_PSA(val);
 589         if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
 590                 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
 591
 592         val = AFUD_READ_CR(afu);
 593         afu->crs_len = AFUD_CR_LEN(val) * 256;
 594         afu->crs_offset = AFUD_READ_CR_OFF(afu);
 595
 596
 597         /* eb_len is in multiple of 4K */
 598         afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
 599         afu->eb_offset = AFUD_READ_EB_OFF(afu);
 600
 601         /* eb_off is 4K aligned so lower 12 bits are always zero */
 602         if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
 603                 dev_warn(&afu->dev,
 604                          "Invalid AFU error buffer offset %Lx\n",
 605                          afu->eb_offset);
 606                 dev_info(&afu->dev,
 607                          "Ignoring AFU error buffer in the descriptor\n");
 608                 /* indicate that no afu buffer exists */
 609                 afu->eb_len = 0;
 610         }
 611
 612         return 0;
 613 }
 614
 615 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
 616 {
 617         int i;
 618
 619         if (afu->psa && afu->adapter->ps_size <
 620                         (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
 621                 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
 622                 return -ENODEV;
 623         }
 624
 625         if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
 626                 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
 627
 628         for (i = 0; i < afu->crs_num; i++) {
 629                 if ((cxl_afu_cr_read32(afu, i, 0) == 0)) {
 630                         dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
 631                         return -EINVAL;
 632                 }
 633         }
 634
 635         return 0;
 636 }
 637
 638 static int sanitise_afu_regs(struct cxl_afu *afu)
 639 {
 640         u64 reg;
 641
 642         /*
 643          * Clear out any regs that contain either an IVTE or address or may be
 644          * waiting on an acknowledgement to try to be a bit safer as we bring
 645          * it online
 646          */
 647         reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
 648         if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
 649                 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#.16llx\n", reg);
 650                 if (cxl_afu_reset(afu))
 651                         return -EIO;
 652                 if (cxl_afu_disable(afu))
 653                         return -EIO;
 654                 if (cxl_psl_purge(afu))
 655                         return -EIO;
 656         }
 657         cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
 658         cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
 659         cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
 660         cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
 661         cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
 662         cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
 663         cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
 664         cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
 665         cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
 666         cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
 667         cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
 668         reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
 669         if (reg) {
 670                 dev_warn(&afu->dev, "AFU had pending DSISR: %#.16llx\n", reg);
 671                 if (reg & CXL_PSL_DSISR_TRANS)
 672                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
 673                 else
 674                         cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
 675         }
 676         reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
 677         if (reg) {
 678                 if (reg & ~0xffff)
 679                         dev_warn(&afu->dev, "AFU had pending SERR: %#.16llx\n", reg);
 680                 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
 681         }
 682         reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
 683         if (reg) {
 684                 dev_warn(&afu->dev, "AFU had pending error status: %#.16llx\n", reg);
 685                 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
 686         }
 687
 688         return 0;
 689 }
 690
 691 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
 692 /*
 693  * afu_eb_read:
 694  * Called from sysfs and reads the afu error info buffer. The h/w only supports
 695  * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
 696  * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
 697  */
 698 ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 699                                 loff_t off, size_t count)
 700 {
 701         loff_t aligned_start, aligned_end;
 702         size_t aligned_length;
 703         void *tbuf;
 704         const void __iomem *ebuf = afu->afu_desc_mmio + afu->eb_offset;
 705
 706         if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
 707                 return 0;
 708
 709         /* calculate aligned read window */
 710         count = min((size_t)(afu->eb_len - off), count);
 711         aligned_start = round_down(off, 8);
 712         aligned_end = round_up(off + count, 8);
 713         aligned_length = aligned_end - aligned_start;
 714
 715         /* max we can copy in one read is PAGE_SIZE */
 716         if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
 717                 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
 718                 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
 719         }
 720
 721         /* use bounce buffer for copy */
 722         tbuf = (void *)__get_free_page(GFP_TEMPORARY);
 723         if (!tbuf)
 724                 return -ENOMEM;
 725
 726         /* perform aligned read from the mmio region */
 727         memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
 728         memcpy(buf, tbuf + (off & 0x7), count);
 729
 730         free_page((unsigned long)tbuf);
 731
 732         return count;
 733 }
 734
 735 static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
 736 {
 737         struct cxl_afu *afu;
 738         bool free = true;
 739         int rc;
 740
 741         if (!(afu = cxl_alloc_afu(adapter, slice)))
 742                 return -ENOMEM;
 743
 744         if ((rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice)))
 745                 goto err1;
 746
 747         if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
 748                 goto err1;
 749
 750         if ((rc = sanitise_afu_regs(afu)))
 751                 goto err2;
 752
 753         /* We need to reset the AFU before we can read the AFU descriptor */
 754         if ((rc = cxl_afu_reset(afu)))
 755                 goto err2;
 756
 757         if (cxl_verbose)
 758                 dump_afu_descriptor(afu);
 759
 760         if ((rc = cxl_read_afu_descriptor(afu)))
 761                 goto err2;
 762
 763         if ((rc = cxl_afu_descriptor_looks_ok(afu)))
 764                 goto err2;
 765
 766         if ((rc = init_implementation_afu_regs(afu)))
 767                 goto err2;
 768
 769         if ((rc = cxl_register_serr_irq(afu)))
 770                 goto err2;
 771
 772         if ((rc = cxl_register_psl_irq(afu)))
 773                 goto err3;
 774
 775         /* Don't care if this fails */
 776         cxl_debugfs_afu_add(afu);
 777
 778         /*
 779          * After we call this function we must not free the afu directly, even
 780          * if it returns an error!
 781          */
 782         if ((rc = cxl_register_afu(afu)))
 783                 goto err_put1;
 784
 785         if ((rc = cxl_sysfs_afu_add(afu)))
 786                 goto err_put1;
 787
 788
 789         if ((rc = cxl_afu_select_best_mode(afu)))
 790                 goto err_put2;
 791
 792         adapter->afu[afu->slice] = afu;
 793
 794         return 0;
 795
 796 err_put2:
 797         cxl_sysfs_afu_remove(afu);
 798 err_put1:
 799         device_unregister(&afu->dev);
 800         free = false;
 801         cxl_debugfs_afu_remove(afu);
 802         cxl_release_psl_irq(afu);
 803 err3:
 804         cxl_release_serr_irq(afu);
 805 err2:
 806         cxl_unmap_slice_regs(afu);
 807 err1:
 808         if (free)
 809                 kfree(afu);
 810         return rc;
 811 }
 812
 813 static void cxl_remove_afu(struct cxl_afu *afu)
 814 {
 815         pr_devel("cxl_remove_afu\n");
 816
 817         if (!afu)
 818                 return;
 819
 820         cxl_sysfs_afu_remove(afu);
 821         cxl_debugfs_afu_remove(afu);
 822
 823         spin_lock(&afu->adapter->afu_list_lock);
 824         afu->adapter->afu[afu->slice] = NULL;
 825         spin_unlock(&afu->adapter->afu_list_lock);
 826
 827         cxl_context_detach_all(afu);
 828         cxl_afu_deactivate_mode(afu);
 829
 830         cxl_release_psl_irq(afu);
 831         cxl_release_serr_irq(afu);
 832         cxl_unmap_slice_regs(afu);
 833
 834         device_unregister(&afu->dev);
 835 }
 836
 837 int cxl_reset(struct cxl *adapter)
 838 {
 839         struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
 840         int rc;
 841         int i;
 842         u32 val;
 843
 844         dev_info(&dev->dev, "CXL reset\n");
 845
 846         for (i = 0; i < adapter->slices; i++)
 847                 cxl_remove_afu(adapter->afu[i]);
 848
 849         /* pcie_warm_reset requests a fundamental pci reset which includes a
 850          * PERST assert/deassert.  PERST triggers a loading of the image
 851          * if "user" or "factory" is selected in sysfs */
 852         if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
 853                 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
 854                 return rc;
 855         }
 856
 857         /* the PERST done above fences the PHB.  So, reset depends on EEH
 858          * to unbind the driver, tell Sapphire to reinit the PHB, and rebind
 859          * the driver.  Do an mmio read explictly to ensure EEH notices the
 860          * fenced PHB.  Retry for a few seconds before giving up. */
 861         i = 0;
 862         while (((val = mmio_read32be(adapter->p1_mmio)) != 0xffffffff) &&
 863                 (i < 5)) {
 864                 msleep(500);
 865                 i++;
 866         }
 867
 868         if (val != 0xffffffff)
 869                 dev_err(&dev->dev, "cxl: PERST failed to trigger EEH\n");
 870
 871         return rc;
 872 }
 873
 874 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
 875 {
 876         if (pci_request_region(dev, 2, "priv 2 regs"))
 877                 goto err1;
 878         if (pci_request_region(dev, 0, "priv 1 regs"))
 879                 goto err2;
 880
 881         pr_devel("cxl_map_adapter_regs: p1: %#.16llx %#llx, p2: %#.16llx %#llx",
 882                         p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
 883
 884         if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
 885                 goto err3;
 886
 887         if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
 888                 goto err4;
 889
 890         return 0;
 891
 892 err4:
 893         iounmap(adapter->p1_mmio);
 894         adapter->p1_mmio = NULL;
 895 err3:
 896         pci_release_region(dev, 0);
 897 err2:
 898         pci_release_region(dev, 2);
 899 err1:
 900         return -ENOMEM;
 901 }
 902
 903 static void cxl_unmap_adapter_regs(struct cxl *adapter)
 904 {
 905         if (adapter->p1_mmio)
 906                 iounmap(adapter->p1_mmio);
 907         if (adapter->p2_mmio)
 908                 iounmap(adapter->p2_mmio);
 909 }
 910
 911 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
 912 {
 913         int vsec;
 914         u32 afu_desc_off, afu_desc_size;
 915         u32 ps_off, ps_size;
 916         u16 vseclen;
 917         u8 image_state;
 918
 919         if (!(vsec = find_cxl_vsec(dev))) {
 920                 dev_err(&adapter->dev, "ABORTING: CXL VSEC not found!\n");
 921                 return -ENODEV;
 922         }
 923
 924         CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
 925         if (vseclen < CXL_VSEC_MIN_SIZE) {
 926                 pr_err("ABORTING: CXL VSEC too short\n");
 927                 return -EINVAL;
 928         }
 929
 930         CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
 931         CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
 932         CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
 933         CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
 934         CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
 935         CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
 936         adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
 937         adapter->perst_loads_image = true;
 938         adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
 939
 940         CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
 941         CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
 942         CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
 943         CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
 944         CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
 945
 946         /* Convert everything to bytes, because there is NO WAY I'd look at the
 947          * code a month later and forget what units these are in ;-) */
 948         adapter->ps_off = ps_off * 64 * 1024;
 949         adapter->ps_size = ps_size * 64 * 1024;
 950         adapter->afu_desc_off = afu_desc_off * 64 * 1024;
 951         adapter->afu_desc_size = afu_desc_size *64 * 1024;
 952
 953         /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
 954         adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
 955
 956         return 0;
 957 }
 958
 959 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
 960 {
 961         if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
 962                 return -EBUSY;
 963
 964         if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
 965                 dev_err(&adapter->dev, "ABORTING: CXL requires unsupported features\n");
 966                 return -EINVAL;
 967         }
 968
 969         if (!adapter->slices) {
 970                 /* Once we support dynamic reprogramming we can use the card if
 971                  * it supports loadable AFUs */
 972                 dev_err(&adapter->dev, "ABORTING: Device has no AFUs\n");
 973                 return -EINVAL;
 974         }
 975
 976         if (!adapter->afu_desc_off || !adapter->afu_desc_size) {
 977                 dev_err(&adapter->dev, "ABORTING: VSEC shows no AFU descriptors\n");
 978                 return -EINVAL;
 979         }
 980
 981         if (adapter->ps_size > p2_size(dev) - adapter->ps_off) {
 982                 dev_err(&adapter->dev, "ABORTING: Problem state size larger than "
 983                                    "available in BAR2: 0x%llx > 0x%llx\n",
 984                          adapter->ps_size, p2_size(dev) - adapter->ps_off);
 985                 return -EINVAL;
 986         }
 987
 988         return 0;
 989 }
 990
 991 static void cxl_release_adapter(struct device *dev)
 992 {
 993         struct cxl *adapter = to_cxl_adapter(dev);
 994
 995         pr_devel("cxl_release_adapter\n");
 996
 997         kfree(adapter);
 998 }
 999
1000 static struct cxl *cxl_alloc_adapter(struct pci_dev *dev)
1001 {
1002         struct cxl *adapter;
1003
1004         if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
1005                 return NULL;
1006
1007         adapter->dev.parent = &dev->dev;
1008         adapter->dev.release = cxl_release_adapter;
1009         pci_set_drvdata(dev, adapter);
1010         spin_lock_init(&adapter->afu_list_lock);
1011
1012         return adapter;
1013 }
1014
1015 static int sanitise_adapter_regs(struct cxl *adapter)
1016 {
1017         cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
1018         return cxl_tlb_slb_invalidate(adapter);
1019 }
1020
1021 static struct cxl *cxl_init_adapter(struct pci_dev *dev)
1022 {
1023         struct cxl *adapter;
1024         bool free = true;
1025         int rc;
1026
1027
1028         if (!(adapter = cxl_alloc_adapter(dev)))
1029                 return ERR_PTR(-ENOMEM);
1030
1031         if ((rc = switch_card_to_cxl(dev)))
1032                 goto err1;
1033
1034         if ((rc = cxl_alloc_adapter_nr(adapter)))
1035                 goto err1;
1036
1037         if ((rc = dev_set_name(&adapter->dev, "card%i", adapter->adapter_num)))
1038                 goto err2;
1039
1040         if ((rc = cxl_read_vsec(adapter, dev)))
1041                 goto err2;
1042
1043         if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1044                 goto err2;
1045
1046         if ((rc = cxl_update_image_control(adapter)))
1047                 goto err2;
1048
1049         if ((rc = cxl_map_adapter_regs(adapter, dev)))
1050                 goto err2;
1051
1052         if ((rc = sanitise_adapter_regs(adapter)))
1053                 goto err2;
1054
1055         if ((rc = init_implementation_adapter_regs(adapter, dev)))
1056                 goto err3;
1057
1058         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
1059                 goto err3;
1060
1061         /* If recovery happened, the last step is to turn on snooping.
1062          * In the non-recovery case this has no effect */
1063         if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) {
1064                 goto err3;
1065         }
1066
1067         if ((rc = cxl_register_psl_err_irq(adapter)))
1068                 goto err3;
1069
1070         /* Don't care if this one fails: */
1071         cxl_debugfs_adapter_add(adapter);
1072
1073         /*
1074          * After we call this function we must not free the adapter directly,
1075          * even if it returns an error!
1076          */
1077         if ((rc = cxl_register_adapter(adapter)))
1078                 goto err_put1;
1079
1080         if ((rc = cxl_sysfs_adapter_add(adapter)))
1081                 goto err_put1;
1082
1083         return adapter;
1084
1085 err_put1:
1086         device_unregister(&adapter->dev);
1087         free = false;
1088         cxl_debugfs_adapter_remove(adapter);
1089         cxl_release_psl_err_irq(adapter);
1090 err3:
1091         cxl_unmap_adapter_regs(adapter);
1092 err2:
1093         cxl_remove_adapter_nr(adapter);
1094 err1:
1095         if (free)
1096                 kfree(adapter);
1097         return ERR_PTR(rc);
1098 }
1099
1100 static void cxl_remove_adapter(struct cxl *adapter)
1101 {
1102         struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1103
1104         pr_devel("cxl_release_adapter\n");
1105
1106         cxl_sysfs_adapter_remove(adapter);
1107         cxl_debugfs_adapter_remove(adapter);
1108         cxl_release_psl_err_irq(adapter);
1109         cxl_unmap_adapter_regs(adapter);
1110         cxl_remove_adapter_nr(adapter);
1111
1112         device_unregister(&adapter->dev);
1113
1114         pci_release_region(pdev, 0);
1115         pci_release_region(pdev, 2);
1116         pci_disable_device(pdev);
1117 }
1118
1119 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1120 {
1121         struct cxl *adapter;
1122         int slice;
1123         int rc;
1124
1125         pci_dev_get(dev);
1126
1127         if (cxl_verbose)
1128                 dump_cxl_config_space(dev);
1129
1130         if ((rc = setup_cxl_bars(dev)))
1131                 return rc;
1132
1133         if ((rc = pci_enable_device(dev))) {
1134                 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1135                 return rc;
1136         }
1137
1138         adapter = cxl_init_adapter(dev);
1139         if (IS_ERR(adapter)) {
1140                 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1141                 return PTR_ERR(adapter);
1142         }
1143
1144         for (slice = 0; slice < adapter->slices; slice++) {
1145                 if ((rc = cxl_init_afu(adapter, slice, dev)))
1146                         dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1147         }
1148
1149         return 0;
1150 }
1151
1152 static void cxl_remove(struct pci_dev *dev)
1153 {
1154         struct cxl *adapter = pci_get_drvdata(dev);
1155         int afu;
1156
1157         dev_warn(&dev->dev, "pci remove\n");
1158
1159         /*
1160          * Lock to prevent someone grabbing a ref through the adapter list as
1161          * we are removing it
1162          */
1163         for (afu = 0; afu < adapter->slices; afu++)
1164                 cxl_remove_afu(adapter->afu[afu]);
1165         cxl_remove_adapter(adapter);
1166 }
1167
1168 struct pci_driver cxl_pci_driver = {
1169         .name = "cxl-pci",
1170         .id_table = cxl_pci_tbl,
1171         .probe = cxl_probe,
1172         .remove = cxl_remove,
1173 };