drivers/misc/pch_phub.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/fs.h>
  22 #include <linux/uaccess.h>
  23 #include <linux/string.h>
  24 #include <linux/pci.h>
  25 #include <linux/io.h>
  26 #include <linux/delay.h>
  27 #include <linux/mutex.h>
  28 #include <linux/if_ether.h>
  29 #include <linux/ctype.h>
  30 #include <linux/dmi.h>
  31
  32 #define PHUB_STATUS 0x00                /* Status Register offset */
  33 #define PHUB_CONTROL 0x04               /* Control Register offset */
  34 #define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
  35 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
  36 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
  37 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
  38                                                offset */
  39 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
  40                                                  offset */
  41 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
  42                                               (Intel EG20T PCH)*/
  43 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
  44                                                 offset(LAPIS Semicon ML7213)
  45                                               */
  46 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
  47                                                 offset(LAPIS Semicon ML7223)
  48                                               */
  49
  50 /* MAX number of INT_REDUCE_CONTROL registers */
  51 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128
  52 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801
  53 #define PCH_MINOR_NOS 1
  54 #define CLKCFG_CAN_50MHZ 0x12000000
  55 #define CLKCFG_CANCLK_MASK 0xFF000000
  56 #define CLKCFG_UART_MASK                        0xFFFFFF
  57
  58 /* CM-iTC */
  59 #define CLKCFG_UART_48MHZ                       (1 << 16)
  60 #define CLKCFG_BAUDDIV                          (2 << 20)
  61 #define CLKCFG_PLL2VCO                          (8 << 9)
  62 #define CLKCFG_UARTCLKSEL                       (1 << 18)
  63
  64 /* Macros for ML7213 */
  65 #define PCI_VENDOR_ID_ROHM                      0x10db
  66 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
  67
  68 /* Macros for ML7223 */
  69 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
  70 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
  71
  72 /* Macros for ML7831 */
  73 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
  74
  75 /* SROM ACCESS Macro */
  76 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
  77
  78 /* Registers address offset */
  79 #define PCH_PHUB_ID_REG                         0x0000
  80 #define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
  81 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
  82 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
  83 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
  84 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
  85 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
  86 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
  87 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
  88 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
  89 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
  90 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
  91 #define CLKCFG_REG_OFFSET                       0x500
  92 #define FUNCSEL_REG_OFFSET                      0x508
  93
  94 #define PCH_PHUB_OROM_SIZE 15360
  95
  96 /**
  97  * struct pch_phub_reg - PHUB register structure
  98  * @phub_id_reg:                        PHUB_ID register val
  99  * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
 100  * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
 101  * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
 102  * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
 103  * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
 104  * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
 105  * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
 106  * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
 107  * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
 108  * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
 109  * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
 110  * @clkcfg_reg:                         CLK CFG register val
 111  * @funcsel_reg:                        Function select register value
 112  * @pch_phub_base_address:              Register base address
 113  * @pch_phub_extrom_base_address:       external rom base address
 114  * @pch_mac_start_address:              MAC address area start address
 115  * @pch_opt_rom_start_address:          Option ROM start address
 116  * @ioh_type:                           Save IOH type
 117  * @pdev:                               pointer to pci device struct
 118  */
 119 struct pch_phub_reg {
 120         u32 phub_id_reg;
 121         u32 q_pri_val_reg;
 122         u32 rc_q_maxsize_reg;
 123         u32 bri_q_maxsize_reg;
 124         u32 comp_resp_timeout_reg;
 125         u32 bus_slave_control_reg;
 126         u32 deadlock_avoid_type_reg;
 127         u32 intpin_reg_wpermit_reg0;
 128         u32 intpin_reg_wpermit_reg1;
 129         u32 intpin_reg_wpermit_reg2;
 130         u32 intpin_reg_wpermit_reg3;
 131         u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
 132         u32 clkcfg_reg;
 133         u32 funcsel_reg;
 134         void __iomem *pch_phub_base_address;
 135         void __iomem *pch_phub_extrom_base_address;
 136         u32 pch_mac_start_address;
 137         u32 pch_opt_rom_start_address;
 138         int ioh_type;
 139         struct pci_dev *pdev;
 140 };
 141
 142 /* SROM SPEC for MAC address assignment offset */
 143 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
 144
 145 static DEFINE_MUTEX(pch_phub_mutex);
 146
 147 /**
 148  * pch_phub_read_modify_write_reg() - Reading modifying and writing register
 149  * @reg_addr_offset:    Register offset address value.
 150  * @data:               Writing value.
 151  * @mask:               Mask value.
 152  */
 153 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
 154                                            unsigned int reg_addr_offset,
 155                                            unsigned int data, unsigned int mask)
 156 {
 157         void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
 158         iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
 159 }
 160
 161 #ifdef CONFIG_PM
 162 /* pch_phub_save_reg_conf - saves register configuration */
 163 static void pch_phub_save_reg_conf(struct pci_dev *pdev)
 164 {
 165         unsigned int i;
 166         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 167
 168         void __iomem *p = chip->pch_phub_base_address;
 169
 170         chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
 171         chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 172         chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 173         chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 174         chip->comp_resp_timeout_reg =
 175                                 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 176         chip->bus_slave_control_reg =
 177                                 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 178         chip->deadlock_avoid_type_reg =
 179                                 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 180         chip->intpin_reg_wpermit_reg0 =
 181                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 182         chip->intpin_reg_wpermit_reg1 =
 183                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 184         chip->intpin_reg_wpermit_reg2 =
 185                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 186         chip->intpin_reg_wpermit_reg3 =
 187                                 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 188         dev_dbg(&pdev->dev, "%s : "
 189                 "chip->phub_id_reg=%x, "
 190                 "chip->q_pri_val_reg=%x, "
 191                 "chip->rc_q_maxsize_reg=%x, "
 192                 "chip->bri_q_maxsize_reg=%x, "
 193                 "chip->comp_resp_timeout_reg=%x, "
 194                 "chip->bus_slave_control_reg=%x, "
 195                 "chip->deadlock_avoid_type_reg=%x, "
 196                 "chip->intpin_reg_wpermit_reg0=%x, "
 197                 "chip->intpin_reg_wpermit_reg1=%x, "
 198                 "chip->intpin_reg_wpermit_reg2=%x, "
 199                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 200                 chip->phub_id_reg,
 201                 chip->q_pri_val_reg,
 202                 chip->rc_q_maxsize_reg,
 203                 chip->bri_q_maxsize_reg,
 204                 chip->comp_resp_timeout_reg,
 205                 chip->bus_slave_control_reg,
 206                 chip->deadlock_avoid_type_reg,
 207                 chip->intpin_reg_wpermit_reg0,
 208                 chip->intpin_reg_wpermit_reg1,
 209                 chip->intpin_reg_wpermit_reg2,
 210                 chip->intpin_reg_wpermit_reg3);
 211         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 212                 chip->int_reduce_control_reg[i] =
 213                     ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 214                 dev_dbg(&pdev->dev, "%s : "
 215                         "chip->int_reduce_control_reg[%d]=%x\n",
 216                         __func__, i, chip->int_reduce_control_reg[i]);
 217         }
 218         chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
 219         if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 220                 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
 221 }
 222
 223 /* pch_phub_restore_reg_conf - restore register configuration */
 224 static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
 225 {
 226         unsigned int i;
 227         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 228         void __iomem *p;
 229         p = chip->pch_phub_base_address;
 230
 231         iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
 232         iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 233         iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 234         iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 235         iowrite32(chip->comp_resp_timeout_reg,
 236                                         p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 237         iowrite32(chip->bus_slave_control_reg,
 238                                         p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 239         iowrite32(chip->deadlock_avoid_type_reg,
 240                                         p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 241         iowrite32(chip->intpin_reg_wpermit_reg0,
 242                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 243         iowrite32(chip->intpin_reg_wpermit_reg1,
 244                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 245         iowrite32(chip->intpin_reg_wpermit_reg2,
 246                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 247         iowrite32(chip->intpin_reg_wpermit_reg3,
 248                                         p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 249         dev_dbg(&pdev->dev, "%s : "
 250                 "chip->phub_id_reg=%x, "
 251                 "chip->q_pri_val_reg=%x, "
 252                 "chip->rc_q_maxsize_reg=%x, "
 253                 "chip->bri_q_maxsize_reg=%x, "
 254                 "chip->comp_resp_timeout_reg=%x, "
 255                 "chip->bus_slave_control_reg=%x, "
 256                 "chip->deadlock_avoid_type_reg=%x, "
 257                 "chip->intpin_reg_wpermit_reg0=%x, "
 258                 "chip->intpin_reg_wpermit_reg1=%x, "
 259                 "chip->intpin_reg_wpermit_reg2=%x, "
 260                 "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 261                 chip->phub_id_reg,
 262                 chip->q_pri_val_reg,
 263                 chip->rc_q_maxsize_reg,
 264                 chip->bri_q_maxsize_reg,
 265                 chip->comp_resp_timeout_reg,
 266                 chip->bus_slave_control_reg,
 267                 chip->deadlock_avoid_type_reg,
 268                 chip->intpin_reg_wpermit_reg0,
 269                 chip->intpin_reg_wpermit_reg1,
 270                 chip->intpin_reg_wpermit_reg2,
 271                 chip->intpin_reg_wpermit_reg3);
 272         for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 273                 iowrite32(chip->int_reduce_control_reg[i],
 274                         p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 275                 dev_dbg(&pdev->dev, "%s : "
 276                         "chip->int_reduce_control_reg[%d]=%x\n",
 277                         __func__, i, chip->int_reduce_control_reg[i]);
 278         }
 279
 280         iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
 281         if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 282                 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
 283 }
 284 #endif
 285
 286 /**
 287  * pch_phub_read_serial_rom() - Reading Serial ROM
 288  * @offset_address:     Serial ROM offset address to read.
 289  * @data:               Read buffer for specified Serial ROM value.
 290  */
 291 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
 292                                      unsigned int offset_address, u8 *data)
 293 {
 294         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 295                                                                 offset_address;
 296
 297         *data = ioread8(mem_addr);
 298 }
 299
 300 /**
 301  * pch_phub_write_serial_rom() - Writing Serial ROM
 302  * @offset_address:     Serial ROM offset address.
 303  * @data:               Serial ROM value to write.
 304  */
 305 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
 306                                      unsigned int offset_address, u8 data)
 307 {
 308         void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 309                                         (offset_address & PCH_WORD_ADDR_MASK);
 310         int i;
 311         unsigned int word_data;
 312         unsigned int pos;
 313         unsigned int mask;
 314         pos = (offset_address % 4) * 8;
 315         mask = ~(0xFF << pos);
 316
 317         iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
 318                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 319
 320         word_data = ioread32(mem_addr);
 321         iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
 322
 323         i = 0;
 324         while (ioread8(chip->pch_phub_extrom_base_address +
 325                                                 PHUB_STATUS) != 0x00) {
 326                 msleep(1);
 327                 if (i == PHUB_TIMEOUT)
 328                         return -ETIMEDOUT;
 329                 i++;
 330         }
 331
 332         iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
 333                         chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 334
 335         return 0;
 336 }
 337
 338 /**
 339  * pch_phub_read_serial_rom_val() - Read Serial ROM value
 340  * @offset_address:     Serial ROM address offset value.
 341  * @data:               Serial ROM value to read.
 342  */
 343 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
 344                                          unsigned int offset_address, u8 *data)
 345 {
 346         unsigned int mem_addr;
 347
 348         mem_addr = chip->pch_mac_start_address +
 349                         pch_phub_mac_offset[offset_address];
 350
 351         pch_phub_read_serial_rom(chip, mem_addr, data);
 352 }
 353
 354 /**
 355  * pch_phub_write_serial_rom_val() - writing Serial ROM value
 356  * @offset_address:     Serial ROM address offset value.
 357  * @data:               Serial ROM value.
 358  */
 359 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
 360                                          unsigned int offset_address, u8 data)
 361 {
 362         int retval;
 363         unsigned int mem_addr;
 364
 365         mem_addr = chip->pch_mac_start_address +
 366                         pch_phub_mac_offset[offset_address];
 367
 368         retval = pch_phub_write_serial_rom(chip, mem_addr, data);
 369
 370         return retval;
 371 }
 372
 373 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
 374  * for Gigabit Ethernet MAC address
 375  */
 376 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
 377 {
 378         int retval;
 379
 380         retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
 381         retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
 382         retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
 383         retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
 384
 385         retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
 386         retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
 387         retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
 388         retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
 389
 390         retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
 391         retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
 392         retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
 393         retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
 394
 395         retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
 396         retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
 397         retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
 398         retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
 399
 400         retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
 401         retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
 402         retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
 403         retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
 404
 405         retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
 406         retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
 407         retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
 408         retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
 409
 410         return retval;
 411 }
 412
 413 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
 414  * for Gigabit Ethernet MAC address
 415  */
 416 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
 417 {
 418         int retval;
 419         u32 offset_addr;
 420
 421         offset_addr = 0x200;
 422         retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
 423         retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
 424         retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
 425         retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
 426
 427         retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
 428         retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
 429         retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
 430         retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
 431
 432         retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
 433         retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
 434         retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
 435         retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
 436
 437         retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
 438         retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
 439         retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
 440         retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
 441
 442         retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
 443         retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
 444         retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
 445         retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
 446
 447         retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
 448         retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
 449         retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
 450         retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
 451
 452         return retval;
 453 }
 454
 455 /**
 456  * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
 457  * @offset_address:     Gigabit Ethernet MAC address offset value.
 458  * @data:               Buffer of the Gigabit Ethernet MAC address value.
 459  */
 460 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 461 {
 462         int i;
 463         for (i = 0; i < ETH_ALEN; i++)
 464                 pch_phub_read_serial_rom_val(chip, i, &data[i]);
 465 }
 466
 467 /**
 468  * pch_phub_write_gbe_mac_addr() - Write MAC address
 469  * @offset_address:     Gigabit Ethernet MAC address offset value.
 470  * @data:               Gigabit Ethernet MAC address value.
 471  */
 472 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 473 {
 474         int retval;
 475         int i;
 476
 477         if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
 478                 retval = pch_phub_gbe_serial_rom_conf(chip);
 479         else    /* ML7223 */
 480                 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
 481         if (retval)
 482                 return retval;
 483
 484         for (i = 0; i < ETH_ALEN; i++) {
 485                 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
 486                 if (retval)
 487                         return retval;
 488         }
 489
 490         return retval;
 491 }
 492
 493 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
 494                                  struct bin_attribute *attr, char *buf,
 495                                  loff_t off, size_t count)
 496 {
 497         unsigned int rom_signature;
 498         unsigned char rom_length;
 499         unsigned int tmp;
 500         unsigned int addr_offset;
 501         unsigned int orom_size;
 502         int ret;
 503         int err;
 504         ssize_t rom_size;
 505
 506         struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
 507
 508         ret = mutex_lock_interruptible(&pch_phub_mutex);
 509         if (ret) {
 510                 err = -ERESTARTSYS;
 511                 goto return_err_nomutex;
 512         }
 513
 514         /* Get Rom signature */
 515         chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 516         if (!chip->pch_phub_extrom_base_address)
 517                 goto exrom_map_err;
 518
 519         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
 520                                 (unsigned char *)&rom_signature);
 521         rom_signature &= 0xff;
 522         pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
 523                                 (unsigned char *)&tmp);
 524         rom_signature |= (tmp & 0xff) << 8;
 525         if (rom_signature == 0xAA55) {
 526                 pch_phub_read_serial_rom(chip,
 527                                          chip->pch_opt_rom_start_address + 2,
 528                                          &rom_length);
 529                 orom_size = rom_length * 512;
 530                 if (orom_size < off) {
 531                         addr_offset = 0;
 532                         goto return_ok;
 533                 }
 534                 if (orom_size < count) {
 535                         addr_offset = 0;
 536                         goto return_ok;
 537                 }
 538
 539                 for (addr_offset = 0; addr_offset < count; addr_offset++) {
 540                         pch_phub_read_serial_rom(chip,
 541                             chip->pch_opt_rom_start_address + addr_offset + off,
 542                             &buf[addr_offset]);
 543                 }
 544         } else {
 545                 err = -ENODATA;
 546                 goto return_err;
 547         }
 548 return_ok:
 549         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 550         mutex_unlock(&pch_phub_mutex);
 551         return addr_offset;
 552
 553 return_err:
 554         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 555 exrom_map_err:
 556         mutex_unlock(&pch_phub_mutex);
 557 return_err_nomutex:
 558         return err;
 559 }
 560
 561 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
 562                                   struct bin_attribute *attr,
 563                                   char *buf, loff_t off, size_t count)
 564 {
 565         int err;
 566         unsigned int addr_offset;
 567         int ret;
 568         ssize_t rom_size;
 569         struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
 570
 571         ret = mutex_lock_interruptible(&pch_phub_mutex);
 572         if (ret)
 573                 return -ERESTARTSYS;
 574
 575         if (off > PCH_PHUB_OROM_SIZE) {
 576                 addr_offset = 0;
 577                 goto return_ok;
 578         }
 579         if (count > PCH_PHUB_OROM_SIZE) {
 580                 addr_offset = 0;
 581                 goto return_ok;
 582         }
 583
 584         chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 585         if (!chip->pch_phub_extrom_base_address) {
 586                 err = -ENOMEM;
 587                 goto exrom_map_err;
 588         }
 589
 590         for (addr_offset = 0; addr_offset < count; addr_offset++) {
 591                 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
 592                         goto return_ok;
 593
 594                 ret = pch_phub_write_serial_rom(chip,
 595                             chip->pch_opt_rom_start_address + addr_offset + off,
 596                             buf[addr_offset]);
 597                 if (ret) {
 598                         err = ret;
 599                         goto return_err;
 600                 }
 601         }
 602
 603 return_ok:
 604         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 605         mutex_unlock(&pch_phub_mutex);
 606         return addr_offset;
 607
 608 return_err:
 609         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 610
 611 exrom_map_err:
 612         mutex_unlock(&pch_phub_mutex);
 613         return err;
 614 }
 615
 616 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
 617                             char *buf)
 618 {
 619         u8 mac[8];
 620         struct pch_phub_reg *chip = dev_get_drvdata(dev);
 621         ssize_t rom_size;
 622
 623         chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 624         if (!chip->pch_phub_extrom_base_address)
 625                 return -ENOMEM;
 626
 627         pch_phub_read_gbe_mac_addr(chip, mac);
 628         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 629
 630         return sprintf(buf, "%pM\n", mac);
 631 }
 632
 633 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
 634                              const char *buf, size_t count)
 635 {
 636         u8 mac[ETH_ALEN];
 637         ssize_t rom_size;
 638         struct pch_phub_reg *chip = dev_get_drvdata(dev);
 639         int ret;
 640
 641         if (!mac_pton(buf, mac))
 642                 return -EINVAL;
 643
 644         chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 645         if (!chip->pch_phub_extrom_base_address)
 646                 return -ENOMEM;
 647
 648         ret = pch_phub_write_gbe_mac_addr(chip, mac);
 649         pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 650         if (ret)
 651                 return ret;
 652
 653         return count;
 654 }
 655
 656 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
 657
 658 static struct bin_attribute pch_bin_attr = {
 659         .attr = {
 660                 .name = "pch_firmware",
 661                 .mode = S_IRUGO | S_IWUSR,
 662         },
 663         .size = PCH_PHUB_OROM_SIZE + 1,
 664         .read = pch_phub_bin_read,
 665         .write = pch_phub_bin_write,
 666 };
 667
 668 static int pch_phub_probe(struct pci_dev *pdev,
 669                                     const struct pci_device_id *id)
 670 {
 671         int ret;
 672         struct pch_phub_reg *chip;
 673
 674         chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
 675         if (chip == NULL)
 676                 return -ENOMEM;
 677
 678         ret = pci_enable_device(pdev);
 679         if (ret) {
 680                 dev_err(&pdev->dev,
 681                 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
 682                 goto err_pci_enable_dev;
 683         }
 684         dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
 685                 ret);
 686
 687         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 688         if (ret) {
 689                 dev_err(&pdev->dev,
 690                 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
 691                 goto err_req_regions;
 692         }
 693         dev_dbg(&pdev->dev, "%s : "
 694                 "pci_request_regions returns %d\n", __func__, ret);
 695
 696         chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
 697
 698
 699         if (chip->pch_phub_base_address == NULL) {
 700                 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 701                 ret = -ENOMEM;
 702                 goto err_pci_iomap;
 703         }
 704         dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
 705                 "in pch_phub_base_address variable is %p\n", __func__,
 706                 chip->pch_phub_base_address);
 707
 708         chip->pdev = pdev; /* Save pci device struct */
 709
 710         if (id->driver_data == 1) { /* EG20T PCH */
 711                 const char *board_name;
 712
 713                 ret = sysfs_create_file(&pdev->dev.kobj,
 714                                         &dev_attr_pch_mac.attr);
 715                 if (ret)
 716                         goto err_sysfs_create;
 717
 718                 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 719                 if (ret)
 720                         goto exit_bin_attr;
 721
 722                 pch_phub_read_modify_write_reg(chip,
 723                                                (unsigned int)CLKCFG_REG_OFFSET,
 724                                                CLKCFG_CAN_50MHZ,
 725                                                CLKCFG_CANCLK_MASK);
 726
 727                 /* quirk for CM-iTC board */
 728                 board_name = dmi_get_system_info(DMI_BOARD_NAME);
 729                 if (board_name && strstr(board_name, "CM-iTC"))
 730                         pch_phub_read_modify_write_reg(chip,
 731                                                 (unsigned int)CLKCFG_REG_OFFSET,
 732                                                 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
 733                                                 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
 734                                                 CLKCFG_UART_MASK);
 735
 736                 /* set the prefech value */
 737                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 738                 /* set the interrupt delay value */
 739                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 740                 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 741                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 742         } else if (id->driver_data == 2) { /* ML7213 IOH */
 743                 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 744                 if (ret)
 745                         goto err_sysfs_create;
 746                 /* set the prefech value
 747                  * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
 748                  * Device4(SDIO #0,1,2):f
 749                  * Device6(SATA 2):f
 750                  * Device8(USB OHCI #0/ USB EHCI #0):a
 751                  */
 752                 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
 753                 chip->pch_opt_rom_start_address =\
 754                                                  PCH_PHUB_ROM_START_ADDR_ML7213;
 755         } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
 756                 /* set the prefech value
 757                  * Device8(GbE)
 758                  */
 759                 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
 760                 /* set the interrupt delay value */
 761                 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
 762                 chip->pch_opt_rom_start_address =\
 763                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
 764                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 765         } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
 766                 ret = sysfs_create_file(&pdev->dev.kobj,
 767                                         &dev_attr_pch_mac.attr);
 768                 if (ret)
 769                         goto err_sysfs_create;
 770                 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 771                 if (ret)
 772                         goto exit_bin_attr;
 773                 /* set the prefech value
 774                  * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
 775                  * Device4(SDIO #0,1):f
 776                  * Device6(SATA 2):f
 777                  */
 778                 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
 779                 chip->pch_opt_rom_start_address =\
 780                                                  PCH_PHUB_ROM_START_ADDR_ML7223;
 781                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 782         } else if (id->driver_data == 5) { /* ML7831 */
 783                 ret = sysfs_create_file(&pdev->dev.kobj,
 784                                         &dev_attr_pch_mac.attr);
 785                 if (ret)
 786                         goto err_sysfs_create;
 787
 788                 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 789                 if (ret)
 790                         goto exit_bin_attr;
 791
 792                 /* set the prefech value */
 793                 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 794                 /* set the interrupt delay value */
 795                 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 796                 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 797                 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 798         }
 799
 800         chip->ioh_type = id->driver_data;
 801         pci_set_drvdata(pdev, chip);
 802
 803         return 0;
 804 exit_bin_attr:
 805         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 806
 807 err_sysfs_create:
 808         pci_iounmap(pdev, chip->pch_phub_base_address);
 809 err_pci_iomap:
 810         pci_release_regions(pdev);
 811 err_req_regions:
 812         pci_disable_device(pdev);
 813 err_pci_enable_dev:
 814         kfree(chip);
 815         dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
 816         return ret;
 817 }
 818
 819 static void pch_phub_remove(struct pci_dev *pdev)
 820 {
 821         struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 822
 823         sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 824         sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 825         pci_iounmap(pdev, chip->pch_phub_base_address);
 826         pci_release_regions(pdev);
 827         pci_disable_device(pdev);
 828         kfree(chip);
 829 }
 830
 831 #ifdef CONFIG_PM
 832
 833 static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
 834 {
 835         int ret;
 836
 837         pch_phub_save_reg_conf(pdev);
 838         ret = pci_save_state(pdev);
 839         if (ret) {
 840                 dev_err(&pdev->dev,
 841                         " %s -pci_save_state returns %d\n", __func__, ret);
 842                 return ret;
 843         }
 844         pci_enable_wake(pdev, PCI_D3hot, 0);
 845         pci_disable_device(pdev);
 846         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 847
 848         return 0;
 849 }
 850
 851 static int pch_phub_resume(struct pci_dev *pdev)
 852 {
 853         int ret;
 854
 855         pci_set_power_state(pdev, PCI_D0);
 856         pci_restore_state(pdev);
 857         ret = pci_enable_device(pdev);
 858         if (ret) {
 859                 dev_err(&pdev->dev,
 860                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
 861                 return ret;
 862         }
 863
 864         pci_enable_wake(pdev, PCI_D3hot, 0);
 865         pch_phub_restore_reg_conf(pdev);
 866
 867         return 0;
 868 }
 869 #else
 870 #define pch_phub_suspend NULL
 871 #define pch_phub_resume NULL
 872 #endif /* CONFIG_PM */
 873
 874 static struct pci_device_id pch_phub_pcidev_id[] = {
 875         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
 876         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
 877         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
 878         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
 879         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5,  },
 880         { }
 881 };
 882 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
 883
 884 static struct pci_driver pch_phub_driver = {
 885         .name = "pch_phub",
 886         .id_table = pch_phub_pcidev_id,
 887         .probe = pch_phub_probe,
 888         .remove = pch_phub_remove,
 889         .suspend = pch_phub_suspend,
 890         .resume = pch_phub_resume
 891 };
 892
 893 module_pci_driver(pch_phub_driver);
 894
 895 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
 896 MODULE_LICENSE("GPL");