2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 uint dsaddr; /* SDMA system address register */
35 uint blkattr; /* Block attributes register */
36 uint cmdarg; /* Command argument register */
37 uint xfertyp; /* Transfer type register */
38 uint cmdrsp0; /* Command response 0 register */
39 uint cmdrsp1; /* Command response 1 register */
40 uint cmdrsp2; /* Command response 2 register */
41 uint cmdrsp3; /* Command response 3 register */
42 uint datport; /* Buffer data port register */
43 uint prsstat; /* Present state register */
44 uint proctl; /* Protocol control register */
45 uint sysctl; /* System Control Register */
46 uint irqstat; /* Interrupt status register */
47 uint irqstaten; /* Interrupt status enable register */
48 uint irqsigen; /* Interrupt signal enable register */
49 uint autoc12err; /* Auto CMD error status register */
50 uint hostcapblt; /* Host controller capabilities register */
51 uint wml; /* Watermark level register */
52 uint mixctrl; /* For USDHC */
53 char reserved1[4]; /* reserved */
54 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
56 uint adsaddr; /* ADMA system address register */
57 char reserved2[100]; /* reserved */
58 uint vendorspec; /* Vendor Specific register */
59 char reserved3[56]; /* reserved */
60 uint hostver; /* Host controller version register */
61 char reserved4[4]; /* reserved */
62 uint dmaerraddr; /* DMA error address register */
63 char reserved5[4]; /* reserved */
64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved6[4]; /* reserved */
66 uint hostcapblt2; /* Host controller capabilities register 2 */
67 char reserved7[8]; /* reserved */
68 uint tcr; /* Tuning control register */
69 char reserved8[28]; /* reserved */
70 uint sddirctl; /* SD direction control register */
71 char reserved9[712]; /* reserved */
72 uint scr; /* eSDHC control register */
75 /* Return the XFERTYP flags for a given command and data packet */
76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
81 xfertyp |= XFERTYP_DPSEL;
82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83 xfertyp |= XFERTYP_DMAEN;
85 if (data->blocks > 1) {
86 xfertyp |= XFERTYP_MSBSEL;
87 xfertyp |= XFERTYP_BCEN;
88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89 xfertyp |= XFERTYP_AC12EN;
93 if (data->flags & MMC_DATA_READ)
94 xfertyp |= XFERTYP_DTDSEL;
97 if (cmd->resp_type & MMC_RSP_CRC)
98 xfertyp |= XFERTYP_CCCEN;
99 if (cmd->resp_type & MMC_RSP_OPCODE)
100 xfertyp |= XFERTYP_CICEN;
101 if (cmd->resp_type & MMC_RSP_136)
102 xfertyp |= XFERTYP_RSPTYP_136;
103 else if (cmd->resp_type & MMC_RSP_BUSY)
104 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
105 else if (cmd->resp_type & MMC_RSP_PRESENT)
106 xfertyp |= XFERTYP_RSPTYP_48;
108 #if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || \
109 defined(CONFIG_SOC_LS102XA) || defined(CONFIG_LS2085A)
110 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
111 xfertyp |= XFERTYP_CMDTYP_ABORT;
113 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
116 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
118 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
121 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
123 struct fsl_esdhc_cfg *cfg = mmc->priv;
124 struct fsl_esdhc *regs = cfg->esdhc_base;
130 int wml = esdhc_read32(®s->wml);
132 if (data->flags & MMC_DATA_READ) {
133 wml &= WML_RD_WML_MASK;
134 blocks = data->blocks;
137 timeout = PIO_TIMEOUT;
138 size = data->blocksize;
140 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
144 while (!((prsstat = esdhc_read32(®s->prsstat)) &
145 PRSSTAT_BREN) && --timeout)
147 if (!(prsstat & PRSSTAT_BREN)) {
148 printf("%s: Data Read Failed in PIO Mode\n",
152 for (i = 0; i < wml && size; i++) {
153 databuf = in_le32(®s->datport);
154 memcpy(buffer, &databuf, sizeof(databuf));
162 wml = (wml & WML_WR_WML_MASK) >> 16;
163 blocks = data->blocks;
164 buffer = (char *)data->src; /* cast away 'const' */
166 timeout = PIO_TIMEOUT;
167 size = data->blocksize;
169 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
173 while (!((prsstat = esdhc_read32(®s->prsstat)) &
174 PRSSTAT_BWEN) && --timeout)
176 if (!(prsstat & PRSSTAT_BWEN)) {
177 printf("%s: Data Write Failed in PIO Mode\n",
181 for (i = 0; i < wml && size; i++) {
182 memcpy(&databuf, buffer, sizeof(databuf));
183 out_le32(®s->datport, databuf);
194 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
197 struct fsl_esdhc_cfg *cfg = mmc->priv;
198 struct fsl_esdhc *regs = cfg->esdhc_base;
199 #ifdef CONFIG_LS2085A
204 wml_value = data->blocksize / 4;
206 if (data->flags & MMC_DATA_READ) {
207 if (wml_value > WML_RD_WML_MAX)
208 wml_value = WML_RD_WML_MAX_VAL;
210 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
212 #ifdef CONFIG_LS2085A
213 addr = virt_to_phys((void *)(data->dest));
214 if (upper_32_bits(addr))
215 printf("Error found for upper 32 bits\n");
217 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
219 esdhc_write32(®s->dsaddr, (u32)data->dest);
223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
224 flush_dcache_range((ulong)data->src,
225 (ulong)data->src+data->blocks
228 if (wml_value > WML_WR_WML_MAX)
229 wml_value = WML_WR_WML_MAX_VAL;
230 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
231 printf("The SD card is locked. Can not write to a locked card.\n");
235 flush_dcache_range((unsigned long)data->src,
236 (unsigned long)data->src + data->blocks * data->blocksize);
237 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
239 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
240 #ifdef CONFIG_LS2085A
241 addr = virt_to_phys((void *)(data->src));
242 if (upper_32_bits(addr))
243 printf("Error found for upper 32 bits\n");
245 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
247 esdhc_write32(®s->dsaddr, (u32)data->src);
252 esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
254 /* Calculate the timeout period for data transactions */
256 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
257 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
258 * So, Number of SD Clock cycles for 0.25sec should be minimum
259 * (SD Clock/sec * 0.25 sec) SD Clock cycles
260 * = (mmc->clock * 1/4) SD Clock cycles
262 * => (2^(timeout+13)) >= mmc->clock * 1/4
263 * Taking log2 both the sides
264 * => timeout + 13 >= log2(mmc->clock/4)
265 * Rounding up to next power of 2
266 * => timeout + 13 = log2(mmc->clock/4) + 1
267 * => timeout + 13 = fls(mmc->clock/4)
269 timeout = fls(mmc->clock/4);
274 else if (timeout < 0)
277 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
278 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
282 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
285 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
290 static void check_and_invalidate_dcache_range
291 (struct mmc_cmd *cmd,
292 struct mmc_data *data) {
293 #ifdef CONFIG_LS2085A
296 unsigned start = (unsigned)data->dest ;
298 unsigned size = roundup(ARCH_DMA_MINALIGN,
299 data->blocks*data->blocksize);
300 unsigned end = start+size ;
301 #ifdef CONFIG_LS2085A
304 addr = virt_to_phys((void *)(data->dest));
305 if (upper_32_bits(addr))
306 printf("Error found for upper 32 bits\n");
308 start = lower_32_bits(addr);
310 invalidate_dcache_range(start, end);
314 * Sends a command out on the bus. Takes the mmc pointer,
315 * a command pointer, and an optional data pointer.
318 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
323 struct fsl_esdhc_cfg *cfg = mmc->priv;
324 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
327 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
328 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
331 esdhc_write32(®s->irqstat, -1);
335 start = get_timer_masked();
336 /* Wait for the bus to be idle */
337 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
338 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) {
339 if (get_timer(start) > CONFIG_SYS_HZ) {
340 printf("%s: Timeout waiting for bus idle\n", __func__);
345 start = get_timer_masked();
346 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) {
347 if (get_timer(start) > CONFIG_SYS_HZ)
351 /* Wait at least 8 SD clock cycles before the next command */
353 * Note: This is way more than 8 cycles, but 1ms seems to
354 * resolve timing issues with some cards
358 /* Set up for a data transfer if we have one */
360 err = esdhc_setup_data(mmc, data);
364 if (data->flags & MMC_DATA_READ)
365 check_and_invalidate_dcache_range(cmd, data);
368 /* Figure out the transfer arguments */
369 xfertyp = esdhc_xfertyp(cmd, data);
372 esdhc_write32(®s->irqsigen, 0);
374 /* Send the command */
375 esdhc_write32(®s->cmdarg, cmd->cmdarg);
376 #if defined(CONFIG_FSL_USDHC)
377 esdhc_write32(®s->mixctrl,
378 (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F)
379 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
380 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
382 esdhc_write32(®s->xfertyp, xfertyp);
386 esdhc_write32(®s->irqsigen, 0);
388 start = get_timer_masked();
389 /* Wait for the command to complete */
390 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) {
391 if (get_timer(start) > CONFIG_SYS_HZ) {
392 printf("%s: Timeout waiting for cmd completion\n", __func__);
397 if (data && (data->flags & MMC_DATA_READ))
398 check_and_invalidate_dcache_range(cmd, data);
400 irqstat = esdhc_read32(®s->irqstat);
402 if (irqstat & CMD_ERR) {
407 if (irqstat & IRQSTAT_CTOE) {
412 /* Switch voltage to 1.8V if CMD11 succeeded */
413 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
414 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
416 printf("Run CMD11 1.8V switch\n");
417 /* Sleep for 5 ms - max time for card to switch to 1.8V */
421 /* Workaround for ESDHC errata ENGcm03648 */
422 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
425 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
426 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
433 printf("Timeout waiting for DAT0 to go high!\n");
439 /* Copy the response to the response buffer */
440 if (cmd->resp_type & MMC_RSP_136) {
441 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
443 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
444 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
445 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
446 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
447 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
448 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
449 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
450 cmd->response[3] = (cmdrsp0 << 8);
452 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
454 /* Wait until all of the blocks are transferred */
456 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
457 esdhc_pio_read_write(mmc, data);
460 irqstat = esdhc_read32(®s->irqstat);
462 if (irqstat & IRQSTAT_DTOE) {
467 if (irqstat & DATA_ERR) {
471 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
474 * Need invalidate the dcache here again to avoid any
475 * cache-fill during the DMA operations such as the
476 * speculative pre-fetching etc.
478 if (data->flags & MMC_DATA_READ)
479 check_and_invalidate_dcache_range(cmd, data);
484 /* Reset CMD and DATA portions on error */
486 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
488 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
492 esdhc_write32(®s->sysctl,
493 esdhc_read32(®s->sysctl) |
495 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
499 /* If this was CMD11, then notify that power cycle is needed */
500 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
501 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
504 esdhc_write32(®s->irqstat, irqstat);
509 static void set_sysctl(struct mmc *mmc, uint clock)
512 struct fsl_esdhc_cfg *cfg = mmc->priv;
513 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
514 int sdhc_clk = cfg->sdhc_clk;
517 if (clock < mmc->cfg->f_min)
518 clock = mmc->cfg->f_min;
520 if (sdhc_clk / 16 > clock) {
521 for (pre_div = 2; pre_div < 256; pre_div *= 2)
522 if ((sdhc_clk / pre_div) <= (clock * 16))
527 for (div = 1; div <= 16; div++)
528 if ((sdhc_clk / (div * pre_div)) <= clock)
531 pre_div >>= mmc->ddr_mode ? 2 : 1;
534 clk = (pre_div << 8) | (div << 4);
536 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
538 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
542 clk = SYSCTL_PEREN | SYSCTL_CKEN;
544 esdhc_setbits32(®s->sysctl, clk);
547 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
548 static void esdhc_clock_control(struct mmc *mmc, bool enable)
550 struct fsl_esdhc_cfg *cfg = mmc->priv;
551 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
555 value = esdhc_read32(®s->sysctl);
558 value |= SYSCTL_CKEN;
560 value &= ~SYSCTL_CKEN;
562 esdhc_write32(®s->sysctl, value);
565 value = PRSSTAT_SDSTB;
566 while (!(esdhc_read32(®s->prsstat) & value)) {
568 printf("fsl_esdhc: Internal clock never stabilised.\n");
577 static void esdhc_set_ios(struct mmc *mmc)
579 struct fsl_esdhc_cfg *cfg = mmc->priv;
580 struct fsl_esdhc *regs = cfg->esdhc_base;
582 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
583 /* Select to use peripheral clock */
584 esdhc_clock_control(mmc, false);
585 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
586 esdhc_clock_control(mmc, true);
588 /* Set the clock speed */
589 set_sysctl(mmc, mmc->clock);
591 /* Set the bus width */
592 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
594 if (mmc->bus_width == 4)
595 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
596 else if (mmc->bus_width == 8)
597 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
601 static int esdhc_init(struct mmc *mmc)
603 struct fsl_esdhc_cfg *cfg = mmc->priv;
604 struct fsl_esdhc *regs = cfg->esdhc_base;
607 /* Reset the entire host controller */
608 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
610 /* Wait until the controller is available */
611 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
615 /* Enable cache snooping */
616 esdhc_write32(®s->scr, 0x00000040);
619 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
621 /* Set the initial clock speed */
622 mmc_set_clock(mmc, 400000);
624 /* Disable the BRR and BWR bits in IRQSTAT */
625 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
627 /* Put the PROCTL reg back to the default */
628 esdhc_write32(®s->proctl, PROCTL_INIT);
630 /* Set timout to the maximum value */
631 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
633 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
634 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
640 static int esdhc_getcd(struct mmc *mmc)
642 struct fsl_esdhc_cfg *cfg = mmc->priv;
643 struct fsl_esdhc *regs = cfg->esdhc_base;
646 #ifdef CONFIG_ESDHC_DETECT_QUIRK
647 if (CONFIG_ESDHC_DETECT_QUIRK)
650 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
656 static void esdhc_reset(struct fsl_esdhc *regs)
658 unsigned long timeout = 100; /* wait max 100 ms */
660 /* reset the controller */
661 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
663 /* hardware clears the bit when it is done */
664 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
667 printf("MMC/SD: Reset never completed.\n");
670 static const struct mmc_ops esdhc_ops = {
671 .send_cmd = esdhc_send_cmd,
672 .set_ios = esdhc_set_ios,
674 .getcd = esdhc_getcd,
677 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
679 struct fsl_esdhc *regs;
681 u32 caps, voltage_caps;
686 regs = (struct fsl_esdhc *)cfg->esdhc_base;
688 /* First reset the eSDHC controller */
691 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
692 | SYSCTL_IPGEN | SYSCTL_CKEN);
694 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
695 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
698 caps = esdhc_read32(®s->hostcapblt);
700 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
701 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
702 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
705 /* T4240 host controller capabilities register should have VS33 bit */
706 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
707 caps = caps | ESDHC_HOSTCAPBLT_VS33;
710 if (caps & ESDHC_HOSTCAPBLT_VS18)
711 voltage_caps |= MMC_VDD_165_195;
712 if (caps & ESDHC_HOSTCAPBLT_VS30)
713 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
714 if (caps & ESDHC_HOSTCAPBLT_VS33)
715 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
717 cfg->cfg.name = "FSL_SDHC";
718 cfg->cfg.ops = &esdhc_ops;
719 #ifdef CONFIG_SYS_SD_VOLTAGE
720 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
722 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
724 if ((cfg->cfg.voltages & voltage_caps) == 0) {
725 printf("voltage not supported by controller\n");
729 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
730 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
731 cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
734 if (cfg->max_bus_width > 0) {
735 if (cfg->max_bus_width < 8)
736 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
737 if (cfg->max_bus_width < 4)
738 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
741 if (caps & ESDHC_HOSTCAPBLT_HSS)
742 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
744 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
745 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
746 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
749 cfg->cfg.f_min = 400000;
750 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
752 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
754 mmc = mmc_create(&cfg->cfg, cfg);
761 int fsl_esdhc_mmc_init(bd_t *bis)
763 struct fsl_esdhc_cfg *cfg;
765 cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL);
768 cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR;
769 cfg->sdhc_clk = gd->arch.sdhc_clk;
770 return fsl_esdhc_initialize(bis, cfg);
773 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
774 void mmc_adapter_card_type_ident(void)
779 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
780 gd->arch.sdhc_adapter = card_id;
783 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
785 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
787 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
788 value = QIXIS_READ(brdcfg[5]);
789 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
790 QIXIS_WRITE(brdcfg[5], value);
792 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
794 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
796 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
798 case QIXIS_ESDHC_NO_ADAPTER:
806 #ifdef CONFIG_OF_LIBFDT
807 void fdt_fixup_esdhc(void *blob, bd_t *bd)
809 const char *compat = "fsl,esdhc";
811 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
812 if (!hwconfig("esdhc")) {
813 do_fixup_by_compat(blob, compat, "status", "disabled",
819 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
820 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
821 gd->arch.sdhc_clk, 1);
823 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
824 gd->arch.sdhc_clk, 1);
826 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
827 do_fixup_by_compat_u32(blob, compat, "adapter-type",
828 (u32)(gd->arch.sdhc_adapter), 1);
830 do_fixup_by_compat(blob, compat, "status", "okay",