drivers/mmc/host/atmel-mci.c

   1 /*
   2  * Atmel MultiMedia Card Interface driver
   3  *
   4  * Copyright (C) 2004-2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/ioport.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/types.h>
  32
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/sdio.h>
  35
  36 #include <linux/atmel-mci.h>
  37 #include <linux/atmel_pdc.h>
  38 #include <linux/pm.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/pinctrl/consumer.h>
  41
  42 #include <asm/cacheflush.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45
  46 /*
  47  * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
  48  * Registers and bitfields marked with [2] are only available in MCI2
  49  */
  50
  51 /* MCI Register Definitions */
  52 #define ATMCI_CR                        0x0000  /* Control */
  53 #define         ATMCI_CR_MCIEN                  BIT(0)          /* MCI Enable */
  54 #define         ATMCI_CR_MCIDIS                 BIT(1)          /* MCI Disable */
  55 #define         ATMCI_CR_PWSEN                  BIT(2)          /* Power Save Enable */
  56 #define         ATMCI_CR_PWSDIS                 BIT(3)          /* Power Save Disable */
  57 #define         ATMCI_CR_SWRST                  BIT(7)          /* Software Reset */
  58 #define ATMCI_MR                        0x0004  /* Mode */
  59 #define         ATMCI_MR_CLKDIV(x)              ((x) <<  0)     /* Clock Divider */
  60 #define         ATMCI_MR_PWSDIV(x)              ((x) <<  8)     /* Power Saving Divider */
  61 #define         ATMCI_MR_RDPROOF                BIT(11)         /* Read Proof */
  62 #define         ATMCI_MR_WRPROOF                BIT(12)         /* Write Proof */
  63 #define         ATMCI_MR_PDCFBYTE               BIT(13)         /* Force Byte Transfer */
  64 #define         ATMCI_MR_PDCPADV                BIT(14)         /* Padding Value */
  65 #define         ATMCI_MR_PDCMODE                BIT(15)         /* PDC-oriented Mode */
  66 #define         ATMCI_MR_CLKODD(x)              ((x) << 16)     /* LSB of Clock Divider */
  67 #define ATMCI_DTOR                      0x0008  /* Data Timeout */
  68 #define         ATMCI_DTOCYC(x)                 ((x) <<  0)     /* Data Timeout Cycles */
  69 #define         ATMCI_DTOMUL(x)                 ((x) <<  4)     /* Data Timeout Multiplier */
  70 #define ATMCI_SDCR                      0x000c  /* SD Card / SDIO */
  71 #define         ATMCI_SDCSEL_SLOT_A             (0 <<  0)       /* Select SD slot A */
  72 #define         ATMCI_SDCSEL_SLOT_B             (1 <<  0)       /* Select SD slot A */
  73 #define         ATMCI_SDCSEL_MASK               (3 <<  0)
  74 #define         ATMCI_SDCBUS_1BIT               (0 <<  6)       /* 1-bit data bus */
  75 #define         ATMCI_SDCBUS_4BIT               (2 <<  6)       /* 4-bit data bus */
  76 #define         ATMCI_SDCBUS_8BIT               (3 <<  6)       /* 8-bit data bus[2] */
  77 #define         ATMCI_SDCBUS_MASK               (3 <<  6)
  78 #define ATMCI_ARGR                      0x0010  /* Command Argument */
  79 #define ATMCI_CMDR                      0x0014  /* Command */
  80 #define         ATMCI_CMDR_CMDNB(x)             ((x) <<  0)     /* Command Opcode */
  81 #define         ATMCI_CMDR_RSPTYP_NONE          (0 <<  6)       /* No response */
  82 #define         ATMCI_CMDR_RSPTYP_48BIT         (1 <<  6)       /* 48-bit response */
  83 #define         ATMCI_CMDR_RSPTYP_136BIT        (2 <<  6)       /* 136-bit response */
  84 #define         ATMCI_CMDR_SPCMD_INIT           (1 <<  8)       /* Initialization command */
  85 #define         ATMCI_CMDR_SPCMD_SYNC           (2 <<  8)       /* Synchronized command */
  86 #define         ATMCI_CMDR_SPCMD_INT            (4 <<  8)       /* Interrupt command */
  87 #define         ATMCI_CMDR_SPCMD_INTRESP        (5 <<  8)       /* Interrupt response */
  88 #define         ATMCI_CMDR_OPDCMD               (1 << 11)       /* Open Drain */
  89 #define         ATMCI_CMDR_MAXLAT_5CYC          (0 << 12)       /* Max latency 5 cycles */
  90 #define         ATMCI_CMDR_MAXLAT_64CYC         (1 << 12)       /* Max latency 64 cycles */
  91 #define         ATMCI_CMDR_START_XFER           (1 << 16)       /* Start data transfer */
  92 #define         ATMCI_CMDR_STOP_XFER            (2 << 16)       /* Stop data transfer */
  93 #define         ATMCI_CMDR_TRDIR_WRITE          (0 << 18)       /* Write data */
  94 #define         ATMCI_CMDR_TRDIR_READ           (1 << 18)       /* Read data */
  95 #define         ATMCI_CMDR_BLOCK                (0 << 19)       /* Single-block transfer */
  96 #define         ATMCI_CMDR_MULTI_BLOCK          (1 << 19)       /* Multi-block transfer */
  97 #define         ATMCI_CMDR_STREAM               (2 << 19)       /* MMC Stream transfer */
  98 #define         ATMCI_CMDR_SDIO_BYTE            (4 << 19)       /* SDIO Byte transfer */
  99 #define         ATMCI_CMDR_SDIO_BLOCK           (5 << 19)       /* SDIO Block transfer */
 100 #define         ATMCI_CMDR_SDIO_SUSPEND         (1 << 24)       /* SDIO Suspend Command */
 101 #define         ATMCI_CMDR_SDIO_RESUME          (2 << 24)       /* SDIO Resume Command */
 102 #define ATMCI_BLKR                      0x0018  /* Block */
 103 #define         ATMCI_BCNT(x)                   ((x) <<  0)     /* Data Block Count */
 104 #define         ATMCI_BLKLEN(x)                 ((x) << 16)     /* Data Block Length */
 105 #define ATMCI_CSTOR                     0x001c  /* Completion Signal Timeout[2] */
 106 #define         ATMCI_CSTOCYC(x)                ((x) <<  0)     /* CST cycles */
 107 #define         ATMCI_CSTOMUL(x)                ((x) <<  4)     /* CST multiplier */
 108 #define ATMCI_RSPR                      0x0020  /* Response 0 */
 109 #define ATMCI_RSPR1                     0x0024  /* Response 1 */
 110 #define ATMCI_RSPR2                     0x0028  /* Response 2 */
 111 #define ATMCI_RSPR3                     0x002c  /* Response 3 */
 112 #define ATMCI_RDR                       0x0030  /* Receive Data */
 113 #define ATMCI_TDR                       0x0034  /* Transmit Data */
 114 #define ATMCI_SR                        0x0040  /* Status */
 115 #define ATMCI_IER                       0x0044  /* Interrupt Enable */
 116 #define ATMCI_IDR                       0x0048  /* Interrupt Disable */
 117 #define ATMCI_IMR                       0x004c  /* Interrupt Mask */
 118 #define         ATMCI_CMDRDY                    BIT(0)          /* Command Ready */
 119 #define         ATMCI_RXRDY                     BIT(1)          /* Receiver Ready */
 120 #define         ATMCI_TXRDY                     BIT(2)          /* Transmitter Ready */
 121 #define         ATMCI_BLKE                      BIT(3)          /* Data Block Ended */
 122 #define         ATMCI_DTIP                      BIT(4)          /* Data Transfer In Progress */
 123 #define         ATMCI_NOTBUSY                   BIT(5)          /* Data Not Busy */
 124 #define         ATMCI_ENDRX                     BIT(6)          /* End of RX Buffer */
 125 #define         ATMCI_ENDTX                     BIT(7)          /* End of TX Buffer */
 126 #define         ATMCI_SDIOIRQA                  BIT(8)          /* SDIO IRQ in slot A */
 127 #define         ATMCI_SDIOIRQB                  BIT(9)          /* SDIO IRQ in slot B */
 128 #define         ATMCI_SDIOWAIT                  BIT(12)         /* SDIO Read Wait Operation Status */
 129 #define         ATMCI_CSRCV                     BIT(13)         /* CE-ATA Completion Signal Received */
 130 #define         ATMCI_RXBUFF                    BIT(14)         /* RX Buffer Full */
 131 #define         ATMCI_TXBUFE                    BIT(15)         /* TX Buffer Empty */
 132 #define         ATMCI_RINDE                     BIT(16)         /* Response Index Error */
 133 #define         ATMCI_RDIRE                     BIT(17)         /* Response Direction Error */
 134 #define         ATMCI_RCRCE                     BIT(18)         /* Response CRC Error */
 135 #define         ATMCI_RENDE                     BIT(19)         /* Response End Bit Error */
 136 #define         ATMCI_RTOE                      BIT(20)         /* Response Time-Out Error */
 137 #define         ATMCI_DCRCE                     BIT(21)         /* Data CRC Error */
 138 #define         ATMCI_DTOE                      BIT(22)         /* Data Time-Out Error */
 139 #define         ATMCI_CSTOE                     BIT(23)         /* Completion Signal Time-out Error */
 140 #define         ATMCI_BLKOVRE                   BIT(24)         /* DMA Block Overrun Error */
 141 #define         ATMCI_DMADONE                   BIT(25)         /* DMA Transfer Done */
 142 #define         ATMCI_FIFOEMPTY                 BIT(26)         /* FIFO Empty Flag */
 143 #define         ATMCI_XFRDONE                   BIT(27)         /* Transfer Done Flag */
 144 #define         ATMCI_ACKRCV                    BIT(28)         /* Boot Operation Acknowledge Received */
 145 #define         ATMCI_ACKRCVE                   BIT(29)         /* Boot Operation Acknowledge Error */
 146 #define         ATMCI_OVRE                      BIT(30)         /* RX Overrun Error */
 147 #define         ATMCI_UNRE                      BIT(31)         /* TX Underrun Error */
 148 #define ATMCI_DMA                       0x0050  /* DMA Configuration[2] */
 149 #define         ATMCI_DMA_OFFSET(x)             ((x) <<  0)     /* DMA Write Buffer Offset */
 150 #define         ATMCI_DMA_CHKSIZE(x)            ((x) <<  4)     /* DMA Channel Read and Write Chunk Size */
 151 #define         ATMCI_DMAEN                     BIT(8)  /* DMA Hardware Handshaking Enable */
 152 #define ATMCI_CFG                       0x0054  /* Configuration[2] */
 153 #define         ATMCI_CFG_FIFOMODE_1DATA        BIT(0)          /* MCI Internal FIFO control mode */
 154 #define         ATMCI_CFG_FERRCTRL_COR          BIT(4)          /* Flow Error flag reset control mode */
 155 #define         ATMCI_CFG_HSMODE                BIT(8)          /* High Speed Mode */
 156 #define         ATMCI_CFG_LSYNC                 BIT(12)         /* Synchronize on the last block */
 157 #define ATMCI_WPMR                      0x00e4  /* Write Protection Mode[2] */
 158 #define         ATMCI_WP_EN                     BIT(0)          /* WP Enable */
 159 #define         ATMCI_WP_KEY                    (0x4d4349 << 8) /* WP Key */
 160 #define ATMCI_WPSR                      0x00e8  /* Write Protection Status[2] */
 161 #define         ATMCI_GET_WP_VS(x)              ((x) & 0x0f)
 162 #define         ATMCI_GET_WP_VSRC(x)            (((x) >> 8) & 0xffff)
 163 #define ATMCI_VERSION                   0x00FC  /* Version */
 164 #define ATMCI_FIFO_APERTURE             0x0200  /* FIFO Aperture[2] */
 165
 166 /* This is not including the FIFO Aperture on MCI2 */
 167 #define ATMCI_REGS_SIZE         0x100
 168
 169 /* Register access macros */
 170 #define atmci_readl(port, reg)                          \
 171         __raw_readl((port)->regs + reg)
 172 #define atmci_writel(port, reg, value)                  \
 173         __raw_writel((value), (port)->regs + reg)
 174
 175 /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
 176 #ifdef CONFIG_AVR32
 177 #       define ATMCI_PDC_CONNECTED      0
 178 #else
 179 #       define ATMCI_PDC_CONNECTED      1
 180 #endif
 181
 182 #define AUTOSUSPEND_DELAY       50
 183
 184 #define ATMCI_DATA_ERROR_FLAGS  (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
 185 #define ATMCI_DMA_THRESHOLD     16
 186
 187 enum {
 188         EVENT_CMD_RDY = 0,
 189         EVENT_XFER_COMPLETE,
 190         EVENT_NOTBUSY,
 191         EVENT_DATA_ERROR,
 192 };
 193
 194 enum atmel_mci_state {
 195         STATE_IDLE = 0,
 196         STATE_SENDING_CMD,
 197         STATE_DATA_XFER,
 198         STATE_WAITING_NOTBUSY,
 199         STATE_SENDING_STOP,
 200         STATE_END_REQUEST,
 201 };
 202
 203 enum atmci_xfer_dir {
 204         XFER_RECEIVE = 0,
 205         XFER_TRANSMIT,
 206 };
 207
 208 enum atmci_pdc_buf {
 209         PDC_FIRST_BUF = 0,
 210         PDC_SECOND_BUF,
 211 };
 212
 213 struct atmel_mci_caps {
 214         bool    has_dma_conf_reg;
 215         bool    has_pdc;
 216         bool    has_cfg_reg;
 217         bool    has_cstor_reg;
 218         bool    has_highspeed;
 219         bool    has_rwproof;
 220         bool    has_odd_clk_div;
 221         bool    has_bad_data_ordering;
 222         bool    need_reset_after_xfer;
 223         bool    need_blksz_mul_4;
 224         bool    need_notbusy_for_read_ops;
 225 };
 226
 227 struct atmel_mci_dma {
 228         struct dma_chan                 *chan;
 229         struct dma_async_tx_descriptor  *data_desc;
 230 };
 231
 232 /**
 233  * struct atmel_mci - MMC controller state shared between all slots
 234  * @lock: Spinlock protecting the queue and associated data.
 235  * @regs: Pointer to MMIO registers.
 236  * @sg: Scatterlist entry currently being processed by PIO or PDC code.
 237  * @pio_offset: Offset into the current scatterlist entry.
 238  * @buffer: Buffer used if we don't have the r/w proof capability. We
 239  *      don't have the time to switch pdc buffers so we have to use only
 240  *      one buffer for the full transaction.
 241  * @buf_size: size of the buffer.
 242  * @phys_buf_addr: buffer address needed for pdc.
 243  * @cur_slot: The slot which is currently using the controller.
 244  * @mrq: The request currently being processed on @cur_slot,
 245  *      or NULL if the controller is idle.
 246  * @cmd: The command currently being sent to the card, or NULL.
 247  * @data: The data currently being transferred, or NULL if no data
 248  *      transfer is in progress.
 249  * @data_size: just data->blocks * data->blksz.
 250  * @dma: DMA client state.
 251  * @data_chan: DMA channel being used for the current data transfer.
 252  * @cmd_status: Snapshot of SR taken upon completion of the current
 253  *      command. Only valid when EVENT_CMD_COMPLETE is pending.
 254  * @data_status: Snapshot of SR taken upon completion of the current
 255  *      data transfer. Only valid when EVENT_DATA_COMPLETE or
 256  *      EVENT_DATA_ERROR is pending.
 257  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 258  *      to be sent.
 259  * @tasklet: Tasklet running the request state machine.
 260  * @pending_events: Bitmask of events flagged by the interrupt handler
 261  *      to be processed by the tasklet.
 262  * @completed_events: Bitmask of events which the state machine has
 263  *      processed.
 264  * @state: Tasklet state.
 265  * @queue: List of slots waiting for access to the controller.
 266  * @need_clock_update: Update the clock rate before the next request.
 267  * @need_reset: Reset controller before next request.
 268  * @timer: Timer to balance the data timeout error flag which cannot rise.
 269  * @mode_reg: Value of the MR register.
 270  * @cfg_reg: Value of the CFG register.
 271  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 272  *      rate and timeout calculations.
 273  * @mapbase: Physical address of the MMIO registers.
 274  * @mck: The peripheral bus clock hooked up to the MMC controller.
 275  * @pdev: Platform device associated with the MMC controller.
 276  * @slot: Slots sharing this MMC controller.
 277  * @caps: MCI capabilities depending on MCI version.
 278  * @prepare_data: function to setup MCI before data transfer which
 279  * depends on MCI capabilities.
 280  * @submit_data: function to start data transfer which depends on MCI
 281  * capabilities.
 282  * @stop_transfer: function to stop data transfer which depends on MCI
 283  * capabilities.
 284  *
 285  * Locking
 286  * =======
 287  *
 288  * @lock is a softirq-safe spinlock protecting @queue as well as
 289  * @cur_slot, @mrq and @state. These must always be updated
 290  * at the same time while holding @lock.
 291  *
 292  * @lock also protects mode_reg and need_clock_update since these are
 293  * used to synchronize mode register updates with the queue
 294  * processing.
 295  *
 296  * The @mrq field of struct atmel_mci_slot is also protected by @lock,
 297  * and must always be written at the same time as the slot is added to
 298  * @queue.
 299  *
 300  * @pending_events and @completed_events are accessed using atomic bit
 301  * operations, so they don't need any locking.
 302  *
 303  * None of the fields touched by the interrupt handler need any
 304  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 305  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 306  * interrupts must be disabled and @data_status updated with a
 307  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 308  * CMDRDY interrupt must be disabled and @cmd_status updated with a
 309  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 310  * bytes_xfered field of @data must be written. This is ensured by
 311  * using barriers.
 312  */
 313 struct atmel_mci {
 314         spinlock_t              lock;
 315         void __iomem            *regs;
 316
 317         struct scatterlist      *sg;
 318         unsigned int            sg_len;
 319         unsigned int            pio_offset;
 320         unsigned int            *buffer;
 321         unsigned int            buf_size;
 322         dma_addr_t              buf_phys_addr;
 323
 324         struct atmel_mci_slot   *cur_slot;
 325         struct mmc_request      *mrq;
 326         struct mmc_command      *cmd;
 327         struct mmc_data         *data;
 328         unsigned int            data_size;
 329
 330         struct atmel_mci_dma    dma;
 331         struct dma_chan         *data_chan;
 332         struct dma_slave_config dma_conf;
 333
 334         u32                     cmd_status;
 335         u32                     data_status;
 336         u32                     stop_cmdr;
 337
 338         struct tasklet_struct   tasklet;
 339         unsigned long           pending_events;
 340         unsigned long           completed_events;
 341         enum atmel_mci_state    state;
 342         struct list_head        queue;
 343
 344         bool                    need_clock_update;
 345         bool                    need_reset;
 346         struct timer_list       timer;
 347         u32                     mode_reg;
 348         u32                     cfg_reg;
 349         unsigned long           bus_hz;
 350         unsigned long           mapbase;
 351         struct clk              *mck;
 352         struct platform_device  *pdev;
 353
 354         struct atmel_mci_slot   *slot[ATMCI_MAX_NR_SLOTS];
 355
 356         struct atmel_mci_caps   caps;
 357
 358         u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
 359         void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
 360         void (*stop_transfer)(struct atmel_mci *host);
 361 };
 362
 363 /**
 364  * struct atmel_mci_slot - MMC slot state
 365  * @mmc: The mmc_host representing this slot.
 366  * @host: The MMC controller this slot is using.
 367  * @sdc_reg: Value of SDCR to be written before using this slot.
 368  * @sdio_irq: SDIO irq mask for this slot.
 369  * @mrq: mmc_request currently being processed or waiting to be
 370  *      processed, or NULL when the slot is idle.
 371  * @queue_node: List node for placing this node in the @queue list of
 372  *      &struct atmel_mci.
 373  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 374  * @flags: Random state bits associated with the slot.
 375  * @detect_pin: GPIO pin used for card detection, or negative if not
 376  *      available.
 377  * @wp_pin: GPIO pin used for card write protect sending, or negative
 378  *      if not available.
 379  * @detect_is_active_high: The state of the detect pin when it is active.
 380  * @detect_timer: Timer used for debouncing @detect_pin interrupts.
 381  */
 382 struct atmel_mci_slot {
 383         struct mmc_host         *mmc;
 384         struct atmel_mci        *host;
 385
 386         u32                     sdc_reg;
 387         u32                     sdio_irq;
 388
 389         struct mmc_request      *mrq;
 390         struct list_head        queue_node;
 391
 392         unsigned int            clock;
 393         unsigned long           flags;
 394 #define ATMCI_CARD_PRESENT      0
 395 #define ATMCI_CARD_NEED_INIT    1
 396 #define ATMCI_SHUTDOWN          2
 397
 398         int                     detect_pin;
 399         int                     wp_pin;
 400         bool                    detect_is_active_high;
 401
 402         struct timer_list       detect_timer;
 403 };
 404
 405 #define atmci_test_and_clear_pending(host, event)               \
 406         test_and_clear_bit(event, &host->pending_events)
 407 #define atmci_set_completed(host, event)                        \
 408         set_bit(event, &host->completed_events)
 409 #define atmci_set_pending(host, event)                          \
 410         set_bit(event, &host->pending_events)
 411
 412 /*
 413  * The debugfs stuff below is mostly optimized away when
 414  * CONFIG_DEBUG_FS is not set.
 415  */
 416 static int atmci_req_show(struct seq_file *s, void *v)
 417 {
 418         struct atmel_mci_slot   *slot = s->private;
 419         struct mmc_request      *mrq;
 420         struct mmc_command      *cmd;
 421         struct mmc_command      *stop;
 422         struct mmc_data         *data;
 423
 424         /* Make sure we get a consistent snapshot */
 425         spin_lock_bh(&slot->host->lock);
 426         mrq = slot->mrq;
 427
 428         if (mrq) {
 429                 cmd = mrq->cmd;
 430                 data = mrq->data;
 431                 stop = mrq->stop;
 432
 433                 if (cmd)
 434                         seq_printf(s,
 435                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 436                                 cmd->opcode, cmd->arg, cmd->flags,
 437                                 cmd->resp[0], cmd->resp[1], cmd->resp[2],
 438                                 cmd->resp[3], cmd->error);
 439                 if (data)
 440                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 441                                 data->bytes_xfered, data->blocks,
 442                                 data->blksz, data->flags, data->error);
 443                 if (stop)
 444                         seq_printf(s,
 445                                 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 446                                 stop->opcode, stop->arg, stop->flags,
 447                                 stop->resp[0], stop->resp[1], stop->resp[2],
 448                                 stop->resp[3], stop->error);
 449         }
 450
 451         spin_unlock_bh(&slot->host->lock);
 452
 453         return 0;
 454 }
 455
 456 static int atmci_req_open(struct inode *inode, struct file *file)
 457 {
 458         return single_open(file, atmci_req_show, inode->i_private);
 459 }
 460
 461 static const struct file_operations atmci_req_fops = {
 462         .owner          = THIS_MODULE,
 463         .open           = atmci_req_open,
 464         .read           = seq_read,
 465         .llseek         = seq_lseek,
 466         .release        = single_release,
 467 };
 468
 469 static void atmci_show_status_reg(struct seq_file *s,
 470                 const char *regname, u32 value)
 471 {
 472         static const char       *sr_bit[] = {
 473                 [0]     = "CMDRDY",
 474                 [1]     = "RXRDY",
 475                 [2]     = "TXRDY",
 476                 [3]     = "BLKE",
 477                 [4]     = "DTIP",
 478                 [5]     = "NOTBUSY",
 479                 [6]     = "ENDRX",
 480                 [7]     = "ENDTX",
 481                 [8]     = "SDIOIRQA",
 482                 [9]     = "SDIOIRQB",
 483                 [12]    = "SDIOWAIT",
 484                 [14]    = "RXBUFF",
 485                 [15]    = "TXBUFE",
 486                 [16]    = "RINDE",
 487                 [17]    = "RDIRE",
 488                 [18]    = "RCRCE",
 489                 [19]    = "RENDE",
 490                 [20]    = "RTOE",
 491                 [21]    = "DCRCE",
 492                 [22]    = "DTOE",
 493                 [23]    = "CSTOE",
 494                 [24]    = "BLKOVRE",
 495                 [25]    = "DMADONE",
 496                 [26]    = "FIFOEMPTY",
 497                 [27]    = "XFRDONE",
 498                 [30]    = "OVRE",
 499                 [31]    = "UNRE",
 500         };
 501         unsigned int            i;
 502
 503         seq_printf(s, "%s:\t0x%08x", regname, value);
 504         for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
 505                 if (value & (1 << i)) {
 506                         if (sr_bit[i])
 507                                 seq_printf(s, " %s", sr_bit[i]);
 508                         else
 509                                 seq_puts(s, " UNKNOWN");
 510                 }
 511         }
 512         seq_putc(s, '\n');
 513 }
 514
 515 static int atmci_regs_show(struct seq_file *s, void *v)
 516 {
 517         struct atmel_mci        *host = s->private;
 518         u32                     *buf;
 519         int                     ret = 0;
 520
 521
 522         buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
 523         if (!buf)
 524                 return -ENOMEM;
 525
 526         pm_runtime_get_sync(&host->pdev->dev);
 527
 528         /*
 529          * Grab a more or less consistent snapshot. Note that we're
 530          * not disabling interrupts, so IMR and SR may not be
 531          * consistent.
 532          */
 533         spin_lock_bh(&host->lock);
 534         memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
 535         spin_unlock_bh(&host->lock);
 536
 537         pm_runtime_mark_last_busy(&host->pdev->dev);
 538         pm_runtime_put_autosuspend(&host->pdev->dev);
 539
 540         seq_printf(s, "MR:\t0x%08x%s%s ",
 541                         buf[ATMCI_MR / 4],
 542                         buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
 543                         buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
 544         if (host->caps.has_odd_clk_div)
 545                 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
 546                                 ((buf[ATMCI_MR / 4] & 0xff) << 1)
 547                                 | ((buf[ATMCI_MR / 4] >> 16) & 1));
 548         else
 549                 seq_printf(s, "CLKDIV=%u\n",
 550                                 (buf[ATMCI_MR / 4] & 0xff));
 551         seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
 552         seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
 553         seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
 554         seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
 555                         buf[ATMCI_BLKR / 4],
 556                         buf[ATMCI_BLKR / 4] & 0xffff,
 557                         (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
 558         if (host->caps.has_cstor_reg)
 559                 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
 560
 561         /* Don't read RSPR and RDR; it will consume the data there */
 562
 563         atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
 564         atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
 565
 566         if (host->caps.has_dma_conf_reg) {
 567                 u32 val;
 568
 569                 val = buf[ATMCI_DMA / 4];
 570                 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
 571                                 val, val & 3,
 572                                 ((val >> 4) & 3) ?
 573                                         1 << (((val >> 4) & 3) + 1) : 1,
 574                                 val & ATMCI_DMAEN ? " DMAEN" : "");
 575         }
 576         if (host->caps.has_cfg_reg) {
 577                 u32 val;
 578
 579                 val = buf[ATMCI_CFG / 4];
 580                 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
 581                                 val,
 582                                 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
 583                                 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
 584                                 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
 585                                 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
 586         }
 587
 588         kfree(buf);
 589
 590         return ret;
 591 }
 592
 593 static int atmci_regs_open(struct inode *inode, struct file *file)
 594 {
 595         return single_open(file, atmci_regs_show, inode->i_private);
 596 }
 597
 598 static const struct file_operations atmci_regs_fops = {
 599         .owner          = THIS_MODULE,
 600         .open           = atmci_regs_open,
 601         .read           = seq_read,
 602         .llseek         = seq_lseek,
 603         .release        = single_release,
 604 };
 605
 606 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
 607 {
 608         struct mmc_host         *mmc = slot->mmc;
 609         struct atmel_mci        *host = slot->host;
 610         struct dentry           *root;
 611         struct dentry           *node;
 612
 613         root = mmc->debugfs_root;
 614         if (!root)
 615                 return;
 616
 617         node = debugfs_create_file("regs", S_IRUSR, root, host,
 618                         &atmci_regs_fops);
 619         if (IS_ERR(node))
 620                 return;
 621         if (!node)
 622                 goto err;
 623
 624         node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
 625         if (!node)
 626                 goto err;
 627
 628         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 629         if (!node)
 630                 goto err;
 631
 632         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 633                                      (u32 *)&host->pending_events);
 634         if (!node)
 635                 goto err;
 636
 637         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 638                                      (u32 *)&host->completed_events);
 639         if (!node)
 640                 goto err;
 641
 642         return;
 643
 644 err:
 645         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 646 }
 647
 648 #if defined(CONFIG_OF)
 649 static const struct of_device_id atmci_dt_ids[] = {
 650         { .compatible = "atmel,hsmci" },
 651         { /* sentinel */ }
 652 };
 653
 654 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
 655
 656 static struct mci_platform_data*
 657 atmci_of_init(struct platform_device *pdev)
 658 {
 659         struct device_node *np = pdev->dev.of_node;
 660         struct device_node *cnp;
 661         struct mci_platform_data *pdata;
 662         u32 slot_id;
 663
 664         if (!np) {
 665                 dev_err(&pdev->dev, "device node not found\n");
 666                 return ERR_PTR(-EINVAL);
 667         }
 668
 669         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 670         if (!pdata) {
 671                 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
 672                 return ERR_PTR(-ENOMEM);
 673         }
 674
 675         for_each_child_of_node(np, cnp) {
 676                 if (of_property_read_u32(cnp, "reg", &slot_id)) {
 677                         dev_warn(&pdev->dev, "reg property is missing for %s\n",
 678                                  cnp->full_name);
 679                         continue;
 680                 }
 681
 682                 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
 683                         dev_warn(&pdev->dev, "can't have more than %d slots\n",
 684                                  ATMCI_MAX_NR_SLOTS);
 685                         break;
 686                 }
 687
 688                 if (of_property_read_u32(cnp, "bus-width",
 689                                          &pdata->slot[slot_id].bus_width))
 690                         pdata->slot[slot_id].bus_width = 1;
 691
 692                 pdata->slot[slot_id].detect_pin =
 693                         of_get_named_gpio(cnp, "cd-gpios", 0);
 694
 695                 pdata->slot[slot_id].detect_is_active_high =
 696                         of_property_read_bool(cnp, "cd-inverted");
 697
 698                 pdata->slot[slot_id].non_removable =
 699                         of_property_read_bool(cnp, "non-removable");
 700
 701                 pdata->slot[slot_id].wp_pin =
 702                         of_get_named_gpio(cnp, "wp-gpios", 0);
 703         }
 704
 705         return pdata;
 706 }
 707 #else /* CONFIG_OF */
 708 static inline struct mci_platform_data*
 709 atmci_of_init(struct platform_device *dev)
 710 {
 711         return ERR_PTR(-EINVAL);
 712 }
 713 #endif
 714
 715 static inline unsigned int atmci_get_version(struct atmel_mci *host)
 716 {
 717         return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
 718 }
 719
 720 /*
 721  * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
 722  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 723  * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
 724  * 8 -> 3, 16 -> 4.
 725  *
 726  * This can be done by finding most significant bit set.
 727  */
 728 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
 729                                                  unsigned int maxburst)
 730 {
 731         unsigned int version = atmci_get_version(host);
 732         unsigned int offset = 2;
 733
 734         if (version >= 0x600)
 735                 offset = 1;
 736
 737         if (maxburst > 1)
 738                 return fls(maxburst) - offset;
 739         else
 740                 return 0;
 741 }
 742
 743 static void atmci_timeout_timer(unsigned long data)
 744 {
 745         struct atmel_mci *host;
 746
 747         host = (struct atmel_mci *)data;
 748
 749         dev_dbg(&host->pdev->dev, "software timeout\n");
 750
 751         if (host->mrq->cmd->data) {
 752                 host->mrq->cmd->data->error = -ETIMEDOUT;
 753                 host->data = NULL;
 754                 /*
 755                  * With some SDIO modules, sometimes DMA transfer hangs. If
 756                  * stop_transfer() is not called then the DMA request is not
 757                  * removed, following ones are queued and never computed.
 758                  */
 759                 if (host->state == STATE_DATA_XFER)
 760                         host->stop_transfer(host);
 761         } else {
 762                 host->mrq->cmd->error = -ETIMEDOUT;
 763                 host->cmd = NULL;
 764         }
 765         host->need_reset = 1;
 766         host->state = STATE_END_REQUEST;
 767         smp_wmb();
 768         tasklet_schedule(&host->tasklet);
 769 }
 770
 771 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 772                                         unsigned int ns)
 773 {
 774         /*
 775          * It is easier here to use us instead of ns for the timeout,
 776          * it prevents from overflows during calculation.
 777          */
 778         unsigned int us = DIV_ROUND_UP(ns, 1000);
 779
 780         /* Maximum clock frequency is host->bus_hz/2 */
 781         return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 782 }
 783
 784 static void atmci_set_timeout(struct atmel_mci *host,
 785                 struct atmel_mci_slot *slot, struct mmc_data *data)
 786 {
 787         static unsigned dtomul_to_shift[] = {
 788                 0, 4, 7, 8, 10, 12, 16, 20
 789         };
 790         unsigned        timeout;
 791         unsigned        dtocyc;
 792         unsigned        dtomul;
 793
 794         timeout = atmci_ns_to_clocks(host, data->timeout_ns)
 795                 + data->timeout_clks;
 796
 797         for (dtomul = 0; dtomul < 8; dtomul++) {
 798                 unsigned shift = dtomul_to_shift[dtomul];
 799                 dtocyc = (timeout + (1 << shift) - 1) >> shift;
 800                 if (dtocyc < 15)
 801                         break;
 802         }
 803
 804         if (dtomul >= 8) {
 805                 dtomul = 7;
 806                 dtocyc = 15;
 807         }
 808
 809         dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
 810                         dtocyc << dtomul_to_shift[dtomul]);
 811         atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
 812 }
 813
 814 /*
 815  * Return mask with command flags to be enabled for this command.
 816  */
 817 static u32 atmci_prepare_command(struct mmc_host *mmc,
 818                                  struct mmc_command *cmd)
 819 {
 820         struct mmc_data *data;
 821         u32             cmdr;
 822
 823         cmd->error = -EINPROGRESS;
 824
 825         cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
 826
 827         if (cmd->flags & MMC_RSP_PRESENT) {
 828                 if (cmd->flags & MMC_RSP_136)
 829                         cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
 830                 else
 831                         cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
 832         }
 833
 834         /*
 835          * This should really be MAXLAT_5 for CMD2 and ACMD41, but
 836          * it's too difficult to determine whether this is an ACMD or
 837          * not. Better make it 64.
 838          */
 839         cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
 840
 841         if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
 842                 cmdr |= ATMCI_CMDR_OPDCMD;
 843
 844         data = cmd->data;
 845         if (data) {
 846                 cmdr |= ATMCI_CMDR_START_XFER;
 847
 848                 if (cmd->opcode == SD_IO_RW_EXTENDED) {
 849                         cmdr |= ATMCI_CMDR_SDIO_BLOCK;
 850                 } else {
 851                         if (data->flags & MMC_DATA_STREAM)
 852                                 cmdr |= ATMCI_CMDR_STREAM;
 853                         else if (data->blocks > 1)
 854                                 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
 855                         else
 856                                 cmdr |= ATMCI_CMDR_BLOCK;
 857                 }
 858
 859                 if (data->flags & MMC_DATA_READ)
 860                         cmdr |= ATMCI_CMDR_TRDIR_READ;
 861         }
 862
 863         return cmdr;
 864 }
 865
 866 static void atmci_send_command(struct atmel_mci *host,
 867                 struct mmc_command *cmd, u32 cmd_flags)
 868 {
 869         WARN_ON(host->cmd);
 870         host->cmd = cmd;
 871
 872         dev_vdbg(&host->pdev->dev,
 873                         "start command: ARGR=0x%08x CMDR=0x%08x\n",
 874                         cmd->arg, cmd_flags);
 875
 876         atmci_writel(host, ATMCI_ARGR, cmd->arg);
 877         atmci_writel(host, ATMCI_CMDR, cmd_flags);
 878 }
 879
 880 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
 881 {
 882         dev_dbg(&host->pdev->dev, "send stop command\n");
 883         atmci_send_command(host, data->stop, host->stop_cmdr);
 884         atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
 885 }
 886
 887 /*
 888  * Configure given PDC buffer taking care of alignement issues.
 889  * Update host->data_size and host->sg.
 890  */
 891 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
 892         enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
 893 {
 894         u32 pointer_reg, counter_reg;
 895         unsigned int buf_size;
 896
 897         if (dir == XFER_RECEIVE) {
 898                 pointer_reg = ATMEL_PDC_RPR;
 899                 counter_reg = ATMEL_PDC_RCR;
 900         } else {
 901                 pointer_reg = ATMEL_PDC_TPR;
 902                 counter_reg = ATMEL_PDC_TCR;
 903         }
 904
 905         if (buf_nb == PDC_SECOND_BUF) {
 906                 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
 907                 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
 908         }
 909
 910         if (!host->caps.has_rwproof) {
 911                 buf_size = host->buf_size;
 912                 atmci_writel(host, pointer_reg, host->buf_phys_addr);
 913         } else {
 914                 buf_size = sg_dma_len(host->sg);
 915                 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
 916         }
 917
 918         if (host->data_size <= buf_size) {
 919                 if (host->data_size & 0x3) {
 920                         /* If size is different from modulo 4, transfer bytes */
 921                         atmci_writel(host, counter_reg, host->data_size);
 922                         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
 923                 } else {
 924                         /* Else transfer 32-bits words */
 925                         atmci_writel(host, counter_reg, host->data_size / 4);
 926                 }
 927                 host->data_size = 0;
 928         } else {
 929                 /* We assume the size of a page is 32-bits aligned */
 930                 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
 931                 host->data_size -= sg_dma_len(host->sg);
 932                 if (host->data_size)
 933                         host->sg = sg_next(host->sg);
 934         }
 935 }
 936
 937 /*
 938  * Configure PDC buffer according to the data size ie configuring one or two
 939  * buffers. Don't use this function if you want to configure only the second
 940  * buffer. In this case, use atmci_pdc_set_single_buf.
 941  */
 942 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
 943 {
 944         atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
 945         if (host->data_size)
 946                 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
 947 }
 948
 949 /*
 950  * Unmap sg lists, called when transfer is finished.
 951  */
 952 static void atmci_pdc_cleanup(struct atmel_mci *host)
 953 {
 954         struct mmc_data         *data = host->data;
 955
 956         if (data)
 957                 dma_unmap_sg(&host->pdev->dev,
 958                                 data->sg, data->sg_len,
 959                                 ((data->flags & MMC_DATA_WRITE)
 960                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 961 }
 962
 963 /*
 964  * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
 965  * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
 966  * interrupt needed for both transfer directions.
 967  */
 968 static void atmci_pdc_complete(struct atmel_mci *host)
 969 {
 970         int transfer_size = host->data->blocks * host->data->blksz;
 971         int i;
 972
 973         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
 974
 975         if ((!host->caps.has_rwproof)
 976             && (host->data->flags & MMC_DATA_READ)) {
 977                 if (host->caps.has_bad_data_ordering)
 978                         for (i = 0; i < transfer_size; i++)
 979                                 host->buffer[i] = swab32(host->buffer[i]);
 980                 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
 981                                     host->buffer, transfer_size);
 982         }
 983
 984         atmci_pdc_cleanup(host);
 985
 986         dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
 987         atmci_set_pending(host, EVENT_XFER_COMPLETE);
 988         tasklet_schedule(&host->tasklet);
 989 }
 990
 991 static void atmci_dma_cleanup(struct atmel_mci *host)
 992 {
 993         struct mmc_data                 *data = host->data;
 994
 995         if (data)
 996                 dma_unmap_sg(host->dma.chan->device->dev,
 997                                 data->sg, data->sg_len,
 998                                 ((data->flags & MMC_DATA_WRITE)
 999                                  ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
1000 }
1001
1002 /*
1003  * This function is called by the DMA driver from tasklet context.
1004  */
1005 static void atmci_dma_complete(void *arg)
1006 {
1007         struct atmel_mci        *host = arg;
1008         struct mmc_data         *data = host->data;
1009
1010         dev_vdbg(&host->pdev->dev, "DMA complete\n");
1011
1012         if (host->caps.has_dma_conf_reg)
1013                 /* Disable DMA hardware handshaking on MCI */
1014                 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1015
1016         atmci_dma_cleanup(host);
1017
1018         /*
1019          * If the card was removed, data will be NULL. No point trying
1020          * to send the stop command or waiting for NBUSY in this case.
1021          */
1022         if (data) {
1023                 dev_dbg(&host->pdev->dev,
1024                         "(%s) set pending xfer complete\n", __func__);
1025                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1026                 tasklet_schedule(&host->tasklet);
1027
1028                 /*
1029                  * Regardless of what the documentation says, we have
1030                  * to wait for NOTBUSY even after block read
1031                  * operations.
1032                  *
1033                  * When the DMA transfer is complete, the controller
1034                  * may still be reading the CRC from the card, i.e.
1035                  * the data transfer is still in progress and we
1036                  * haven't seen all the potential error bits yet.
1037                  *
1038                  * The interrupt handler will schedule a different
1039                  * tasklet to finish things up when the data transfer
1040                  * is completely done.
1041                  *
1042                  * We may not complete the mmc request here anyway
1043                  * because the mmc layer may call back and cause us to
1044                  * violate the "don't submit new operations from the
1045                  * completion callback" rule of the dma engine
1046                  * framework.
1047                  */
1048                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1049         }
1050 }
1051
1052 /*
1053  * Returns a mask of interrupt flags to be enabled after the whole
1054  * request has been prepared.
1055  */
1056 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1057 {
1058         u32 iflags;
1059
1060         data->error = -EINPROGRESS;
1061
1062         host->sg = data->sg;
1063         host->sg_len = data->sg_len;
1064         host->data = data;
1065         host->data_chan = NULL;
1066
1067         iflags = ATMCI_DATA_ERROR_FLAGS;
1068
1069         /*
1070          * Errata: MMC data write operation with less than 12
1071          * bytes is impossible.
1072          *
1073          * Errata: MCI Transmit Data Register (TDR) FIFO
1074          * corruption when length is not multiple of 4.
1075          */
1076         if (data->blocks * data->blksz < 12
1077                         || (data->blocks * data->blksz) & 3)
1078                 host->need_reset = true;
1079
1080         host->pio_offset = 0;
1081         if (data->flags & MMC_DATA_READ)
1082                 iflags |= ATMCI_RXRDY;
1083         else
1084                 iflags |= ATMCI_TXRDY;
1085
1086         return iflags;
1087 }
1088
1089 /*
1090  * Set interrupt flags and set block length into the MCI mode register even
1091  * if this value is also accessible in the MCI block register. It seems to be
1092  * necessary before the High Speed MCI version. It also map sg and configure
1093  * PDC registers.
1094  */
1095 static u32
1096 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1097 {
1098         u32 iflags, tmp;
1099         unsigned int sg_len;
1100         enum dma_data_direction dir;
1101         int i;
1102
1103         data->error = -EINPROGRESS;
1104
1105         host->data = data;
1106         host->sg = data->sg;
1107         iflags = ATMCI_DATA_ERROR_FLAGS;
1108
1109         /* Enable pdc mode */
1110         atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1111
1112         if (data->flags & MMC_DATA_READ) {
1113                 dir = DMA_FROM_DEVICE;
1114                 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1115         } else {
1116                 dir = DMA_TO_DEVICE;
1117                 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1118         }
1119
1120         /* Set BLKLEN */
1121         tmp = atmci_readl(host, ATMCI_MR);
1122         tmp &= 0x0000ffff;
1123         tmp |= ATMCI_BLKLEN(data->blksz);
1124         atmci_writel(host, ATMCI_MR, tmp);
1125
1126         /* Configure PDC */
1127         host->data_size = data->blocks * data->blksz;
1128         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
1129
1130         if ((!host->caps.has_rwproof)
1131             && (host->data->flags & MMC_DATA_WRITE)) {
1132                 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1133                                   host->buffer, host->data_size);
1134                 if (host->caps.has_bad_data_ordering)
1135                         for (i = 0; i < host->data_size; i++)
1136                                 host->buffer[i] = swab32(host->buffer[i]);
1137         }
1138
1139         if (host->data_size)
1140                 atmci_pdc_set_both_buf(host,
1141                         ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
1142
1143         return iflags;
1144 }
1145
1146 static u32
1147 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1148 {
1149         struct dma_chan                 *chan;
1150         struct dma_async_tx_descriptor  *desc;
1151         struct scatterlist              *sg;
1152         unsigned int                    i;
1153         enum dma_data_direction         direction;
1154         enum dma_transfer_direction     slave_dirn;
1155         unsigned int                    sglen;
1156         u32                             maxburst;
1157         u32 iflags;
1158
1159         data->error = -EINPROGRESS;
1160
1161         WARN_ON(host->data);
1162         host->sg = NULL;
1163         host->data = data;
1164
1165         iflags = ATMCI_DATA_ERROR_FLAGS;
1166
1167         /*
1168          * We don't do DMA on "complex" transfers, i.e. with
1169          * non-word-aligned buffers or lengths. Also, we don't bother
1170          * with all the DMA setup overhead for short transfers.
1171          */
1172         if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1173                 return atmci_prepare_data(host, data);
1174         if (data->blksz & 3)
1175                 return atmci_prepare_data(host, data);
1176
1177         for_each_sg(data->sg, sg, data->sg_len, i) {
1178                 if (sg->offset & 3 || sg->length & 3)
1179                         return atmci_prepare_data(host, data);
1180         }
1181
1182         /* If we don't have a channel, we can't do DMA */
1183         chan = host->dma.chan;
1184         if (chan)
1185                 host->data_chan = chan;
1186
1187         if (!chan)
1188                 return -ENODEV;
1189
1190         if (data->flags & MMC_DATA_READ) {
1191                 direction = DMA_FROM_DEVICE;
1192                 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1193                 maxburst = atmci_convert_chksize(host,
1194                                                  host->dma_conf.src_maxburst);
1195         } else {
1196                 direction = DMA_TO_DEVICE;
1197                 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1198                 maxburst = atmci_convert_chksize(host,
1199                                                  host->dma_conf.dst_maxburst);
1200         }
1201
1202         if (host->caps.has_dma_conf_reg)
1203                 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1204                         ATMCI_DMAEN);
1205
1206         sglen = dma_map_sg(chan->device->dev, data->sg,
1207                         data->sg_len, direction);
1208
1209         dmaengine_slave_config(chan, &host->dma_conf);
1210         desc = dmaengine_prep_slave_sg(chan,
1211                         data->sg, sglen, slave_dirn,
1212                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1213         if (!desc)
1214                 goto unmap_exit;
1215
1216         host->dma.data_desc = desc;
1217         desc->callback = atmci_dma_complete;
1218         desc->callback_param = host;
1219
1220         return iflags;
1221 unmap_exit:
1222         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1223         return -ENOMEM;
1224 }
1225
1226 static void
1227 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1228 {
1229         return;
1230 }
1231
1232 /*
1233  * Start PDC according to transfer direction.
1234  */
1235 static void
1236 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1237 {
1238         if (data->flags & MMC_DATA_READ)
1239                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1240         else
1241                 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1242 }
1243
1244 static void
1245 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1246 {
1247         struct dma_chan                 *chan = host->data_chan;
1248         struct dma_async_tx_descriptor  *desc = host->dma.data_desc;
1249
1250         if (chan) {
1251                 dmaengine_submit(desc);
1252                 dma_async_issue_pending(chan);
1253         }
1254 }
1255
1256 static void atmci_stop_transfer(struct atmel_mci *host)
1257 {
1258         dev_dbg(&host->pdev->dev,
1259                 "(%s) set pending xfer complete\n", __func__);
1260         atmci_set_pending(host, EVENT_XFER_COMPLETE);
1261         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1262 }
1263
1264 /*
1265  * Stop data transfer because error(s) occurred.
1266  */
1267 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1268 {
1269         atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1270 }
1271
1272 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1273 {
1274         struct dma_chan *chan = host->data_chan;
1275
1276         if (chan) {
1277                 dmaengine_terminate_all(chan);
1278                 atmci_dma_cleanup(host);
1279         } else {
1280                 /* Data transfer was stopped by the interrupt handler */
1281                 dev_dbg(&host->pdev->dev,
1282                         "(%s) set pending xfer complete\n", __func__);
1283                 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1284                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1285         }
1286 }
1287
1288 /*
1289  * Start a request: prepare data if needed, prepare the command and activate
1290  * interrupts.
1291  */
1292 static void atmci_start_request(struct atmel_mci *host,
1293                 struct atmel_mci_slot *slot)
1294 {
1295         struct mmc_request      *mrq;
1296         struct mmc_command      *cmd;
1297         struct mmc_data         *data;
1298         u32                     iflags;
1299         u32                     cmdflags;
1300
1301         mrq = slot->mrq;
1302         host->cur_slot = slot;
1303         host->mrq = mrq;
1304
1305         host->pending_events = 0;
1306         host->completed_events = 0;
1307         host->cmd_status = 0;
1308         host->data_status = 0;
1309
1310         dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1311
1312         if (host->need_reset || host->caps.need_reset_after_xfer) {
1313                 iflags = atmci_readl(host, ATMCI_IMR);
1314                 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1315                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1316                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1317                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1318                 if (host->caps.has_cfg_reg)
1319                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1320                 atmci_writel(host, ATMCI_IER, iflags);
1321                 host->need_reset = false;
1322         }
1323         atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1324
1325         iflags = atmci_readl(host, ATMCI_IMR);
1326         if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1327                 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1328                                 iflags);
1329
1330         if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1331                 /* Send init sequence (74 clock cycles) */
1332                 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1333                 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1334                         cpu_relax();
1335         }
1336         iflags = 0;
1337         data = mrq->data;
1338         if (data) {
1339                 atmci_set_timeout(host, slot, data);
1340
1341                 /* Must set block count/size before sending command */
1342                 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1343                                 | ATMCI_BLKLEN(data->blksz));
1344                 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1345                         ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1346
1347                 iflags |= host->prepare_data(host, data);
1348         }
1349
1350         iflags |= ATMCI_CMDRDY;
1351         cmd = mrq->cmd;
1352         cmdflags = atmci_prepare_command(slot->mmc, cmd);
1353
1354         /*
1355          * DMA transfer should be started before sending the command to avoid
1356          * unexpected errors especially for read operations in SDIO mode.
1357          * Unfortunately, in PDC mode, command has to be sent before starting
1358          * the transfer.
1359          */
1360         if (host->submit_data != &atmci_submit_data_dma)
1361                 atmci_send_command(host, cmd, cmdflags);
1362
1363         if (data)
1364                 host->submit_data(host, data);
1365
1366         if (host->submit_data == &atmci_submit_data_dma)
1367                 atmci_send_command(host, cmd, cmdflags);
1368
1369         if (mrq->stop) {
1370                 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1371                 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1372                 if (!(data->flags & MMC_DATA_WRITE))
1373                         host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1374                 if (data->flags & MMC_DATA_STREAM)
1375                         host->stop_cmdr |= ATMCI_CMDR_STREAM;
1376                 else
1377                         host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1378         }
1379
1380         /*
1381          * We could have enabled interrupts earlier, but I suspect
1382          * that would open up a nice can of interesting race
1383          * conditions (e.g. command and data complete, but stop not
1384          * prepared yet.)
1385          */
1386         atmci_writel(host, ATMCI_IER, iflags);
1387
1388         mod_timer(&host->timer, jiffies +  msecs_to_jiffies(2000));
1389 }
1390
1391 static void atmci_queue_request(struct atmel_mci *host,
1392                 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1393 {
1394         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1395                         host->state);
1396
1397         spin_lock_bh(&host->lock);
1398         slot->mrq = mrq;
1399         if (host->state == STATE_IDLE) {
1400                 host->state = STATE_SENDING_CMD;
1401                 atmci_start_request(host, slot);
1402         } else {
1403                 dev_dbg(&host->pdev->dev, "queue request\n");
1404                 list_add_tail(&slot->queue_node, &host->queue);
1405         }
1406         spin_unlock_bh(&host->lock);
1407 }
1408
1409 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1410 {
1411         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1412         struct atmel_mci        *host = slot->host;
1413         struct mmc_data         *data;
1414
1415         WARN_ON(slot->mrq);
1416         dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1417
1418         pm_runtime_get_sync(&host->pdev->dev);
1419
1420         /*
1421          * We may "know" the card is gone even though there's still an
1422          * electrical connection. If so, we really need to communicate
1423          * this to the MMC core since there won't be any more
1424          * interrupts as the card is completely removed. Otherwise,
1425          * the MMC core might believe the card is still there even
1426          * though the card was just removed very slowly.
1427          */
1428         if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1429                 mrq->cmd->error = -ENOMEDIUM;
1430                 mmc_request_done(mmc, mrq);
1431                 return;
1432         }
1433
1434         /* We don't support multiple blocks of weird lengths. */
1435         data = mrq->data;
1436         if (data && data->blocks > 1 && data->blksz & 3) {
1437                 mrq->cmd->error = -EINVAL;
1438                 mmc_request_done(mmc, mrq);
1439         }
1440
1441         atmci_queue_request(host, slot, mrq);
1442 }
1443
1444 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1445 {
1446         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1447         struct atmel_mci        *host = slot->host;
1448         unsigned int            i;
1449
1450         pm_runtime_get_sync(&host->pdev->dev);
1451
1452         slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1453         switch (ios->bus_width) {
1454         case MMC_BUS_WIDTH_1:
1455                 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1456                 break;
1457         case MMC_BUS_WIDTH_4:
1458                 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1459                 break;
1460         }
1461
1462         if (ios->clock) {
1463                 unsigned int clock_min = ~0U;
1464                 int clkdiv;
1465
1466                 spin_lock_bh(&host->lock);
1467                 if (!host->mode_reg) {
1468                         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1469                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1470                         if (host->caps.has_cfg_reg)
1471                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1472                 }
1473
1474                 /*
1475                  * Use mirror of ios->clock to prevent race with mmc
1476                  * core ios update when finding the minimum.
1477                  */
1478                 slot->clock = ios->clock;
1479                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1480                         if (host->slot[i] && host->slot[i]->clock
1481                                         && host->slot[i]->clock < clock_min)
1482                                 clock_min = host->slot[i]->clock;
1483                 }
1484
1485                 /* Calculate clock divider */
1486                 if (host->caps.has_odd_clk_div) {
1487                         clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1488                         if (clkdiv < 0) {
1489                                 dev_warn(&mmc->class_dev,
1490                                          "clock %u too fast; using %lu\n",
1491                                          clock_min, host->bus_hz / 2);
1492                                 clkdiv = 0;
1493                         } else if (clkdiv > 511) {
1494                                 dev_warn(&mmc->class_dev,
1495                                          "clock %u too slow; using %lu\n",
1496                                          clock_min, host->bus_hz / (511 + 2));
1497                                 clkdiv = 511;
1498                         }
1499                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1500                                          | ATMCI_MR_CLKODD(clkdiv & 1);
1501                 } else {
1502                         clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1503                         if (clkdiv > 255) {
1504                                 dev_warn(&mmc->class_dev,
1505                                          "clock %u too slow; using %lu\n",
1506                                          clock_min, host->bus_hz / (2 * 256));
1507                                 clkdiv = 255;
1508                         }
1509                         host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1510                 }
1511
1512                 /*
1513                  * WRPROOF and RDPROOF prevent overruns/underruns by
1514                  * stopping the clock when the FIFO is full/empty.
1515                  * This state is not expected to last for long.
1516                  */
1517                 if (host->caps.has_rwproof)
1518                         host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1519
1520                 if (host->caps.has_cfg_reg) {
1521                         /* setup High Speed mode in relation with card capacity */
1522                         if (ios->timing == MMC_TIMING_SD_HS)
1523                                 host->cfg_reg |= ATMCI_CFG_HSMODE;
1524                         else
1525                                 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1526                 }
1527
1528                 if (list_empty(&host->queue)) {
1529                         atmci_writel(host, ATMCI_MR, host->mode_reg);
1530                         if (host->caps.has_cfg_reg)
1531                                 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1532                 } else {
1533                         host->need_clock_update = true;
1534                 }
1535
1536                 spin_unlock_bh(&host->lock);
1537         } else {
1538                 bool any_slot_active = false;
1539
1540                 spin_lock_bh(&host->lock);
1541                 slot->clock = 0;
1542                 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1543                         if (host->slot[i] && host->slot[i]->clock) {
1544                                 any_slot_active = true;
1545                                 break;
1546                         }
1547                 }
1548                 if (!any_slot_active) {
1549                         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1550                         if (host->mode_reg) {
1551                                 atmci_readl(host, ATMCI_MR);
1552                         }
1553                         host->mode_reg = 0;
1554                 }
1555                 spin_unlock_bh(&host->lock);
1556         }
1557
1558         switch (ios->power_mode) {
1559         case MMC_POWER_OFF:
1560                 if (!IS_ERR(mmc->supply.vmmc))
1561                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1562                 break;
1563         case MMC_POWER_UP:
1564                 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1565                 if (!IS_ERR(mmc->supply.vmmc))
1566                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1567                 break;
1568         default:
1569                 /*
1570                  * TODO: None of the currently available AVR32-based
1571                  * boards allow MMC power to be turned off. Implement
1572                  * power control when this can be tested properly.
1573                  *
1574                  * We also need to hook this into the clock management
1575                  * somehow so that newly inserted cards aren't
1576                  * subjected to a fast clock before we have a chance
1577                  * to figure out what the maximum rate is. Currently,
1578                  * there's no way to avoid this, and there never will
1579                  * be for boards that don't support power control.
1580                  */
1581                 break;
1582         }
1583
1584         pm_runtime_mark_last_busy(&host->pdev->dev);
1585         pm_runtime_put_autosuspend(&host->pdev->dev);
1586 }
1587
1588 static int atmci_get_ro(struct mmc_host *mmc)
1589 {
1590         int                     read_only = -ENOSYS;
1591         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1592
1593         if (gpio_is_valid(slot->wp_pin)) {
1594                 read_only = gpio_get_value(slot->wp_pin);
1595                 dev_dbg(&mmc->class_dev, "card is %s\n",
1596                                 read_only ? "read-only" : "read-write");
1597         }
1598
1599         return read_only;
1600 }
1601
1602 static int atmci_get_cd(struct mmc_host *mmc)
1603 {
1604         int                     present = -ENOSYS;
1605         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1606
1607         if (gpio_is_valid(slot->detect_pin)) {
1608                 present = !(gpio_get_value(slot->detect_pin) ^
1609                             slot->detect_is_active_high);
1610                 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1611                                 present ? "" : "not ");
1612         }
1613
1614         return present;
1615 }
1616
1617 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1618 {
1619         struct atmel_mci_slot   *slot = mmc_priv(mmc);
1620         struct atmel_mci        *host = slot->host;
1621
1622         if (enable)
1623                 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1624         else
1625                 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1626 }
1627
1628 static const struct mmc_host_ops atmci_ops = {
1629         .request        = atmci_request,
1630         .set_ios        = atmci_set_ios,
1631         .get_ro         = atmci_get_ro,
1632         .get_cd         = atmci_get_cd,
1633         .enable_sdio_irq = atmci_enable_sdio_irq,
1634 };
1635
1636 /* Called with host->lock held */
1637 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1638         __releases(&host->lock)
1639         __acquires(&host->lock)
1640 {
1641         struct atmel_mci_slot   *slot = NULL;
1642         struct mmc_host         *prev_mmc = host->cur_slot->mmc;
1643
1644         WARN_ON(host->cmd || host->data);
1645
1646         /*
1647          * Update the MMC clock rate if necessary. This may be
1648          * necessary if set_ios() is called when a different slot is
1649          * busy transferring data.
1650          */
1651         if (host->need_clock_update) {
1652                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1653                 if (host->caps.has_cfg_reg)
1654                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1655         }
1656
1657         host->cur_slot->mrq = NULL;
1658         host->mrq = NULL;
1659         if (!list_empty(&host->queue)) {
1660                 slot = list_entry(host->queue.next,
1661                                 struct atmel_mci_slot, queue_node);
1662                 list_del(&slot->queue_node);
1663                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1664                                 mmc_hostname(slot->mmc));
1665                 host->state = STATE_SENDING_CMD;
1666                 atmci_start_request(host, slot);
1667         } else {
1668                 dev_vdbg(&host->pdev->dev, "list empty\n");
1669                 host->state = STATE_IDLE;
1670         }
1671
1672         del_timer(&host->timer);
1673
1674         spin_unlock(&host->lock);
1675         mmc_request_done(prev_mmc, mrq);
1676         spin_lock(&host->lock);
1677
1678         pm_runtime_mark_last_busy(&host->pdev->dev);
1679         pm_runtime_put_autosuspend(&host->pdev->dev);
1680 }
1681
1682 static void atmci_command_complete(struct atmel_mci *host,
1683                         struct mmc_command *cmd)
1684 {
1685         u32             status = host->cmd_status;
1686
1687         /* Read the response from the card (up to 16 bytes) */
1688         cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1689         cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1690         cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1691         cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1692
1693         if (status & ATMCI_RTOE)
1694                 cmd->error = -ETIMEDOUT;
1695         else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1696                 cmd->error = -EILSEQ;
1697         else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1698                 cmd->error = -EIO;
1699         else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1700                 if (host->caps.need_blksz_mul_4) {
1701                         cmd->error = -EINVAL;
1702                         host->need_reset = 1;
1703                 }
1704         } else
1705                 cmd->error = 0;
1706 }
1707
1708 static void atmci_detect_change(unsigned long data)
1709 {
1710         struct atmel_mci_slot   *slot = (struct atmel_mci_slot *)data;
1711         bool                    present;
1712         bool                    present_old;
1713
1714         /*
1715          * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1716          * freeing the interrupt. We must not re-enable the interrupt
1717          * if it has been freed, and if we're shutting down, it
1718          * doesn't really matter whether the card is present or not.
1719          */
1720         smp_rmb();
1721         if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1722                 return;
1723
1724         enable_irq(gpio_to_irq(slot->detect_pin));
1725         present = !(gpio_get_value(slot->detect_pin) ^
1726                     slot->detect_is_active_high);
1727         present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1728
1729         dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1730                         present, present_old);
1731
1732         if (present != present_old) {
1733                 struct atmel_mci        *host = slot->host;
1734                 struct mmc_request      *mrq;
1735
1736                 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1737                         present ? "inserted" : "removed");
1738
1739                 spin_lock(&host->lock);
1740
1741                 if (!present)
1742                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1743                 else
1744                         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1745
1746                 /* Clean up queue if present */
1747                 mrq = slot->mrq;
1748                 if (mrq) {
1749                         if (mrq == host->mrq) {
1750                                 /*
1751                                  * Reset controller to terminate any ongoing
1752                                  * commands or data transfers.
1753                                  */
1754                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1755                                 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1756                                 atmci_writel(host, ATMCI_MR, host->mode_reg);
1757                                 if (host->caps.has_cfg_reg)
1758                                         atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1759
1760                                 host->data = NULL;
1761                                 host->cmd = NULL;
1762
1763                                 switch (host->state) {
1764                                 case STATE_IDLE:
1765                                         break;
1766                                 case STATE_SENDING_CMD:
1767                                         mrq->cmd->error = -ENOMEDIUM;
1768                                         if (mrq->data)
1769                                                 host->stop_transfer(host);
1770                                         break;
1771                                 case STATE_DATA_XFER:
1772                                         mrq->data->error = -ENOMEDIUM;
1773                                         host->stop_transfer(host);
1774                                         break;
1775                                 case STATE_WAITING_NOTBUSY:
1776                                         mrq->data->error = -ENOMEDIUM;
1777                                         break;
1778                                 case STATE_SENDING_STOP:
1779                                         mrq->stop->error = -ENOMEDIUM;
1780                                         break;
1781                                 case STATE_END_REQUEST:
1782                                         break;
1783                                 }
1784
1785                                 atmci_request_end(host, mrq);
1786                         } else {
1787                                 list_del(&slot->queue_node);
1788                                 mrq->cmd->error = -ENOMEDIUM;
1789                                 if (mrq->data)
1790                                         mrq->data->error = -ENOMEDIUM;
1791                                 if (mrq->stop)
1792                                         mrq->stop->error = -ENOMEDIUM;
1793
1794                                 spin_unlock(&host->lock);
1795                                 mmc_request_done(slot->mmc, mrq);
1796                                 spin_lock(&host->lock);
1797                         }
1798                 }
1799                 spin_unlock(&host->lock);
1800
1801                 mmc_detect_change(slot->mmc, 0);
1802         }
1803 }
1804
1805 static void atmci_tasklet_func(unsigned long priv)
1806 {
1807         struct atmel_mci        *host = (struct atmel_mci *)priv;
1808         struct mmc_request      *mrq = host->mrq;
1809         struct mmc_data         *data = host->data;
1810         enum atmel_mci_state    state = host->state;
1811         enum atmel_mci_state    prev_state;
1812         u32                     status;
1813
1814         spin_lock(&host->lock);
1815
1816         state = host->state;
1817
1818         dev_vdbg(&host->pdev->dev,
1819                 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1820                 state, host->pending_events, host->completed_events,
1821                 atmci_readl(host, ATMCI_IMR));
1822
1823         do {
1824                 prev_state = state;
1825                 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1826
1827                 switch (state) {
1828                 case STATE_IDLE:
1829                         break;
1830
1831                 case STATE_SENDING_CMD:
1832                         /*
1833                          * Command has been sent, we are waiting for command
1834                          * ready. Then we have three next states possible:
1835                          * END_REQUEST by default, WAITING_NOTBUSY if it's a
1836                          * command needing it or DATA_XFER if there is data.
1837                          */
1838                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1839                         if (!atmci_test_and_clear_pending(host,
1840                                                 EVENT_CMD_RDY))
1841                                 break;
1842
1843                         dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1844                         host->cmd = NULL;
1845                         atmci_set_completed(host, EVENT_CMD_RDY);
1846                         atmci_command_complete(host, mrq->cmd);
1847                         if (mrq->data) {
1848                                 dev_dbg(&host->pdev->dev,
1849                                         "command with data transfer");
1850                                 /*
1851                                  * If there is a command error don't start
1852                                  * data transfer.
1853                                  */
1854                                 if (mrq->cmd->error) {
1855                                         host->stop_transfer(host);
1856                                         host->data = NULL;
1857                                         atmci_writel(host, ATMCI_IDR,
1858                                                      ATMCI_TXRDY | ATMCI_RXRDY
1859                                                      | ATMCI_DATA_ERROR_FLAGS);
1860                                         state = STATE_END_REQUEST;
1861                                 } else
1862                                         state = STATE_DATA_XFER;
1863                         } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1864                                 dev_dbg(&host->pdev->dev,
1865                                         "command response need waiting notbusy");
1866                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1867                                 state = STATE_WAITING_NOTBUSY;
1868                         } else
1869                                 state = STATE_END_REQUEST;
1870
1871                         break;
1872
1873                 case STATE_DATA_XFER:
1874                         if (atmci_test_and_clear_pending(host,
1875                                                 EVENT_DATA_ERROR)) {
1876                                 dev_dbg(&host->pdev->dev, "set completed data error\n");
1877                                 atmci_set_completed(host, EVENT_DATA_ERROR);
1878                                 state = STATE_END_REQUEST;
1879                                 break;
1880                         }
1881
1882                         /*
1883                          * A data transfer is in progress. The event expected
1884                          * to move to the next state depends of data transfer
1885                          * type (PDC or DMA). Once transfer done we can move
1886                          * to the next step which is WAITING_NOTBUSY in write
1887                          * case and directly SENDING_STOP in read case.
1888                          */
1889                         dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1890                         if (!atmci_test_and_clear_pending(host,
1891                                                 EVENT_XFER_COMPLETE))
1892                                 break;
1893
1894                         dev_dbg(&host->pdev->dev,
1895                                 "(%s) set completed xfer complete\n",
1896                                 __func__);
1897                         atmci_set_completed(host, EVENT_XFER_COMPLETE);
1898
1899                         if (host->caps.need_notbusy_for_read_ops ||
1900                            (host->data->flags & MMC_DATA_WRITE)) {
1901                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1902                                 state = STATE_WAITING_NOTBUSY;
1903                         } else if (host->mrq->stop) {
1904                                 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1905                                 atmci_send_stop_cmd(host, data);
1906                                 state = STATE_SENDING_STOP;
1907                         } else {
1908                                 host->data = NULL;
1909                                 data->bytes_xfered = data->blocks * data->blksz;
1910                                 data->error = 0;
1911                                 state = STATE_END_REQUEST;
1912                         }
1913                         break;
1914
1915                 case STATE_WAITING_NOTBUSY:
1916                         /*
1917                          * We can be in the state for two reasons: a command
1918                          * requiring waiting not busy signal (stop command
1919                          * included) or a write operation. In the latest case,
1920                          * we need to send a stop command.
1921                          */
1922                         dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1923                         if (!atmci_test_and_clear_pending(host,
1924                                                 EVENT_NOTBUSY))
1925                                 break;
1926
1927                         dev_dbg(&host->pdev->dev, "set completed not busy\n");
1928                         atmci_set_completed(host, EVENT_NOTBUSY);
1929
1930                         if (host->data) {
1931                                 /*
1932                                  * For some commands such as CMD53, even if
1933                                  * there is data transfer, there is no stop
1934                                  * command to send.
1935                                  */
1936                                 if (host->mrq->stop) {
1937                                         atmci_writel(host, ATMCI_IER,
1938                                                      ATMCI_CMDRDY);
1939                                         atmci_send_stop_cmd(host, data);
1940                                         state = STATE_SENDING_STOP;
1941                                 } else {
1942                                         host->data = NULL;
1943                                         data->bytes_xfered = data->blocks
1944                                                              * data->blksz;
1945                                         data->error = 0;
1946                                         state = STATE_END_REQUEST;
1947                                 }
1948                         } else
1949                                 state = STATE_END_REQUEST;
1950                         break;
1951
1952                 case STATE_SENDING_STOP:
1953                         /*
1954                          * In this state, it is important to set host->data to
1955                          * NULL (which is tested in the waiting notbusy state)
1956                          * in order to go to the end request state instead of
1957                          * sending stop again.
1958                          */
1959                         dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1960                         if (!atmci_test_and_clear_pending(host,
1961                                                 EVENT_CMD_RDY))
1962                                 break;
1963
1964                         dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1965                         host->cmd = NULL;
1966                         data->bytes_xfered = data->blocks * data->blksz;
1967                         data->error = 0;
1968                         atmci_command_complete(host, mrq->stop);
1969                         if (mrq->stop->error) {
1970                                 host->stop_transfer(host);
1971                                 atmci_writel(host, ATMCI_IDR,
1972                                              ATMCI_TXRDY | ATMCI_RXRDY
1973                                              | ATMCI_DATA_ERROR_FLAGS);
1974                                 state = STATE_END_REQUEST;
1975                         } else {
1976                                 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1977                                 state = STATE_WAITING_NOTBUSY;
1978                         }
1979                         host->data = NULL;
1980                         break;
1981
1982                 case STATE_END_REQUEST:
1983                         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1984                                            | ATMCI_DATA_ERROR_FLAGS);
1985                         status = host->data_status;
1986                         if (unlikely(status)) {
1987                                 host->stop_transfer(host);
1988                                 host->data = NULL;
1989                                 if (data) {
1990                                         if (status & ATMCI_DTOE) {
1991                                                 data->error = -ETIMEDOUT;
1992                                         } else if (status & ATMCI_DCRCE) {
1993                                                 data->error = -EILSEQ;
1994                                         } else {
1995                                                 data->error = -EIO;
1996                                         }
1997                                 }
1998                         }
1999
2000                         atmci_request_end(host, host->mrq);
2001                         state = STATE_IDLE;
2002                         break;
2003                 }
2004         } while (state != prev_state);
2005
2006         host->state = state;
2007
2008         spin_unlock(&host->lock);
2009 }
2010
2011 static void atmci_read_data_pio(struct atmel_mci *host)
2012 {
2013         struct scatterlist      *sg = host->sg;
2014         void                    *buf = sg_virt(sg);
2015         unsigned int            offset = host->pio_offset;
2016         struct mmc_data         *data = host->data;
2017         u32                     value;
2018         u32                     status;
2019         unsigned int            nbytes = 0;
2020
2021         do {
2022                 value = atmci_readl(host, ATMCI_RDR);
2023                 if (likely(offset + 4 <= sg->length)) {
2024                         put_unaligned(value, (u32 *)(buf + offset));
2025
2026                         offset += 4;
2027                         nbytes += 4;
2028
2029                         if (offset == sg->length) {
2030                                 flush_dcache_page(sg_page(sg));
2031                                 host->sg = sg = sg_next(sg);
2032                                 host->sg_len--;
2033                                 if (!sg || !host->sg_len)
2034                                         goto done;
2035
2036                                 offset = 0;
2037                                 buf = sg_virt(sg);
2038                         }
2039                 } else {
2040                         unsigned int remaining = sg->length - offset;
2041                         memcpy(buf + offset, &value, remaining);
2042                         nbytes += remaining;
2043
2044                         flush_dcache_page(sg_page(sg));
2045                         host->sg = sg = sg_next(sg);
2046                         host->sg_len--;
2047                         if (!sg || !host->sg_len)
2048                                 goto done;
2049
2050                         offset = 4 - remaining;
2051                         buf = sg_virt(sg);
2052                         memcpy(buf, (u8 *)&value + remaining, offset);
2053                         nbytes += offset;
2054                 }
2055
2056                 status = atmci_readl(host, ATMCI_SR);
2057                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2058                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
2059                                                 | ATMCI_DATA_ERROR_FLAGS));
2060                         host->data_status = status;
2061                         data->bytes_xfered += nbytes;
2062                         return;
2063                 }
2064         } while (status & ATMCI_RXRDY);
2065
2066         host->pio_offset = offset;
2067         data->bytes_xfered += nbytes;
2068
2069         return;
2070
2071 done:
2072         atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2073         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2074         data->bytes_xfered += nbytes;
2075         smp_wmb();
2076         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2077 }
2078
2079 static void atmci_write_data_pio(struct atmel_mci *host)
2080 {
2081         struct scatterlist      *sg = host->sg;
2082         void                    *buf = sg_virt(sg);
2083         unsigned int            offset = host->pio_offset;
2084         struct mmc_data         *data = host->data;
2085         u32                     value;
2086         u32                     status;
2087         unsigned int            nbytes = 0;
2088
2089         do {
2090                 if (likely(offset + 4 <= sg->length)) {
2091                         value = get_unaligned((u32 *)(buf + offset));
2092                         atmci_writel(host, ATMCI_TDR, value);
2093
2094                         offset += 4;
2095                         nbytes += 4;
2096                         if (offset == sg->length) {
2097                                 host->sg = sg = sg_next(sg);
2098                                 host->sg_len--;
2099                                 if (!sg || !host->sg_len)
2100                                         goto done;
2101
2102                                 offset = 0;
2103                                 buf = sg_virt(sg);
2104                         }
2105                 } else {
2106                         unsigned int remaining = sg->length - offset;
2107
2108                         value = 0;
2109                         memcpy(&value, buf + offset, remaining);
2110                         nbytes += remaining;
2111
2112                         host->sg = sg = sg_next(sg);
2113                         host->sg_len--;
2114                         if (!sg || !host->sg_len) {
2115                                 atmci_writel(host, ATMCI_TDR, value);
2116                                 goto done;
2117                         }
2118
2119                         offset = 4 - remaining;
2120                         buf = sg_virt(sg);
2121                         memcpy((u8 *)&value + remaining, buf, offset);
2122                         atmci_writel(host, ATMCI_TDR, value);
2123                         nbytes += offset;
2124                 }
2125
2126                 status = atmci_readl(host, ATMCI_SR);
2127                 if (status & ATMCI_DATA_ERROR_FLAGS) {
2128                         atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2129                                                 | ATMCI_DATA_ERROR_FLAGS));
2130                         host->data_status = status;
2131                         data->bytes_xfered += nbytes;
2132                         return;
2133                 }
2134         } while (status & ATMCI_TXRDY);
2135
2136         host->pio_offset = offset;
2137         data->bytes_xfered += nbytes;
2138
2139         return;
2140
2141 done:
2142         atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2143         atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2144         data->bytes_xfered += nbytes;
2145         smp_wmb();
2146         atmci_set_pending(host, EVENT_XFER_COMPLETE);
2147 }
2148
2149 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2150 {
2151         int     i;
2152
2153         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2154                 struct atmel_mci_slot *slot = host->slot[i];
2155                 if (slot && (status & slot->sdio_irq)) {
2156                         mmc_signal_sdio_irq(slot->mmc);
2157                 }
2158         }
2159 }
2160
2161
2162 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2163 {
2164         struct atmel_mci        *host = dev_id;
2165         u32                     status, mask, pending;
2166         unsigned int            pass_count = 0;
2167
2168         do {
2169                 status = atmci_readl(host, ATMCI_SR);
2170                 mask = atmci_readl(host, ATMCI_IMR);
2171                 pending = status & mask;
2172                 if (!pending)
2173                         break;
2174
2175                 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2176                         dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2177                         atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2178                                         | ATMCI_RXRDY | ATMCI_TXRDY
2179                                         | ATMCI_ENDRX | ATMCI_ENDTX
2180                                         | ATMCI_RXBUFF | ATMCI_TXBUFE);
2181
2182                         host->data_status = status;
2183                         dev_dbg(&host->pdev->dev, "set pending data error\n");
2184                         smp_wmb();
2185                         atmci_set_pending(host, EVENT_DATA_ERROR);
2186                         tasklet_schedule(&host->tasklet);
2187                 }
2188
2189                 if (pending & ATMCI_TXBUFE) {
2190                         dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2191                         atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2192                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2193                         /*
2194                          * We can receive this interruption before having configured
2195                          * the second pdc buffer, so we need to reconfigure first and
2196                          * second buffers again
2197                          */
2198                         if (host->data_size) {
2199                                 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2200                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2201                                 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2202                         } else {
2203                                 atmci_pdc_complete(host);
2204                         }
2205                 } else if (pending & ATMCI_ENDTX) {
2206                         dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2207                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2208
2209                         if (host->data_size) {
2210                                 atmci_pdc_set_single_buf(host,
2211                                                 XFER_TRANSMIT, PDC_SECOND_BUF);
2212                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2213                         }
2214                 }
2215
2216                 if (pending & ATMCI_RXBUFF) {
2217                         dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2218                         atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2219                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2220                         /*
2221                          * We can receive this interruption before having configured
2222                          * the second pdc buffer, so we need to reconfigure first and
2223                          * second buffers again
2224                          */
2225                         if (host->data_size) {
2226                                 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2227                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2228                                 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2229                         } else {
2230                                 atmci_pdc_complete(host);
2231                         }
2232                 } else if (pending & ATMCI_ENDRX) {
2233                         dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2234                         atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2235
2236                         if (host->data_size) {
2237                                 atmci_pdc_set_single_buf(host,
2238                                                 XFER_RECEIVE, PDC_SECOND_BUF);
2239                                 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2240                         }
2241                 }
2242
2243                 /*
2244                  * First mci IPs, so mainly the ones having pdc, have some
2245                  * issues with the notbusy signal. You can't get it after
2246                  * data transmission if you have not sent a stop command.
2247                  * The appropriate workaround is to use the BLKE signal.
2248                  */
2249                 if (pending & ATMCI_BLKE) {
2250                         dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2251                         atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2252                         smp_wmb();
2253                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2254                         atmci_set_pending(host, EVENT_NOTBUSY);
2255                         tasklet_schedule(&host->tasklet);
2256                 }
2257
2258                 if (pending & ATMCI_NOTBUSY) {
2259                         dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2260                         atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2261                         smp_wmb();
2262                         dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2263                         atmci_set_pending(host, EVENT_NOTBUSY);
2264                         tasklet_schedule(&host->tasklet);
2265                 }
2266
2267                 if (pending & ATMCI_RXRDY)
2268                         atmci_read_data_pio(host);
2269                 if (pending & ATMCI_TXRDY)
2270                         atmci_write_data_pio(host);
2271
2272                 if (pending & ATMCI_CMDRDY) {
2273                         dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2274                         atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2275                         host->cmd_status = status;
2276                         smp_wmb();
2277                         dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2278                         atmci_set_pending(host, EVENT_CMD_RDY);
2279                         tasklet_schedule(&host->tasklet);
2280                 }
2281
2282                 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2283                         atmci_sdio_interrupt(host, status);
2284
2285         } while (pass_count++ < 5);
2286
2287         return pass_count ? IRQ_HANDLED : IRQ_NONE;
2288 }
2289
2290 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2291 {
2292         struct atmel_mci_slot   *slot = dev_id;
2293
2294         /*
2295          * Disable interrupts until the pin has stabilized and check
2296          * the state then. Use mod_timer() since we may be in the
2297          * middle of the timer routine when this interrupt triggers.
2298          */
2299         disable_irq_nosync(irq);
2300         mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2301
2302         return IRQ_HANDLED;
2303 }
2304
2305 static int atmci_init_slot(struct atmel_mci *host,
2306                 struct mci_slot_pdata *slot_data, unsigned int id,
2307                 u32 sdc_reg, u32 sdio_irq)
2308 {
2309         struct mmc_host                 *mmc;
2310         struct atmel_mci_slot           *slot;
2311
2312         mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2313         if (!mmc)
2314                 return -ENOMEM;
2315
2316         slot = mmc_priv(mmc);
2317         slot->mmc = mmc;
2318         slot->host = host;
2319         slot->detect_pin = slot_data->detect_pin;
2320         slot->wp_pin = slot_data->wp_pin;
2321         slot->detect_is_active_high = slot_data->detect_is_active_high;
2322         slot->sdc_reg = sdc_reg;
2323         slot->sdio_irq = sdio_irq;
2324
2325         dev_dbg(&mmc->class_dev,
2326                 "slot[%u]: bus_width=%u, detect_pin=%d, "
2327                 "detect_is_active_high=%s, wp_pin=%d\n",
2328                 id, slot_data->bus_width, slot_data->detect_pin,
2329                 slot_data->detect_is_active_high ? "true" : "false",
2330                 slot_data->wp_pin);
2331
2332         mmc->ops = &atmci_ops;
2333         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2334         mmc->f_max = host->bus_hz / 2;
2335         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
2336         if (sdio_irq)
2337                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2338         if (host->caps.has_highspeed)
2339                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2340         /*
2341          * Without the read/write proof capability, it is strongly suggested to
2342          * use only one bit for data to prevent fifo underruns and overruns
2343          * which will corrupt data.
2344          */
2345         if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2346                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2347
2348         if (atmci_get_version(host) < 0x200) {
2349                 mmc->max_segs = 256;
2350                 mmc->max_blk_size = 4095;
2351                 mmc->max_blk_count = 256;
2352                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2353                 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2354         } else {
2355                 mmc->max_segs = 64;
2356                 mmc->max_req_size = 32768 * 512;
2357                 mmc->max_blk_size = 32768;
2358                 mmc->max_blk_count = 512;
2359         }
2360
2361         /* Assume card is present initially */
2362         set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2363         if (gpio_is_valid(slot->detect_pin)) {
2364                 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2365                                       "mmc_detect")) {
2366                         dev_dbg(&mmc->class_dev, "no detect pin available\n");
2367                         slot->detect_pin = -EBUSY;
2368                 } else if (gpio_get_value(slot->detect_pin) ^
2369                                 slot->detect_is_active_high) {
2370                         clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2371                 }
2372         }
2373
2374         if (!gpio_is_valid(slot->detect_pin)) {
2375                 if (slot_data->non_removable)
2376                         mmc->caps |= MMC_CAP_NONREMOVABLE;
2377                 else
2378                         mmc->caps |= MMC_CAP_NEEDS_POLL;
2379         }
2380
2381         if (gpio_is_valid(slot->wp_pin)) {
2382                 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2383                                       "mmc_wp")) {
2384                         dev_dbg(&mmc->class_dev, "no WP pin available\n");
2385                         slot->wp_pin = -EBUSY;
2386                 }
2387         }
2388
2389         host->slot[id] = slot;
2390         mmc_regulator_get_supply(mmc);
2391         mmc_add_host(mmc);
2392
2393         if (gpio_is_valid(slot->detect_pin)) {
2394                 int ret;
2395
2396                 setup_timer(&slot->detect_timer, atmci_detect_change,
2397                                 (unsigned long)slot);
2398
2399                 ret = request_irq(gpio_to_irq(slot->detect_pin),
2400                                 atmci_detect_interrupt,
2401                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2402                                 "mmc-detect", slot);
2403                 if (ret) {
2404                         dev_dbg(&mmc->class_dev,
2405                                 "could not request IRQ %d for detect pin\n",
2406                                 gpio_to_irq(slot->detect_pin));
2407                         slot->detect_pin = -EBUSY;
2408                 }
2409         }
2410
2411         atmci_init_debugfs(slot);
2412
2413         return 0;
2414 }
2415
2416 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2417                 unsigned int id)
2418 {
2419         /* Debugfs stuff is cleaned up by mmc core */
2420
2421         set_bit(ATMCI_SHUTDOWN, &slot->flags);
2422         smp_wmb();
2423
2424         mmc_remove_host(slot->mmc);
2425
2426         if (gpio_is_valid(slot->detect_pin)) {
2427                 int pin = slot->detect_pin;
2428
2429                 free_irq(gpio_to_irq(pin), slot);
2430                 del_timer_sync(&slot->detect_timer);
2431         }
2432
2433         slot->host->slot[id] = NULL;
2434         mmc_free_host(slot->mmc);
2435 }
2436
2437 static int atmci_configure_dma(struct atmel_mci *host)
2438 {
2439         host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2440                                                         "rxtx");
2441
2442         if (PTR_ERR(host->dma.chan) == -ENODEV) {
2443                 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2444                 dma_cap_mask_t mask;
2445
2446                 if (!pdata->dma_filter)
2447                         return -ENODEV;
2448
2449                 dma_cap_zero(mask);
2450                 dma_cap_set(DMA_SLAVE, mask);
2451
2452                 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2453                                                      pdata->dma_slave);
2454                 if (!host->dma.chan)
2455                         host->dma.chan = ERR_PTR(-ENODEV);
2456         }
2457
2458         if (IS_ERR(host->dma.chan))
2459                 return PTR_ERR(host->dma.chan);
2460
2461         dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2462                  dma_chan_name(host->dma.chan));
2463
2464         host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2465         host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2466         host->dma_conf.src_maxburst = 1;
2467         host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2468         host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2469         host->dma_conf.dst_maxburst = 1;
2470         host->dma_conf.device_fc = false;
2471
2472         return 0;
2473 }
2474
2475 /*
2476  * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2477  * HSMCI provides DMA support and a new config register but no more supports
2478  * PDC.
2479  */
2480 static void atmci_get_cap(struct atmel_mci *host)
2481 {
2482         unsigned int version;
2483
2484         version = atmci_get_version(host);
2485         dev_info(&host->pdev->dev,
2486                         "version: 0x%x\n", version);
2487
2488         host->caps.has_dma_conf_reg = 0;
2489         host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2490         host->caps.has_cfg_reg = 0;
2491         host->caps.has_cstor_reg = 0;
2492         host->caps.has_highspeed = 0;
2493         host->caps.has_rwproof = 0;
2494         host->caps.has_odd_clk_div = 0;
2495         host->caps.has_bad_data_ordering = 1;
2496         host->caps.need_reset_after_xfer = 1;
2497         host->caps.need_blksz_mul_4 = 1;
2498         host->caps.need_notbusy_for_read_ops = 0;
2499
2500         /* keep only major version number */
2501         switch (version & 0xf00) {
2502         case 0x600:
2503         case 0x500:
2504                 host->caps.has_odd_clk_div = 1;
2505         case 0x400:
2506         case 0x300:
2507                 host->caps.has_dma_conf_reg = 1;
2508                 host->caps.has_pdc = 0;
2509                 host->caps.has_cfg_reg = 1;
2510                 host->caps.has_cstor_reg = 1;
2511                 host->caps.has_highspeed = 1;
2512         case 0x200:
2513                 host->caps.has_rwproof = 1;
2514                 host->caps.need_blksz_mul_4 = 0;
2515                 host->caps.need_notbusy_for_read_ops = 1;
2516         case 0x100:
2517                 host->caps.has_bad_data_ordering = 0;
2518                 host->caps.need_reset_after_xfer = 0;
2519         case 0x0:
2520                 break;
2521         default:
2522                 host->caps.has_pdc = 0;
2523                 dev_warn(&host->pdev->dev,
2524                                 "Unmanaged mci version, set minimum capabilities\n");
2525                 break;
2526         }
2527 }
2528
2529 static int atmci_probe(struct platform_device *pdev)
2530 {
2531         struct mci_platform_data        *pdata;
2532         struct atmel_mci                *host;
2533         struct resource                 *regs;
2534         unsigned int                    nr_slots;
2535         int                             irq;
2536         int                             ret, i;
2537
2538         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2539         if (!regs)
2540                 return -ENXIO;
2541         pdata = pdev->dev.platform_data;
2542         if (!pdata) {
2543                 pdata = atmci_of_init(pdev);
2544                 if (IS_ERR(pdata)) {
2545                         dev_err(&pdev->dev, "platform data not available\n");
2546                         return PTR_ERR(pdata);
2547                 }
2548         }
2549
2550         irq = platform_get_irq(pdev, 0);
2551         if (irq < 0)
2552                 return irq;
2553
2554         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2555         if (!host)
2556                 return -ENOMEM;
2557
2558         host->pdev = pdev;
2559         spin_lock_init(&host->lock);
2560         INIT_LIST_HEAD(&host->queue);
2561
2562         host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2563         if (IS_ERR(host->mck))
2564                 return PTR_ERR(host->mck);
2565
2566         host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2567         if (!host->regs)
2568                 return -ENOMEM;
2569
2570         ret = clk_prepare_enable(host->mck);
2571         if (ret)
2572                 return ret;
2573
2574         atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2575         host->bus_hz = clk_get_rate(host->mck);
2576
2577         host->mapbase = regs->start;
2578
2579         tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2580
2581         ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2582         if (ret) {
2583                 clk_disable_unprepare(host->mck);
2584                 return ret;
2585         }
2586
2587         /* Get MCI capabilities and set operations according to it */
2588         atmci_get_cap(host);
2589         ret = atmci_configure_dma(host);
2590         if (ret == -EPROBE_DEFER)
2591                 goto err_dma_probe_defer;
2592         if (ret == 0) {
2593                 host->prepare_data = &atmci_prepare_data_dma;
2594                 host->submit_data = &atmci_submit_data_dma;
2595                 host->stop_transfer = &atmci_stop_transfer_dma;
2596         } else if (host->caps.has_pdc) {
2597                 dev_info(&pdev->dev, "using PDC\n");
2598                 host->prepare_data = &atmci_prepare_data_pdc;
2599                 host->submit_data = &atmci_submit_data_pdc;
2600                 host->stop_transfer = &atmci_stop_transfer_pdc;
2601         } else {
2602                 dev_info(&pdev->dev, "using PIO\n");
2603                 host->prepare_data = &atmci_prepare_data;
2604                 host->submit_data = &atmci_submit_data;
2605                 host->stop_transfer = &atmci_stop_transfer;
2606         }
2607
2608         platform_set_drvdata(pdev, host);
2609
2610         setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2611
2612         pm_runtime_get_noresume(&pdev->dev);
2613         pm_runtime_set_active(&pdev->dev);
2614         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2615         pm_runtime_use_autosuspend(&pdev->dev);
2616         pm_runtime_enable(&pdev->dev);
2617
2618         /* We need at least one slot to succeed */
2619         nr_slots = 0;
2620         ret = -ENODEV;
2621         if (pdata->slot[0].bus_width) {
2622                 ret = atmci_init_slot(host, &pdata->slot[0],
2623                                 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2624                 if (!ret) {
2625                         nr_slots++;
2626                         host->buf_size = host->slot[0]->mmc->max_req_size;
2627                 }
2628         }
2629         if (pdata->slot[1].bus_width) {
2630                 ret = atmci_init_slot(host, &pdata->slot[1],
2631                                 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2632                 if (!ret) {
2633                         nr_slots++;
2634                         if (host->slot[1]->mmc->max_req_size > host->buf_size)
2635                                 host->buf_size =
2636                                         host->slot[1]->mmc->max_req_size;
2637                 }
2638         }
2639
2640         if (!nr_slots) {
2641                 dev_err(&pdev->dev, "init failed: no slot defined\n");
2642                 goto err_init_slot;
2643         }
2644
2645         if (!host->caps.has_rwproof) {
2646                 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2647                                                   &host->buf_phys_addr,
2648                                                   GFP_KERNEL);
2649                 if (!host->buffer) {
2650                         ret = -ENOMEM;
2651                         dev_err(&pdev->dev, "buffer allocation failed\n");
2652                         goto err_dma_alloc;
2653                 }
2654         }
2655
2656         dev_info(&pdev->dev,
2657                         "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2658                         host->mapbase, irq, nr_slots);
2659
2660         pm_runtime_mark_last_busy(&host->pdev->dev);
2661         pm_runtime_put_autosuspend(&pdev->dev);
2662
2663         return 0;
2664
2665 err_dma_alloc:
2666         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2667                 if (host->slot[i])
2668                         atmci_cleanup_slot(host->slot[i], i);
2669         }
2670 err_init_slot:
2671         clk_disable_unprepare(host->mck);
2672
2673         pm_runtime_disable(&pdev->dev);
2674         pm_runtime_put_noidle(&pdev->dev);
2675
2676         del_timer_sync(&host->timer);
2677         if (!IS_ERR(host->dma.chan))
2678                 dma_release_channel(host->dma.chan);
2679 err_dma_probe_defer:
2680         free_irq(irq, host);
2681         return ret;
2682 }
2683
2684 static int atmci_remove(struct platform_device *pdev)
2685 {
2686         struct atmel_mci        *host = platform_get_drvdata(pdev);
2687         unsigned int            i;
2688
2689         pm_runtime_get_sync(&pdev->dev);
2690
2691         if (host->buffer)
2692                 dma_free_coherent(&pdev->dev, host->buf_size,
2693                                   host->buffer, host->buf_phys_addr);
2694
2695         for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2696                 if (host->slot[i])
2697                         atmci_cleanup_slot(host->slot[i], i);
2698         }
2699
2700         atmci_writel(host, ATMCI_IDR, ~0UL);
2701         atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2702         atmci_readl(host, ATMCI_SR);
2703
2704         del_timer_sync(&host->timer);
2705         if (!IS_ERR(host->dma.chan))
2706                 dma_release_channel(host->dma.chan);
2707
2708         free_irq(platform_get_irq(pdev, 0), host);
2709
2710         clk_disable_unprepare(host->mck);
2711
2712         pm_runtime_disable(&pdev->dev);
2713         pm_runtime_put_noidle(&pdev->dev);
2714
2715         return 0;
2716 }
2717
2718 #ifdef CONFIG_PM
2719 static int atmci_runtime_suspend(struct device *dev)
2720 {
2721         struct atmel_mci *host = dev_get_drvdata(dev);
2722
2723         clk_disable_unprepare(host->mck);
2724
2725         pinctrl_pm_select_sleep_state(dev);
2726
2727         return 0;
2728 }
2729
2730 static int atmci_runtime_resume(struct device *dev)
2731 {
2732         struct atmel_mci *host = dev_get_drvdata(dev);
2733
2734         pinctrl_pm_select_default_state(dev);
2735
2736         return clk_prepare_enable(host->mck);
2737 }
2738 #endif
2739
2740 static const struct dev_pm_ops atmci_dev_pm_ops = {
2741         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2742                                 pm_runtime_force_resume)
2743         SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2744 };
2745
2746 static struct platform_driver atmci_driver = {
2747         .probe          = atmci_probe,
2748         .remove         = atmci_remove,
2749         .driver         = {
2750                 .name           = "atmel_mci",
2751                 .of_match_table = of_match_ptr(atmci_dt_ids),
2752                 .pm             = &atmci_dev_pm_ops,
2753         },
2754 };
2755 module_platform_driver(atmci_driver);
2756
2757 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2758 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2759 MODULE_LICENSE("GPL v2");