2 * Atmel MultiMedia Card Interface driver
4 * Copyright (C) 2004-2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/types.h>
31 #include <linux/platform_data/atmel.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/sdio.h>
36 #include <mach/atmel-mci.h>
37 #include <linux/atmel-mci.h>
38 #include <linux/atmel_pdc.h>
41 #include <asm/unaligned.h>
43 #include "atmel-mci-regs.h"
45 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
46 #define ATMCI_DMA_THRESHOLD 16
55 enum atmel_mci_state {
59 STATE_WAITING_NOTBUSY,
74 struct atmel_mci_caps {
75 bool has_dma_conf_reg;
82 bool has_bad_data_ordering;
83 bool need_reset_after_xfer;
84 bool need_blksz_mul_4;
85 bool need_notbusy_for_read_ops;
88 struct atmel_mci_dma {
89 struct dma_chan *chan;
90 struct dma_async_tx_descriptor *data_desc;
94 * struct atmel_mci - MMC controller state shared between all slots
95 * @lock: Spinlock protecting the queue and associated data.
96 * @regs: Pointer to MMIO registers.
97 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
98 * @pio_offset: Offset into the current scatterlist entry.
99 * @buffer: Buffer used if we don't have the r/w proof capability. We
100 * don't have the time to switch pdc buffers so we have to use only
101 * one buffer for the full transaction.
102 * @buf_size: size of the buffer.
103 * @phys_buf_addr: buffer address needed for pdc.
104 * @cur_slot: The slot which is currently using the controller.
105 * @mrq: The request currently being processed on @cur_slot,
106 * or NULL if the controller is idle.
107 * @cmd: The command currently being sent to the card, or NULL.
108 * @data: The data currently being transferred, or NULL if no data
109 * transfer is in progress.
110 * @data_size: just data->blocks * data->blksz.
111 * @dma: DMA client state.
112 * @data_chan: DMA channel being used for the current data transfer.
113 * @cmd_status: Snapshot of SR taken upon completion of the current
114 * command. Only valid when EVENT_CMD_COMPLETE is pending.
115 * @data_status: Snapshot of SR taken upon completion of the current
116 * data transfer. Only valid when EVENT_DATA_COMPLETE or
117 * EVENT_DATA_ERROR is pending.
118 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
120 * @tasklet: Tasklet running the request state machine.
121 * @pending_events: Bitmask of events flagged by the interrupt handler
122 * to be processed by the tasklet.
123 * @completed_events: Bitmask of events which the state machine has
125 * @state: Tasklet state.
126 * @queue: List of slots waiting for access to the controller.
127 * @need_clock_update: Update the clock rate before the next request.
128 * @need_reset: Reset controller before next request.
129 * @timer: Timer to balance the data timeout error flag which cannot rise.
130 * @mode_reg: Value of the MR register.
131 * @cfg_reg: Value of the CFG register.
132 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
133 * rate and timeout calculations.
134 * @mapbase: Physical address of the MMIO registers.
135 * @mck: The peripheral bus clock hooked up to the MMC controller.
136 * @pdev: Platform device associated with the MMC controller.
137 * @slot: Slots sharing this MMC controller.
138 * @caps: MCI capabilities depending on MCI version.
139 * @prepare_data: function to setup MCI before data transfer which
140 * depends on MCI capabilities.
141 * @submit_data: function to start data transfer which depends on MCI
143 * @stop_transfer: function to stop data transfer which depends on MCI
149 * @lock is a softirq-safe spinlock protecting @queue as well as
150 * @cur_slot, @mrq and @state. These must always be updated
151 * at the same time while holding @lock.
153 * @lock also protects mode_reg and need_clock_update since these are
154 * used to synchronize mode register updates with the queue
157 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
158 * and must always be written at the same time as the slot is added to
161 * @pending_events and @completed_events are accessed using atomic bit
162 * operations, so they don't need any locking.
164 * None of the fields touched by the interrupt handler need any
165 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
166 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
167 * interrupts must be disabled and @data_status updated with a
168 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
169 * CMDRDY interrupt must be disabled and @cmd_status updated with a
170 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
171 * bytes_xfered field of @data must be written. This is ensured by
178 struct scatterlist *sg;
180 unsigned int pio_offset;
181 unsigned int *buffer;
182 unsigned int buf_size;
183 dma_addr_t buf_phys_addr;
185 struct atmel_mci_slot *cur_slot;
186 struct mmc_request *mrq;
187 struct mmc_command *cmd;
188 struct mmc_data *data;
189 unsigned int data_size;
191 struct atmel_mci_dma dma;
192 struct dma_chan *data_chan;
193 struct dma_slave_config dma_conf;
199 struct tasklet_struct tasklet;
200 unsigned long pending_events;
201 unsigned long completed_events;
202 enum atmel_mci_state state;
203 struct list_head queue;
205 bool need_clock_update;
207 struct timer_list timer;
210 unsigned long bus_hz;
211 unsigned long mapbase;
213 struct platform_device *pdev;
215 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
217 struct atmel_mci_caps caps;
219 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
220 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
221 void (*stop_transfer)(struct atmel_mci *host);
225 * struct atmel_mci_slot - MMC slot state
226 * @mmc: The mmc_host representing this slot.
227 * @host: The MMC controller this slot is using.
228 * @sdc_reg: Value of SDCR to be written before using this slot.
229 * @sdio_irq: SDIO irq mask for this slot.
230 * @mrq: mmc_request currently being processed or waiting to be
231 * processed, or NULL when the slot is idle.
232 * @queue_node: List node for placing this node in the @queue list of
234 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
235 * @flags: Random state bits associated with the slot.
236 * @detect_pin: GPIO pin used for card detection, or negative if not
238 * @wp_pin: GPIO pin used for card write protect sending, or negative
240 * @detect_is_active_high: The state of the detect pin when it is active.
241 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
243 struct atmel_mci_slot {
244 struct mmc_host *mmc;
245 struct atmel_mci *host;
250 struct mmc_request *mrq;
251 struct list_head queue_node;
255 #define ATMCI_CARD_PRESENT 0
256 #define ATMCI_CARD_NEED_INIT 1
257 #define ATMCI_SHUTDOWN 2
258 #define ATMCI_SUSPENDED 3
262 bool detect_is_active_high;
264 struct timer_list detect_timer;
267 #define atmci_test_and_clear_pending(host, event) \
268 test_and_clear_bit(event, &host->pending_events)
269 #define atmci_set_completed(host, event) \
270 set_bit(event, &host->completed_events)
271 #define atmci_set_pending(host, event) \
272 set_bit(event, &host->pending_events)
275 * The debugfs stuff below is mostly optimized away when
276 * CONFIG_DEBUG_FS is not set.
278 static int atmci_req_show(struct seq_file *s, void *v)
280 struct atmel_mci_slot *slot = s->private;
281 struct mmc_request *mrq;
282 struct mmc_command *cmd;
283 struct mmc_command *stop;
284 struct mmc_data *data;
286 /* Make sure we get a consistent snapshot */
287 spin_lock_bh(&slot->host->lock);
297 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
298 cmd->opcode, cmd->arg, cmd->flags,
299 cmd->resp[0], cmd->resp[1], cmd->resp[2],
300 cmd->resp[3], cmd->error);
302 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
303 data->bytes_xfered, data->blocks,
304 data->blksz, data->flags, data->error);
307 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
308 stop->opcode, stop->arg, stop->flags,
309 stop->resp[0], stop->resp[1], stop->resp[2],
310 stop->resp[3], stop->error);
313 spin_unlock_bh(&slot->host->lock);
318 static int atmci_req_open(struct inode *inode, struct file *file)
320 return single_open(file, atmci_req_show, inode->i_private);
323 static const struct file_operations atmci_req_fops = {
324 .owner = THIS_MODULE,
325 .open = atmci_req_open,
328 .release = single_release,
331 static void atmci_show_status_reg(struct seq_file *s,
332 const char *regname, u32 value)
334 static const char *sr_bit[] = {
365 seq_printf(s, "%s:\t0x%08x", regname, value);
366 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
367 if (value & (1 << i)) {
369 seq_printf(s, " %s", sr_bit[i]);
371 seq_puts(s, " UNKNOWN");
377 static int atmci_regs_show(struct seq_file *s, void *v)
379 struct atmel_mci *host = s->private;
382 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
387 * Grab a more or less consistent snapshot. Note that we're
388 * not disabling interrupts, so IMR and SR may not be
391 spin_lock_bh(&host->lock);
392 clk_enable(host->mck);
393 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
394 clk_disable(host->mck);
395 spin_unlock_bh(&host->lock);
397 seq_printf(s, "MR:\t0x%08x%s%s ",
399 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
400 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
401 if (host->caps.has_odd_clk_div)
402 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
403 ((buf[ATMCI_MR / 4] & 0xff) << 1)
404 | ((buf[ATMCI_MR / 4] >> 16) & 1));
406 seq_printf(s, "CLKDIV=%u\n",
407 (buf[ATMCI_MR / 4] & 0xff));
408 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
409 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
410 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
411 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
413 buf[ATMCI_BLKR / 4] & 0xffff,
414 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
415 if (host->caps.has_cstor_reg)
416 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
418 /* Don't read RSPR and RDR; it will consume the data there */
420 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
421 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
423 if (host->caps.has_dma_conf_reg) {
426 val = buf[ATMCI_DMA / 4];
427 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
430 1 << (((val >> 4) & 3) + 1) : 1,
431 val & ATMCI_DMAEN ? " DMAEN" : "");
433 if (host->caps.has_cfg_reg) {
436 val = buf[ATMCI_CFG / 4];
437 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
439 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
440 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
441 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
442 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
450 static int atmci_regs_open(struct inode *inode, struct file *file)
452 return single_open(file, atmci_regs_show, inode->i_private);
455 static const struct file_operations atmci_regs_fops = {
456 .owner = THIS_MODULE,
457 .open = atmci_regs_open,
460 .release = single_release,
463 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
465 struct mmc_host *mmc = slot->mmc;
466 struct atmel_mci *host = slot->host;
470 root = mmc->debugfs_root;
474 node = debugfs_create_file("regs", S_IRUSR, root, host,
481 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
485 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
489 node = debugfs_create_x32("pending_events", S_IRUSR, root,
490 (u32 *)&host->pending_events);
494 node = debugfs_create_x32("completed_events", S_IRUSR, root,
495 (u32 *)&host->completed_events);
502 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
505 #if defined(CONFIG_OF)
506 static const struct of_device_id atmci_dt_ids[] = {
507 { .compatible = "atmel,hsmci" },
511 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
513 static struct mci_platform_data*
514 atmci_of_init(struct platform_device *pdev)
516 struct device_node *np = pdev->dev.of_node;
517 struct device_node *cnp;
518 struct mci_platform_data *pdata;
522 dev_err(&pdev->dev, "device node not found\n");
523 return ERR_PTR(-EINVAL);
526 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
528 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
529 return ERR_PTR(-ENOMEM);
532 for_each_child_of_node(np, cnp) {
533 if (of_property_read_u32(cnp, "reg", &slot_id)) {
534 dev_warn(&pdev->dev, "reg property is missing for %s\n",
539 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
540 dev_warn(&pdev->dev, "can't have more than %d slots\n",
545 if (of_property_read_u32(cnp, "bus-width",
546 &pdata->slot[slot_id].bus_width))
547 pdata->slot[slot_id].bus_width = 1;
549 pdata->slot[slot_id].detect_pin =
550 of_get_named_gpio(cnp, "cd-gpios", 0);
552 pdata->slot[slot_id].detect_is_active_high =
553 of_property_read_bool(cnp, "cd-inverted");
555 pdata->slot[slot_id].wp_pin =
556 of_get_named_gpio(cnp, "wp-gpios", 0);
561 #else /* CONFIG_OF */
562 static inline struct mci_platform_data*
563 atmci_of_init(struct platform_device *dev)
565 return ERR_PTR(-EINVAL);
569 static inline unsigned int atmci_get_version(struct atmel_mci *host)
571 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
574 static void atmci_timeout_timer(unsigned long data)
576 struct atmel_mci *host;
578 host = (struct atmel_mci *)data;
580 dev_dbg(&host->pdev->dev, "software timeout\n");
582 if (host->mrq->cmd->data) {
583 host->mrq->cmd->data->error = -ETIMEDOUT;
586 host->mrq->cmd->error = -ETIMEDOUT;
589 host->need_reset = 1;
590 host->state = STATE_END_REQUEST;
592 tasklet_schedule(&host->tasklet);
595 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
599 * It is easier here to use us instead of ns for the timeout,
600 * it prevents from overflows during calculation.
602 unsigned int us = DIV_ROUND_UP(ns, 1000);
604 /* Maximum clock frequency is host->bus_hz/2 */
605 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
608 static void atmci_set_timeout(struct atmel_mci *host,
609 struct atmel_mci_slot *slot, struct mmc_data *data)
611 static unsigned dtomul_to_shift[] = {
612 0, 4, 7, 8, 10, 12, 16, 20
618 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
619 + data->timeout_clks;
621 for (dtomul = 0; dtomul < 8; dtomul++) {
622 unsigned shift = dtomul_to_shift[dtomul];
623 dtocyc = (timeout + (1 << shift) - 1) >> shift;
633 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
634 dtocyc << dtomul_to_shift[dtomul]);
635 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
639 * Return mask with command flags to be enabled for this command.
641 static u32 atmci_prepare_command(struct mmc_host *mmc,
642 struct mmc_command *cmd)
644 struct mmc_data *data;
647 cmd->error = -EINPROGRESS;
649 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
651 if (cmd->flags & MMC_RSP_PRESENT) {
652 if (cmd->flags & MMC_RSP_136)
653 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
655 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
659 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
660 * it's too difficult to determine whether this is an ACMD or
661 * not. Better make it 64.
663 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
665 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
666 cmdr |= ATMCI_CMDR_OPDCMD;
670 cmdr |= ATMCI_CMDR_START_XFER;
672 if (cmd->opcode == SD_IO_RW_EXTENDED) {
673 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
675 if (data->flags & MMC_DATA_STREAM)
676 cmdr |= ATMCI_CMDR_STREAM;
677 else if (data->blocks > 1)
678 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
680 cmdr |= ATMCI_CMDR_BLOCK;
683 if (data->flags & MMC_DATA_READ)
684 cmdr |= ATMCI_CMDR_TRDIR_READ;
690 static void atmci_send_command(struct atmel_mci *host,
691 struct mmc_command *cmd, u32 cmd_flags)
696 dev_vdbg(&host->pdev->dev,
697 "start command: ARGR=0x%08x CMDR=0x%08x\n",
698 cmd->arg, cmd_flags);
700 atmci_writel(host, ATMCI_ARGR, cmd->arg);
701 atmci_writel(host, ATMCI_CMDR, cmd_flags);
704 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
706 dev_dbg(&host->pdev->dev, "send stop command\n");
707 atmci_send_command(host, data->stop, host->stop_cmdr);
708 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
712 * Configure given PDC buffer taking care of alignement issues.
713 * Update host->data_size and host->sg.
715 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
716 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
718 u32 pointer_reg, counter_reg;
719 unsigned int buf_size;
721 if (dir == XFER_RECEIVE) {
722 pointer_reg = ATMEL_PDC_RPR;
723 counter_reg = ATMEL_PDC_RCR;
725 pointer_reg = ATMEL_PDC_TPR;
726 counter_reg = ATMEL_PDC_TCR;
729 if (buf_nb == PDC_SECOND_BUF) {
730 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
731 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
734 if (!host->caps.has_rwproof) {
735 buf_size = host->buf_size;
736 atmci_writel(host, pointer_reg, host->buf_phys_addr);
738 buf_size = sg_dma_len(host->sg);
739 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
742 if (host->data_size <= buf_size) {
743 if (host->data_size & 0x3) {
744 /* If size is different from modulo 4, transfer bytes */
745 atmci_writel(host, counter_reg, host->data_size);
746 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
748 /* Else transfer 32-bits words */
749 atmci_writel(host, counter_reg, host->data_size / 4);
753 /* We assume the size of a page is 32-bits aligned */
754 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
755 host->data_size -= sg_dma_len(host->sg);
757 host->sg = sg_next(host->sg);
762 * Configure PDC buffer according to the data size ie configuring one or two
763 * buffers. Don't use this function if you want to configure only the second
764 * buffer. In this case, use atmci_pdc_set_single_buf.
766 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
768 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
770 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
774 * Unmap sg lists, called when transfer is finished.
776 static void atmci_pdc_cleanup(struct atmel_mci *host)
778 struct mmc_data *data = host->data;
781 dma_unmap_sg(&host->pdev->dev,
782 data->sg, data->sg_len,
783 ((data->flags & MMC_DATA_WRITE)
784 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
788 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
789 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
790 * interrupt needed for both transfer directions.
792 static void atmci_pdc_complete(struct atmel_mci *host)
794 int transfer_size = host->data->blocks * host->data->blksz;
797 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
799 if ((!host->caps.has_rwproof)
800 && (host->data->flags & MMC_DATA_READ)) {
801 if (host->caps.has_bad_data_ordering)
802 for (i = 0; i < transfer_size; i++)
803 host->buffer[i] = swab32(host->buffer[i]);
804 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
805 host->buffer, transfer_size);
808 atmci_pdc_cleanup(host);
811 * If the card was removed, data will be NULL. No point trying
812 * to send the stop command or waiting for NBUSY in this case.
815 dev_dbg(&host->pdev->dev,
816 "(%s) set pending xfer complete\n", __func__);
817 atmci_set_pending(host, EVENT_XFER_COMPLETE);
818 tasklet_schedule(&host->tasklet);
822 static void atmci_dma_cleanup(struct atmel_mci *host)
824 struct mmc_data *data = host->data;
827 dma_unmap_sg(host->dma.chan->device->dev,
828 data->sg, data->sg_len,
829 ((data->flags & MMC_DATA_WRITE)
830 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
834 * This function is called by the DMA driver from tasklet context.
836 static void atmci_dma_complete(void *arg)
838 struct atmel_mci *host = arg;
839 struct mmc_data *data = host->data;
841 dev_vdbg(&host->pdev->dev, "DMA complete\n");
843 if (host->caps.has_dma_conf_reg)
844 /* Disable DMA hardware handshaking on MCI */
845 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
847 atmci_dma_cleanup(host);
850 * If the card was removed, data will be NULL. No point trying
851 * to send the stop command or waiting for NBUSY in this case.
854 dev_dbg(&host->pdev->dev,
855 "(%s) set pending xfer complete\n", __func__);
856 atmci_set_pending(host, EVENT_XFER_COMPLETE);
857 tasklet_schedule(&host->tasklet);
860 * Regardless of what the documentation says, we have
861 * to wait for NOTBUSY even after block read
864 * When the DMA transfer is complete, the controller
865 * may still be reading the CRC from the card, i.e.
866 * the data transfer is still in progress and we
867 * haven't seen all the potential error bits yet.
869 * The interrupt handler will schedule a different
870 * tasklet to finish things up when the data transfer
871 * is completely done.
873 * We may not complete the mmc request here anyway
874 * because the mmc layer may call back and cause us to
875 * violate the "don't submit new operations from the
876 * completion callback" rule of the dma engine
879 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
884 * Returns a mask of interrupt flags to be enabled after the whole
885 * request has been prepared.
887 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
891 data->error = -EINPROGRESS;
894 host->sg_len = data->sg_len;
896 host->data_chan = NULL;
898 iflags = ATMCI_DATA_ERROR_FLAGS;
901 * Errata: MMC data write operation with less than 12
902 * bytes is impossible.
904 * Errata: MCI Transmit Data Register (TDR) FIFO
905 * corruption when length is not multiple of 4.
907 if (data->blocks * data->blksz < 12
908 || (data->blocks * data->blksz) & 3)
909 host->need_reset = true;
911 host->pio_offset = 0;
912 if (data->flags & MMC_DATA_READ)
913 iflags |= ATMCI_RXRDY;
915 iflags |= ATMCI_TXRDY;
921 * Set interrupt flags and set block length into the MCI mode register even
922 * if this value is also accessible in the MCI block register. It seems to be
923 * necessary before the High Speed MCI version. It also map sg and configure
927 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
931 enum dma_data_direction dir;
934 data->error = -EINPROGRESS;
938 iflags = ATMCI_DATA_ERROR_FLAGS;
940 /* Enable pdc mode */
941 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
943 if (data->flags & MMC_DATA_READ) {
944 dir = DMA_FROM_DEVICE;
945 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
948 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
952 tmp = atmci_readl(host, ATMCI_MR);
954 tmp |= ATMCI_BLKLEN(data->blksz);
955 atmci_writel(host, ATMCI_MR, tmp);
958 host->data_size = data->blocks * data->blksz;
959 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
961 if ((!host->caps.has_rwproof)
962 && (host->data->flags & MMC_DATA_WRITE)) {
963 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
964 host->buffer, host->data_size);
965 if (host->caps.has_bad_data_ordering)
966 for (i = 0; i < host->data_size; i++)
967 host->buffer[i] = swab32(host->buffer[i]);
971 atmci_pdc_set_both_buf(host,
972 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
978 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
980 struct dma_chan *chan;
981 struct dma_async_tx_descriptor *desc;
982 struct scatterlist *sg;
984 enum dma_data_direction direction;
985 enum dma_transfer_direction slave_dirn;
990 data->error = -EINPROGRESS;
996 iflags = ATMCI_DATA_ERROR_FLAGS;
999 * We don't do DMA on "complex" transfers, i.e. with
1000 * non-word-aligned buffers or lengths. Also, we don't bother
1001 * with all the DMA setup overhead for short transfers.
1003 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1004 return atmci_prepare_data(host, data);
1005 if (data->blksz & 3)
1006 return atmci_prepare_data(host, data);
1008 for_each_sg(data->sg, sg, data->sg_len, i) {
1009 if (sg->offset & 3 || sg->length & 3)
1010 return atmci_prepare_data(host, data);
1013 /* If we don't have a channel, we can't do DMA */
1014 chan = host->dma.chan;
1016 host->data_chan = chan;
1021 if (data->flags & MMC_DATA_READ) {
1022 direction = DMA_FROM_DEVICE;
1023 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1024 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1026 direction = DMA_TO_DEVICE;
1027 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1028 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1031 if (host->caps.has_dma_conf_reg)
1032 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1035 sglen = dma_map_sg(chan->device->dev, data->sg,
1036 data->sg_len, direction);
1038 dmaengine_slave_config(chan, &host->dma_conf);
1039 desc = dmaengine_prep_slave_sg(chan,
1040 data->sg, sglen, slave_dirn,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1045 host->dma.data_desc = desc;
1046 desc->callback = atmci_dma_complete;
1047 desc->callback_param = host;
1051 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1056 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1062 * Start PDC according to transfer direction.
1065 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1067 if (data->flags & MMC_DATA_READ)
1068 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1070 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1074 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1076 struct dma_chan *chan = host->data_chan;
1077 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1080 dmaengine_submit(desc);
1081 dma_async_issue_pending(chan);
1085 static void atmci_stop_transfer(struct atmel_mci *host)
1087 dev_dbg(&host->pdev->dev,
1088 "(%s) set pending xfer complete\n", __func__);
1089 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1090 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1094 * Stop data transfer because error(s) occurred.
1096 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1098 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1101 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1103 struct dma_chan *chan = host->data_chan;
1106 dmaengine_terminate_all(chan);
1107 atmci_dma_cleanup(host);
1109 /* Data transfer was stopped by the interrupt handler */
1110 dev_dbg(&host->pdev->dev,
1111 "(%s) set pending xfer complete\n", __func__);
1112 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1113 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1118 * Start a request: prepare data if needed, prepare the command and activate
1121 static void atmci_start_request(struct atmel_mci *host,
1122 struct atmel_mci_slot *slot)
1124 struct mmc_request *mrq;
1125 struct mmc_command *cmd;
1126 struct mmc_data *data;
1131 host->cur_slot = slot;
1134 host->pending_events = 0;
1135 host->completed_events = 0;
1136 host->cmd_status = 0;
1137 host->data_status = 0;
1139 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1141 if (host->need_reset || host->caps.need_reset_after_xfer) {
1142 iflags = atmci_readl(host, ATMCI_IMR);
1143 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1144 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1145 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1146 atmci_writel(host, ATMCI_MR, host->mode_reg);
1147 if (host->caps.has_cfg_reg)
1148 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1149 atmci_writel(host, ATMCI_IER, iflags);
1150 host->need_reset = false;
1152 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1154 iflags = atmci_readl(host, ATMCI_IMR);
1155 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1156 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1159 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1160 /* Send init sequence (74 clock cycles) */
1161 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1162 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1168 atmci_set_timeout(host, slot, data);
1170 /* Must set block count/size before sending command */
1171 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1172 | ATMCI_BLKLEN(data->blksz));
1173 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1174 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1176 iflags |= host->prepare_data(host, data);
1179 iflags |= ATMCI_CMDRDY;
1181 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1182 atmci_send_command(host, cmd, cmdflags);
1185 host->submit_data(host, data);
1188 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1189 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1190 if (!(data->flags & MMC_DATA_WRITE))
1191 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1192 if (data->flags & MMC_DATA_STREAM)
1193 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1195 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1199 * We could have enabled interrupts earlier, but I suspect
1200 * that would open up a nice can of interesting race
1201 * conditions (e.g. command and data complete, but stop not
1204 atmci_writel(host, ATMCI_IER, iflags);
1206 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1209 static void atmci_queue_request(struct atmel_mci *host,
1210 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1212 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1215 spin_lock_bh(&host->lock);
1217 if (host->state == STATE_IDLE) {
1218 host->state = STATE_SENDING_CMD;
1219 atmci_start_request(host, slot);
1221 dev_dbg(&host->pdev->dev, "queue request\n");
1222 list_add_tail(&slot->queue_node, &host->queue);
1224 spin_unlock_bh(&host->lock);
1227 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1229 struct atmel_mci_slot *slot = mmc_priv(mmc);
1230 struct atmel_mci *host = slot->host;
1231 struct mmc_data *data;
1234 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1237 * We may "know" the card is gone even though there's still an
1238 * electrical connection. If so, we really need to communicate
1239 * this to the MMC core since there won't be any more
1240 * interrupts as the card is completely removed. Otherwise,
1241 * the MMC core might believe the card is still there even
1242 * though the card was just removed very slowly.
1244 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1245 mrq->cmd->error = -ENOMEDIUM;
1246 mmc_request_done(mmc, mrq);
1250 /* We don't support multiple blocks of weird lengths. */
1252 if (data && data->blocks > 1 && data->blksz & 3) {
1253 mrq->cmd->error = -EINVAL;
1254 mmc_request_done(mmc, mrq);
1257 atmci_queue_request(host, slot, mrq);
1260 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1262 struct atmel_mci_slot *slot = mmc_priv(mmc);
1263 struct atmel_mci *host = slot->host;
1266 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1267 switch (ios->bus_width) {
1268 case MMC_BUS_WIDTH_1:
1269 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1271 case MMC_BUS_WIDTH_4:
1272 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1277 unsigned int clock_min = ~0U;
1280 spin_lock_bh(&host->lock);
1281 if (!host->mode_reg) {
1282 clk_enable(host->mck);
1283 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1284 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1285 if (host->caps.has_cfg_reg)
1286 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1290 * Use mirror of ios->clock to prevent race with mmc
1291 * core ios update when finding the minimum.
1293 slot->clock = ios->clock;
1294 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1295 if (host->slot[i] && host->slot[i]->clock
1296 && host->slot[i]->clock < clock_min)
1297 clock_min = host->slot[i]->clock;
1300 /* Calculate clock divider */
1301 if (host->caps.has_odd_clk_div) {
1302 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1304 dev_warn(&mmc->class_dev,
1305 "clock %u too slow; using %lu\n",
1306 clock_min, host->bus_hz / (511 + 2));
1309 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1310 | ATMCI_MR_CLKODD(clkdiv & 1);
1312 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1314 dev_warn(&mmc->class_dev,
1315 "clock %u too slow; using %lu\n",
1316 clock_min, host->bus_hz / (2 * 256));
1319 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1323 * WRPROOF and RDPROOF prevent overruns/underruns by
1324 * stopping the clock when the FIFO is full/empty.
1325 * This state is not expected to last for long.
1327 if (host->caps.has_rwproof)
1328 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1330 if (host->caps.has_cfg_reg) {
1331 /* setup High Speed mode in relation with card capacity */
1332 if (ios->timing == MMC_TIMING_SD_HS)
1333 host->cfg_reg |= ATMCI_CFG_HSMODE;
1335 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1338 if (list_empty(&host->queue)) {
1339 atmci_writel(host, ATMCI_MR, host->mode_reg);
1340 if (host->caps.has_cfg_reg)
1341 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1343 host->need_clock_update = true;
1346 spin_unlock_bh(&host->lock);
1348 bool any_slot_active = false;
1350 spin_lock_bh(&host->lock);
1352 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1353 if (host->slot[i] && host->slot[i]->clock) {
1354 any_slot_active = true;
1358 if (!any_slot_active) {
1359 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1360 if (host->mode_reg) {
1361 atmci_readl(host, ATMCI_MR);
1362 clk_disable(host->mck);
1366 spin_unlock_bh(&host->lock);
1369 switch (ios->power_mode) {
1371 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1375 * TODO: None of the currently available AVR32-based
1376 * boards allow MMC power to be turned off. Implement
1377 * power control when this can be tested properly.
1379 * We also need to hook this into the clock management
1380 * somehow so that newly inserted cards aren't
1381 * subjected to a fast clock before we have a chance
1382 * to figure out what the maximum rate is. Currently,
1383 * there's no way to avoid this, and there never will
1384 * be for boards that don't support power control.
1390 static int atmci_get_ro(struct mmc_host *mmc)
1392 int read_only = -ENOSYS;
1393 struct atmel_mci_slot *slot = mmc_priv(mmc);
1395 if (gpio_is_valid(slot->wp_pin)) {
1396 read_only = gpio_get_value(slot->wp_pin);
1397 dev_dbg(&mmc->class_dev, "card is %s\n",
1398 read_only ? "read-only" : "read-write");
1404 static int atmci_get_cd(struct mmc_host *mmc)
1406 int present = -ENOSYS;
1407 struct atmel_mci_slot *slot = mmc_priv(mmc);
1409 if (gpio_is_valid(slot->detect_pin)) {
1410 present = !(gpio_get_value(slot->detect_pin) ^
1411 slot->detect_is_active_high);
1412 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1413 present ? "" : "not ");
1419 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1421 struct atmel_mci_slot *slot = mmc_priv(mmc);
1422 struct atmel_mci *host = slot->host;
1425 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1427 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1430 static const struct mmc_host_ops atmci_ops = {
1431 .request = atmci_request,
1432 .set_ios = atmci_set_ios,
1433 .get_ro = atmci_get_ro,
1434 .get_cd = atmci_get_cd,
1435 .enable_sdio_irq = atmci_enable_sdio_irq,
1438 /* Called with host->lock held */
1439 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1440 __releases(&host->lock)
1441 __acquires(&host->lock)
1443 struct atmel_mci_slot *slot = NULL;
1444 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1446 WARN_ON(host->cmd || host->data);
1449 * Update the MMC clock rate if necessary. This may be
1450 * necessary if set_ios() is called when a different slot is
1451 * busy transferring data.
1453 if (host->need_clock_update) {
1454 atmci_writel(host, ATMCI_MR, host->mode_reg);
1455 if (host->caps.has_cfg_reg)
1456 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1459 host->cur_slot->mrq = NULL;
1461 if (!list_empty(&host->queue)) {
1462 slot = list_entry(host->queue.next,
1463 struct atmel_mci_slot, queue_node);
1464 list_del(&slot->queue_node);
1465 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1466 mmc_hostname(slot->mmc));
1467 host->state = STATE_SENDING_CMD;
1468 atmci_start_request(host, slot);
1470 dev_vdbg(&host->pdev->dev, "list empty\n");
1471 host->state = STATE_IDLE;
1474 del_timer(&host->timer);
1476 spin_unlock(&host->lock);
1477 mmc_request_done(prev_mmc, mrq);
1478 spin_lock(&host->lock);
1481 static void atmci_command_complete(struct atmel_mci *host,
1482 struct mmc_command *cmd)
1484 u32 status = host->cmd_status;
1486 /* Read the response from the card (up to 16 bytes) */
1487 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1488 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1489 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1490 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1492 if (status & ATMCI_RTOE)
1493 cmd->error = -ETIMEDOUT;
1494 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1495 cmd->error = -EILSEQ;
1496 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1498 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1499 if (host->caps.need_blksz_mul_4) {
1500 cmd->error = -EINVAL;
1501 host->need_reset = 1;
1507 static void atmci_detect_change(unsigned long data)
1509 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1514 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1515 * freeing the interrupt. We must not re-enable the interrupt
1516 * if it has been freed, and if we're shutting down, it
1517 * doesn't really matter whether the card is present or not.
1520 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1523 enable_irq(gpio_to_irq(slot->detect_pin));
1524 present = !(gpio_get_value(slot->detect_pin) ^
1525 slot->detect_is_active_high);
1526 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1528 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1529 present, present_old);
1531 if (present != present_old) {
1532 struct atmel_mci *host = slot->host;
1533 struct mmc_request *mrq;
1535 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1536 present ? "inserted" : "removed");
1538 spin_lock(&host->lock);
1541 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1543 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1545 /* Clean up queue if present */
1548 if (mrq == host->mrq) {
1550 * Reset controller to terminate any ongoing
1551 * commands or data transfers.
1553 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1554 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1555 atmci_writel(host, ATMCI_MR, host->mode_reg);
1556 if (host->caps.has_cfg_reg)
1557 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1562 switch (host->state) {
1565 case STATE_SENDING_CMD:
1566 mrq->cmd->error = -ENOMEDIUM;
1568 host->stop_transfer(host);
1570 case STATE_DATA_XFER:
1571 mrq->data->error = -ENOMEDIUM;
1572 host->stop_transfer(host);
1574 case STATE_WAITING_NOTBUSY:
1575 mrq->data->error = -ENOMEDIUM;
1577 case STATE_SENDING_STOP:
1578 mrq->stop->error = -ENOMEDIUM;
1580 case STATE_END_REQUEST:
1584 atmci_request_end(host, mrq);
1586 list_del(&slot->queue_node);
1587 mrq->cmd->error = -ENOMEDIUM;
1589 mrq->data->error = -ENOMEDIUM;
1591 mrq->stop->error = -ENOMEDIUM;
1593 spin_unlock(&host->lock);
1594 mmc_request_done(slot->mmc, mrq);
1595 spin_lock(&host->lock);
1598 spin_unlock(&host->lock);
1600 mmc_detect_change(slot->mmc, 0);
1604 static void atmci_tasklet_func(unsigned long priv)
1606 struct atmel_mci *host = (struct atmel_mci *)priv;
1607 struct mmc_request *mrq = host->mrq;
1608 struct mmc_data *data = host->data;
1609 enum atmel_mci_state state = host->state;
1610 enum atmel_mci_state prev_state;
1613 spin_lock(&host->lock);
1615 state = host->state;
1617 dev_vdbg(&host->pdev->dev,
1618 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1619 state, host->pending_events, host->completed_events,
1620 atmci_readl(host, ATMCI_IMR));
1624 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1630 case STATE_SENDING_CMD:
1632 * Command has been sent, we are waiting for command
1633 * ready. Then we have three next states possible:
1634 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1635 * command needing it or DATA_XFER if there is data.
1637 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1638 if (!atmci_test_and_clear_pending(host,
1642 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1644 atmci_set_completed(host, EVENT_CMD_RDY);
1645 atmci_command_complete(host, mrq->cmd);
1647 dev_dbg(&host->pdev->dev,
1648 "command with data transfer");
1650 * If there is a command error don't start
1653 if (mrq->cmd->error) {
1654 host->stop_transfer(host);
1656 atmci_writel(host, ATMCI_IDR,
1657 ATMCI_TXRDY | ATMCI_RXRDY
1658 | ATMCI_DATA_ERROR_FLAGS);
1659 state = STATE_END_REQUEST;
1661 state = STATE_DATA_XFER;
1662 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1663 dev_dbg(&host->pdev->dev,
1664 "command response need waiting notbusy");
1665 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1666 state = STATE_WAITING_NOTBUSY;
1668 state = STATE_END_REQUEST;
1672 case STATE_DATA_XFER:
1673 if (atmci_test_and_clear_pending(host,
1674 EVENT_DATA_ERROR)) {
1675 dev_dbg(&host->pdev->dev, "set completed data error\n");
1676 atmci_set_completed(host, EVENT_DATA_ERROR);
1677 state = STATE_END_REQUEST;
1682 * A data transfer is in progress. The event expected
1683 * to move to the next state depends of data transfer
1684 * type (PDC or DMA). Once transfer done we can move
1685 * to the next step which is WAITING_NOTBUSY in write
1686 * case and directly SENDING_STOP in read case.
1688 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1689 if (!atmci_test_and_clear_pending(host,
1690 EVENT_XFER_COMPLETE))
1693 dev_dbg(&host->pdev->dev,
1694 "(%s) set completed xfer complete\n",
1696 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1698 if (host->caps.need_notbusy_for_read_ops ||
1699 (host->data->flags & MMC_DATA_WRITE)) {
1700 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1701 state = STATE_WAITING_NOTBUSY;
1702 } else if (host->mrq->stop) {
1703 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1704 atmci_send_stop_cmd(host, data);
1705 state = STATE_SENDING_STOP;
1708 data->bytes_xfered = data->blocks * data->blksz;
1710 state = STATE_END_REQUEST;
1714 case STATE_WAITING_NOTBUSY:
1716 * We can be in the state for two reasons: a command
1717 * requiring waiting not busy signal (stop command
1718 * included) or a write operation. In the latest case,
1719 * we need to send a stop command.
1721 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1722 if (!atmci_test_and_clear_pending(host,
1726 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1727 atmci_set_completed(host, EVENT_NOTBUSY);
1731 * For some commands such as CMD53, even if
1732 * there is data transfer, there is no stop
1735 if (host->mrq->stop) {
1736 atmci_writel(host, ATMCI_IER,
1738 atmci_send_stop_cmd(host, data);
1739 state = STATE_SENDING_STOP;
1742 data->bytes_xfered = data->blocks
1745 state = STATE_END_REQUEST;
1748 state = STATE_END_REQUEST;
1751 case STATE_SENDING_STOP:
1753 * In this state, it is important to set host->data to
1754 * NULL (which is tested in the waiting notbusy state)
1755 * in order to go to the end request state instead of
1756 * sending stop again.
1758 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1759 if (!atmci_test_and_clear_pending(host,
1763 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1765 data->bytes_xfered = data->blocks * data->blksz;
1767 atmci_command_complete(host, mrq->stop);
1768 if (mrq->stop->error) {
1769 host->stop_transfer(host);
1770 atmci_writel(host, ATMCI_IDR,
1771 ATMCI_TXRDY | ATMCI_RXRDY
1772 | ATMCI_DATA_ERROR_FLAGS);
1773 state = STATE_END_REQUEST;
1775 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1776 state = STATE_WAITING_NOTBUSY;
1781 case STATE_END_REQUEST:
1782 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1783 | ATMCI_DATA_ERROR_FLAGS);
1784 status = host->data_status;
1785 if (unlikely(status)) {
1786 host->stop_transfer(host);
1788 if (status & ATMCI_DTOE) {
1789 data->error = -ETIMEDOUT;
1790 } else if (status & ATMCI_DCRCE) {
1791 data->error = -EILSEQ;
1797 atmci_request_end(host, host->mrq);
1801 } while (state != prev_state);
1803 host->state = state;
1805 spin_unlock(&host->lock);
1808 static void atmci_read_data_pio(struct atmel_mci *host)
1810 struct scatterlist *sg = host->sg;
1811 void *buf = sg_virt(sg);
1812 unsigned int offset = host->pio_offset;
1813 struct mmc_data *data = host->data;
1816 unsigned int nbytes = 0;
1819 value = atmci_readl(host, ATMCI_RDR);
1820 if (likely(offset + 4 <= sg->length)) {
1821 put_unaligned(value, (u32 *)(buf + offset));
1826 if (offset == sg->length) {
1827 flush_dcache_page(sg_page(sg));
1828 host->sg = sg = sg_next(sg);
1830 if (!sg || !host->sg_len)
1837 unsigned int remaining = sg->length - offset;
1838 memcpy(buf + offset, &value, remaining);
1839 nbytes += remaining;
1841 flush_dcache_page(sg_page(sg));
1842 host->sg = sg = sg_next(sg);
1844 if (!sg || !host->sg_len)
1847 offset = 4 - remaining;
1849 memcpy(buf, (u8 *)&value + remaining, offset);
1853 status = atmci_readl(host, ATMCI_SR);
1854 if (status & ATMCI_DATA_ERROR_FLAGS) {
1855 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1856 | ATMCI_DATA_ERROR_FLAGS));
1857 host->data_status = status;
1858 data->bytes_xfered += nbytes;
1861 } while (status & ATMCI_RXRDY);
1863 host->pio_offset = offset;
1864 data->bytes_xfered += nbytes;
1869 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1870 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1871 data->bytes_xfered += nbytes;
1873 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1876 static void atmci_write_data_pio(struct atmel_mci *host)
1878 struct scatterlist *sg = host->sg;
1879 void *buf = sg_virt(sg);
1880 unsigned int offset = host->pio_offset;
1881 struct mmc_data *data = host->data;
1884 unsigned int nbytes = 0;
1887 if (likely(offset + 4 <= sg->length)) {
1888 value = get_unaligned((u32 *)(buf + offset));
1889 atmci_writel(host, ATMCI_TDR, value);
1893 if (offset == sg->length) {
1894 host->sg = sg = sg_next(sg);
1896 if (!sg || !host->sg_len)
1903 unsigned int remaining = sg->length - offset;
1906 memcpy(&value, buf + offset, remaining);
1907 nbytes += remaining;
1909 host->sg = sg = sg_next(sg);
1911 if (!sg || !host->sg_len) {
1912 atmci_writel(host, ATMCI_TDR, value);
1916 offset = 4 - remaining;
1918 memcpy((u8 *)&value + remaining, buf, offset);
1919 atmci_writel(host, ATMCI_TDR, value);
1923 status = atmci_readl(host, ATMCI_SR);
1924 if (status & ATMCI_DATA_ERROR_FLAGS) {
1925 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1926 | ATMCI_DATA_ERROR_FLAGS));
1927 host->data_status = status;
1928 data->bytes_xfered += nbytes;
1931 } while (status & ATMCI_TXRDY);
1933 host->pio_offset = offset;
1934 data->bytes_xfered += nbytes;
1939 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1940 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1941 data->bytes_xfered += nbytes;
1943 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1946 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1950 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1951 struct atmel_mci_slot *slot = host->slot[i];
1952 if (slot && (status & slot->sdio_irq)) {
1953 mmc_signal_sdio_irq(slot->mmc);
1959 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1961 struct atmel_mci *host = dev_id;
1962 u32 status, mask, pending;
1963 unsigned int pass_count = 0;
1966 status = atmci_readl(host, ATMCI_SR);
1967 mask = atmci_readl(host, ATMCI_IMR);
1968 pending = status & mask;
1972 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1973 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
1974 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1975 | ATMCI_RXRDY | ATMCI_TXRDY
1976 | ATMCI_ENDRX | ATMCI_ENDTX
1977 | ATMCI_RXBUFF | ATMCI_TXBUFE);
1979 host->data_status = status;
1980 dev_dbg(&host->pdev->dev, "set pending data error\n");
1982 atmci_set_pending(host, EVENT_DATA_ERROR);
1983 tasklet_schedule(&host->tasklet);
1986 if (pending & ATMCI_TXBUFE) {
1987 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
1988 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1989 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1991 * We can receive this interruption before having configured
1992 * the second pdc buffer, so we need to reconfigure first and
1993 * second buffers again
1995 if (host->data_size) {
1996 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1997 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1998 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2000 atmci_pdc_complete(host);
2002 } else if (pending & ATMCI_ENDTX) {
2003 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2004 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2006 if (host->data_size) {
2007 atmci_pdc_set_single_buf(host,
2008 XFER_TRANSMIT, PDC_SECOND_BUF);
2009 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2013 if (pending & ATMCI_RXBUFF) {
2014 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2015 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2016 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2018 * We can receive this interruption before having configured
2019 * the second pdc buffer, so we need to reconfigure first and
2020 * second buffers again
2022 if (host->data_size) {
2023 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2024 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2025 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2027 atmci_pdc_complete(host);
2029 } else if (pending & ATMCI_ENDRX) {
2030 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2031 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2033 if (host->data_size) {
2034 atmci_pdc_set_single_buf(host,
2035 XFER_RECEIVE, PDC_SECOND_BUF);
2036 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2041 * First mci IPs, so mainly the ones having pdc, have some
2042 * issues with the notbusy signal. You can't get it after
2043 * data transmission if you have not sent a stop command.
2044 * The appropriate workaround is to use the BLKE signal.
2046 if (pending & ATMCI_BLKE) {
2047 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2048 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2050 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2051 atmci_set_pending(host, EVENT_NOTBUSY);
2052 tasklet_schedule(&host->tasklet);
2055 if (pending & ATMCI_NOTBUSY) {
2056 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2057 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2059 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2060 atmci_set_pending(host, EVENT_NOTBUSY);
2061 tasklet_schedule(&host->tasklet);
2064 if (pending & ATMCI_RXRDY)
2065 atmci_read_data_pio(host);
2066 if (pending & ATMCI_TXRDY)
2067 atmci_write_data_pio(host);
2069 if (pending & ATMCI_CMDRDY) {
2070 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2071 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2072 host->cmd_status = status;
2074 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2075 atmci_set_pending(host, EVENT_CMD_RDY);
2076 tasklet_schedule(&host->tasklet);
2079 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2080 atmci_sdio_interrupt(host, status);
2082 } while (pass_count++ < 5);
2084 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2087 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2089 struct atmel_mci_slot *slot = dev_id;
2092 * Disable interrupts until the pin has stabilized and check
2093 * the state then. Use mod_timer() since we may be in the
2094 * middle of the timer routine when this interrupt triggers.
2096 disable_irq_nosync(irq);
2097 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2102 static int __init atmci_init_slot(struct atmel_mci *host,
2103 struct mci_slot_pdata *slot_data, unsigned int id,
2104 u32 sdc_reg, u32 sdio_irq)
2106 struct mmc_host *mmc;
2107 struct atmel_mci_slot *slot;
2109 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2113 slot = mmc_priv(mmc);
2116 slot->detect_pin = slot_data->detect_pin;
2117 slot->wp_pin = slot_data->wp_pin;
2118 slot->detect_is_active_high = slot_data->detect_is_active_high;
2119 slot->sdc_reg = sdc_reg;
2120 slot->sdio_irq = sdio_irq;
2122 dev_dbg(&mmc->class_dev,
2123 "slot[%u]: bus_width=%u, detect_pin=%d, "
2124 "detect_is_active_high=%s, wp_pin=%d\n",
2125 id, slot_data->bus_width, slot_data->detect_pin,
2126 slot_data->detect_is_active_high ? "true" : "false",
2129 mmc->ops = &atmci_ops;
2130 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2131 mmc->f_max = host->bus_hz / 2;
2132 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2134 mmc->caps |= MMC_CAP_SDIO_IRQ;
2135 if (host->caps.has_highspeed)
2136 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2138 * Without the read/write proof capability, it is strongly suggested to
2139 * use only one bit for data to prevent fifo underruns and overruns
2140 * which will corrupt data.
2142 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2143 mmc->caps |= MMC_CAP_4_BIT_DATA;
2145 if (atmci_get_version(host) < 0x200) {
2146 mmc->max_segs = 256;
2147 mmc->max_blk_size = 4095;
2148 mmc->max_blk_count = 256;
2149 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2150 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2153 mmc->max_req_size = 32768 * 512;
2154 mmc->max_blk_size = 32768;
2155 mmc->max_blk_count = 512;
2158 /* Assume card is present initially */
2159 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2160 if (gpio_is_valid(slot->detect_pin)) {
2161 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2162 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2163 slot->detect_pin = -EBUSY;
2164 } else if (gpio_get_value(slot->detect_pin) ^
2165 slot->detect_is_active_high) {
2166 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2170 if (!gpio_is_valid(slot->detect_pin))
2171 mmc->caps |= MMC_CAP_NEEDS_POLL;
2173 if (gpio_is_valid(slot->wp_pin)) {
2174 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2175 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2176 slot->wp_pin = -EBUSY;
2180 host->slot[id] = slot;
2183 if (gpio_is_valid(slot->detect_pin)) {
2186 setup_timer(&slot->detect_timer, atmci_detect_change,
2187 (unsigned long)slot);
2189 ret = request_irq(gpio_to_irq(slot->detect_pin),
2190 atmci_detect_interrupt,
2191 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2192 "mmc-detect", slot);
2194 dev_dbg(&mmc->class_dev,
2195 "could not request IRQ %d for detect pin\n",
2196 gpio_to_irq(slot->detect_pin));
2197 gpio_free(slot->detect_pin);
2198 slot->detect_pin = -EBUSY;
2202 atmci_init_debugfs(slot);
2207 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2210 /* Debugfs stuff is cleaned up by mmc core */
2212 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2215 mmc_remove_host(slot->mmc);
2217 if (gpio_is_valid(slot->detect_pin)) {
2218 int pin = slot->detect_pin;
2220 free_irq(gpio_to_irq(pin), slot);
2221 del_timer_sync(&slot->detect_timer);
2224 if (gpio_is_valid(slot->wp_pin))
2225 gpio_free(slot->wp_pin);
2227 slot->host->slot[id] = NULL;
2228 mmc_free_host(slot->mmc);
2231 static bool atmci_filter(struct dma_chan *chan, void *pdata)
2233 struct mci_platform_data *sl_pdata = pdata;
2234 struct mci_dma_data *sl;
2239 sl = sl_pdata->dma_slave;
2240 if (sl && find_slave_dev(sl) == chan->device->dev) {
2241 chan->private = slave_data_ptr(sl);
2248 static bool atmci_configure_dma(struct atmel_mci *host)
2250 struct mci_platform_data *pdata;
2251 dma_cap_mask_t mask;
2256 pdata = host->pdev->dev.platform_data;
2259 dma_cap_set(DMA_SLAVE, mask);
2261 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2262 &host->pdev->dev, "rxtx");
2263 if (!host->dma.chan) {
2264 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2267 dev_info(&host->pdev->dev,
2268 "using %s for DMA transfers\n",
2269 dma_chan_name(host->dma.chan));
2271 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2272 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2273 host->dma_conf.src_maxburst = 1;
2274 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2275 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2276 host->dma_conf.dst_maxburst = 1;
2277 host->dma_conf.device_fc = false;
2283 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2284 * HSMCI provides DMA support and a new config register but no more supports
2287 static void __init atmci_get_cap(struct atmel_mci *host)
2289 unsigned int version;
2291 version = atmci_get_version(host);
2292 dev_info(&host->pdev->dev,
2293 "version: 0x%x\n", version);
2295 host->caps.has_dma_conf_reg = 0;
2296 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2297 host->caps.has_cfg_reg = 0;
2298 host->caps.has_cstor_reg = 0;
2299 host->caps.has_highspeed = 0;
2300 host->caps.has_rwproof = 0;
2301 host->caps.has_odd_clk_div = 0;
2302 host->caps.has_bad_data_ordering = 1;
2303 host->caps.need_reset_after_xfer = 1;
2304 host->caps.need_blksz_mul_4 = 1;
2305 host->caps.need_notbusy_for_read_ops = 0;
2307 /* keep only major version number */
2308 switch (version & 0xf00) {
2310 host->caps.has_odd_clk_div = 1;
2313 host->caps.has_dma_conf_reg = 1;
2314 host->caps.has_pdc = 0;
2315 host->caps.has_cfg_reg = 1;
2316 host->caps.has_cstor_reg = 1;
2317 host->caps.has_highspeed = 1;
2319 host->caps.has_rwproof = 1;
2320 host->caps.need_blksz_mul_4 = 0;
2321 host->caps.need_notbusy_for_read_ops = 1;
2323 host->caps.has_bad_data_ordering = 0;
2324 host->caps.need_reset_after_xfer = 0;
2328 host->caps.has_pdc = 0;
2329 dev_warn(&host->pdev->dev,
2330 "Unmanaged mci version, set minimum capabilities\n");
2335 static int __init atmci_probe(struct platform_device *pdev)
2337 struct mci_platform_data *pdata;
2338 struct atmel_mci *host;
2339 struct resource *regs;
2340 unsigned int nr_slots;
2344 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2347 pdata = pdev->dev.platform_data;
2349 pdata = atmci_of_init(pdev);
2350 if (IS_ERR(pdata)) {
2351 dev_err(&pdev->dev, "platform data not available\n");
2352 return PTR_ERR(pdata);
2356 irq = platform_get_irq(pdev, 0);
2360 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2365 spin_lock_init(&host->lock);
2366 INIT_LIST_HEAD(&host->queue);
2368 host->mck = clk_get(&pdev->dev, "mci_clk");
2369 if (IS_ERR(host->mck)) {
2370 ret = PTR_ERR(host->mck);
2375 host->regs = ioremap(regs->start, resource_size(regs));
2379 clk_enable(host->mck);
2380 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2381 host->bus_hz = clk_get_rate(host->mck);
2382 clk_disable(host->mck);
2384 host->mapbase = regs->start;
2386 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2388 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2390 goto err_request_irq;
2392 /* Get MCI capabilities and set operations according to it */
2393 atmci_get_cap(host);
2394 if (atmci_configure_dma(host)) {
2395 host->prepare_data = &atmci_prepare_data_dma;
2396 host->submit_data = &atmci_submit_data_dma;
2397 host->stop_transfer = &atmci_stop_transfer_dma;
2398 } else if (host->caps.has_pdc) {
2399 dev_info(&pdev->dev, "using PDC\n");
2400 host->prepare_data = &atmci_prepare_data_pdc;
2401 host->submit_data = &atmci_submit_data_pdc;
2402 host->stop_transfer = &atmci_stop_transfer_pdc;
2404 dev_info(&pdev->dev, "using PIO\n");
2405 host->prepare_data = &atmci_prepare_data;
2406 host->submit_data = &atmci_submit_data;
2407 host->stop_transfer = &atmci_stop_transfer;
2410 platform_set_drvdata(pdev, host);
2412 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2414 /* We need at least one slot to succeed */
2417 if (pdata->slot[0].bus_width) {
2418 ret = atmci_init_slot(host, &pdata->slot[0],
2419 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2422 host->buf_size = host->slot[0]->mmc->max_req_size;
2425 if (pdata->slot[1].bus_width) {
2426 ret = atmci_init_slot(host, &pdata->slot[1],
2427 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2430 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2432 host->slot[1]->mmc->max_req_size;
2437 dev_err(&pdev->dev, "init failed: no slot defined\n");
2441 if (!host->caps.has_rwproof) {
2442 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2443 &host->buf_phys_addr,
2445 if (!host->buffer) {
2447 dev_err(&pdev->dev, "buffer allocation failed\n");
2452 dev_info(&pdev->dev,
2453 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2454 host->mapbase, irq, nr_slots);
2460 dma_release_channel(host->dma.chan);
2461 free_irq(irq, host);
2463 iounmap(host->regs);
2471 static int __exit atmci_remove(struct platform_device *pdev)
2473 struct atmel_mci *host = platform_get_drvdata(pdev);
2477 dma_free_coherent(&pdev->dev, host->buf_size,
2478 host->buffer, host->buf_phys_addr);
2480 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2482 atmci_cleanup_slot(host->slot[i], i);
2485 clk_enable(host->mck);
2486 atmci_writel(host, ATMCI_IDR, ~0UL);
2487 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2488 atmci_readl(host, ATMCI_SR);
2489 clk_disable(host->mck);
2492 dma_release_channel(host->dma.chan);
2494 free_irq(platform_get_irq(pdev, 0), host);
2495 iounmap(host->regs);
2503 #ifdef CONFIG_PM_SLEEP
2504 static int atmci_suspend(struct device *dev)
2506 struct atmel_mci *host = dev_get_drvdata(dev);
2509 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2510 struct atmel_mci_slot *slot = host->slot[i];
2515 ret = mmc_suspend_host(slot->mmc);
2518 slot = host->slot[i];
2520 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2521 mmc_resume_host(host->slot[i]->mmc);
2522 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2527 set_bit(ATMCI_SUSPENDED, &slot->flags);
2534 static int atmci_resume(struct device *dev)
2536 struct atmel_mci *host = dev_get_drvdata(dev);
2540 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2541 struct atmel_mci_slot *slot = host->slot[i];
2544 slot = host->slot[i];
2547 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2549 err = mmc_resume_host(slot->mmc);
2553 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2560 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2562 static struct platform_driver atmci_driver = {
2563 .remove = __exit_p(atmci_remove),
2565 .name = "atmel_mci",
2567 .of_match_table = of_match_ptr(atmci_dt_ids),
2571 static int __init atmci_init(void)
2573 return platform_driver_probe(&atmci_driver, atmci_probe);
2576 static void __exit atmci_exit(void)
2578 platform_driver_unregister(&atmci_driver);
2581 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2582 module_exit(atmci_exit);
2584 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2585 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2586 MODULE_LICENSE("GPL v2");