2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why don't we use the SD controllers' carddetect feature?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/leds.h>
43 #include <linux/mmc/host.h>
44 #include <linux/slab.h>
47 #include <asm/mach-au1x00/au1000.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49 #include <asm/mach-au1x00/au1100_mmc.h>
51 #define DRIVER_NAME "au1xxx-mmc"
53 /* Set this to enable special debugging macros */
57 #define DBG(fmt, idx, args...) \
58 pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
60 #define DBG(fmt, idx, args...) do {} while (0)
63 /* Hardware definitions */
64 #define AU1XMMC_DESCRIPTOR_COUNT 1
66 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
67 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
68 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
70 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
71 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
72 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
74 /* This gives us a hard value for the stop command that we can write directly
75 * to the command register.
78 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
80 /* This is the set of interrupts that we configure by default. */
81 #define AU1XMMC_INTERRUPTS \
82 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
83 SD_CONFIG_CR | SD_CONFIG_I)
85 /* The poll event (looking for insert/remove events runs twice a second. */
86 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
90 struct mmc_request *mrq;
116 struct tasklet_struct finish_task;
117 struct tasklet_struct data_task;
118 struct au1xmmc_platform_data *platdata;
119 struct platform_device *pdev;
120 struct resource *ioarea;
123 /* Status flags used by the host structure */
124 #define HOST_F_XMIT 0x0001
125 #define HOST_F_RECV 0x0002
126 #define HOST_F_DMA 0x0010
127 #define HOST_F_DBDMA 0x0020
128 #define HOST_F_ACTIVE 0x0100
129 #define HOST_F_STOP 0x1000
131 #define HOST_S_IDLE 0x0001
132 #define HOST_S_CMD 0x0002
133 #define HOST_S_DATA 0x0003
134 #define HOST_S_STOP 0x0004
136 /* Easy access macros */
137 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
138 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
139 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
140 #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
141 #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
142 #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
143 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
144 #define HOST_CMD(h) ((h)->iobase + SD_CMD)
145 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
146 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
147 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
149 #define DMA_CHANNEL(h) \
150 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
152 static inline int has_dbdma(void)
154 switch (alchemy_get_cputype()) {
155 case ALCHEMY_CPU_AU1200:
156 case ALCHEMY_CPU_AU1300:
163 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
165 u32 val = au_readl(HOST_CONFIG(host));
167 au_writel(val, HOST_CONFIG(host));
171 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
173 u32 val = au_readl(HOST_CONFIG2(host));
175 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
178 /* SEND_STOP will turn off clock control - this re-enables it */
179 val &= ~SD_CONFIG2_DF;
181 au_writel(val, HOST_CONFIG2(host));
185 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
187 u32 val = au_readl(HOST_CONFIG(host));
189 au_writel(val, HOST_CONFIG(host));
193 static inline void SEND_STOP(struct au1xmmc_host *host)
197 WARN_ON(host->status != HOST_S_DATA);
198 host->status = HOST_S_STOP;
200 config2 = au_readl(HOST_CONFIG2(host));
201 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
204 /* Send the stop command */
205 au_writel(STOP_CMD, HOST_CMD(host));
208 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
210 if (host->platdata && host->platdata->set_power)
211 host->platdata->set_power(host->mmc, state);
214 static int au1xmmc_card_inserted(struct mmc_host *mmc)
216 struct au1xmmc_host *host = mmc_priv(mmc);
218 if (host->platdata && host->platdata->card_inserted)
219 return !!host->platdata->card_inserted(host->mmc);
224 static int au1xmmc_card_readonly(struct mmc_host *mmc)
226 struct au1xmmc_host *host = mmc_priv(mmc);
228 if (host->platdata && host->platdata->card_readonly)
229 return !!host->platdata->card_readonly(mmc);
234 static void au1xmmc_finish_request(struct au1xmmc_host *host)
236 struct mmc_request *mrq = host->mrq;
239 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
245 host->pio.offset = 0;
248 host->status = HOST_S_IDLE;
250 mmc_request_done(host->mmc, mrq);
253 static void au1xmmc_tasklet_finish(unsigned long param)
255 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
256 au1xmmc_finish_request(host);
259 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
260 struct mmc_command *cmd, struct mmc_data *data)
262 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
264 switch (mmc_resp_type(cmd)) {
268 mmccmd |= SD_CMD_RT_1;
271 mmccmd |= SD_CMD_RT_1B;
274 mmccmd |= SD_CMD_RT_2;
277 mmccmd |= SD_CMD_RT_3;
280 pr_info("au1xmmc: unhandled response type %02x\n",
286 if (data->flags & MMC_DATA_READ) {
287 if (data->blocks > 1)
288 mmccmd |= SD_CMD_CT_4;
290 mmccmd |= SD_CMD_CT_2;
291 } else if (data->flags & MMC_DATA_WRITE) {
292 if (data->blocks > 1)
293 mmccmd |= SD_CMD_CT_3;
295 mmccmd |= SD_CMD_CT_1;
299 au_writel(cmd->arg, HOST_CMDARG(host));
303 IRQ_OFF(host, SD_CONFIG_CR);
305 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
308 /* Wait for the command to go on the line */
309 while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
312 /* Wait for the command to come back */
314 u32 status = au_readl(HOST_STATUS(host));
316 while (!(status & SD_STATUS_CR))
317 status = au_readl(HOST_STATUS(host));
319 /* Clear the CR status */
320 au_writel(SD_STATUS_CR, HOST_STATUS(host));
322 IRQ_ON(host, SD_CONFIG_CR);
328 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
330 struct mmc_request *mrq = host->mrq;
331 struct mmc_data *data;
334 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
336 if (host->mrq == NULL)
339 data = mrq->cmd->data;
342 status = au_readl(HOST_STATUS(host));
344 /* The transaction is really over when the SD_STATUS_DB bit is clear */
345 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
346 status = au_readl(HOST_STATUS(host));
349 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
351 /* Process any errors */
352 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
353 if (host->flags & HOST_F_XMIT)
354 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
357 data->error = -EILSEQ;
359 /* Clear the CRC bits */
360 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
362 data->bytes_xfered = 0;
365 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
366 u32 chan = DMA_CHANNEL(host);
368 chan_tab_t *c = *((chan_tab_t **)chan);
369 au1x_dma_chan_t *cp = c->chan_ptr;
370 data->bytes_xfered = cp->ddma_bytecnt;
373 (data->blocks * data->blksz) - host->pio.len;
376 au1xmmc_finish_request(host);
379 static void au1xmmc_tasklet_data(unsigned long param)
381 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
383 u32 status = au_readl(HOST_STATUS(host));
384 au1xmmc_data_complete(host, status);
387 #define AU1XMMC_MAX_TRANSFER 8
389 static void au1xmmc_send_pio(struct au1xmmc_host *host)
391 struct mmc_data *data;
392 int sg_len, max, count;
393 unsigned char *sg_ptr, val;
395 struct scatterlist *sg;
397 data = host->mrq->data;
399 if (!(host->flags & HOST_F_XMIT))
402 /* This is the pointer to the data buffer */
403 sg = &data->sg[host->pio.index];
404 sg_ptr = sg_virt(sg) + host->pio.offset;
406 /* This is the space left inside the buffer */
407 sg_len = data->sg[host->pio.index].length - host->pio.offset;
409 /* Check if we need less than the size of the sg_buffer */
410 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
411 if (max > AU1XMMC_MAX_TRANSFER)
412 max = AU1XMMC_MAX_TRANSFER;
414 for (count = 0; count < max; count++) {
415 status = au_readl(HOST_STATUS(host));
417 if (!(status & SD_STATUS_TH))
422 au_writel((unsigned long)val, HOST_TXPORT(host));
426 host->pio.len -= count;
427 host->pio.offset += count;
429 if (count == sg_len) {
431 host->pio.offset = 0;
434 if (host->pio.len == 0) {
435 IRQ_OFF(host, SD_CONFIG_TH);
437 if (host->flags & HOST_F_STOP)
440 tasklet_schedule(&host->data_task);
444 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
446 struct mmc_data *data;
447 int max, count, sg_len = 0;
448 unsigned char *sg_ptr = NULL;
450 struct scatterlist *sg;
452 data = host->mrq->data;
454 if (!(host->flags & HOST_F_RECV))
459 if (host->pio.index < host->dma.len) {
460 sg = &data->sg[host->pio.index];
461 sg_ptr = sg_virt(sg) + host->pio.offset;
463 /* This is the space left inside the buffer */
464 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
466 /* Check if we need less than the size of the sg_buffer */
471 if (max > AU1XMMC_MAX_TRANSFER)
472 max = AU1XMMC_MAX_TRANSFER;
474 for (count = 0; count < max; count++) {
475 status = au_readl(HOST_STATUS(host));
477 if (!(status & SD_STATUS_NE))
480 if (status & SD_STATUS_RC) {
481 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
482 host->pio.len, count);
486 if (status & SD_STATUS_RO) {
487 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
488 host->pio.len, count);
491 else if (status & SD_STATUS_RU) {
492 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
493 host->pio.len, count);
497 val = au_readl(HOST_RXPORT(host));
500 *sg_ptr++ = (unsigned char)(val & 0xFF);
503 host->pio.len -= count;
504 host->pio.offset += count;
506 if (sg_len && count == sg_len) {
508 host->pio.offset = 0;
511 if (host->pio.len == 0) {
512 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
513 IRQ_OFF(host, SD_CONFIG_NE);
515 if (host->flags & HOST_F_STOP)
518 tasklet_schedule(&host->data_task);
522 /* This is called when a command has been completed - grab the response
523 * and check for errors. Then start the data transfer if it is indicated.
525 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
527 struct mmc_request *mrq = host->mrq;
528 struct mmc_command *cmd;
538 if (cmd->flags & MMC_RSP_PRESENT) {
539 if (cmd->flags & MMC_RSP_136) {
540 r[0] = au_readl(host->iobase + SD_RESP3);
541 r[1] = au_readl(host->iobase + SD_RESP2);
542 r[2] = au_readl(host->iobase + SD_RESP1);
543 r[3] = au_readl(host->iobase + SD_RESP0);
545 /* The CRC is omitted from the response, so really
546 * we only got 120 bytes, but the engine expects
547 * 128 bits, so we have to shift things up.
549 for (i = 0; i < 4; i++) {
550 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
552 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
555 /* Techincally, we should be getting all 48 bits of
556 * the response (SD_RESP1 + SD_RESP2), but because
557 * our response omits the CRC, our data ends up
558 * being shifted 8 bits to the right. In this case,
559 * that means that the OSR data starts at bit 31,
560 * so we can just read RESP0 and return that.
562 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
566 /* Figure out errors */
567 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
568 cmd->error = -EILSEQ;
570 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
572 if (!trans || cmd->error) {
573 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
574 tasklet_schedule(&host->finish_task);
578 host->status = HOST_S_DATA;
580 if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
581 u32 channel = DMA_CHANNEL(host);
583 /* Start the DBDMA as soon as the buffer gets something in it */
585 if (host->flags & HOST_F_RECV) {
586 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
588 while((status & mask) != mask)
589 status = au_readl(HOST_STATUS(host));
592 au1xxx_dbdma_start(channel);
596 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
598 unsigned int pbus = get_au1x00_speed();
599 unsigned int divisor;
603 * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
605 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
607 divisor = ((pbus / rate) / 2) - 1;
609 config = au_readl(HOST_CONFIG(host));
611 config &= ~(SD_CONFIG_DIV);
612 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
614 au_writel(config, HOST_CONFIG(host));
618 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
619 struct mmc_data *data)
621 int datalen = data->blocks * data->blksz;
623 if (data->flags & MMC_DATA_READ)
624 host->flags |= HOST_F_RECV;
626 host->flags |= HOST_F_XMIT;
629 host->flags |= HOST_F_STOP;
631 host->dma.dir = DMA_BIDIRECTIONAL;
633 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
634 data->sg_len, host->dma.dir);
636 if (host->dma.len == 0)
639 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
641 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
643 u32 channel = DMA_CHANNEL(host);
645 au1xxx_dbdma_stop(channel);
647 for (i = 0; i < host->dma.len; i++) {
648 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
649 struct scatterlist *sg = &data->sg[i];
650 int sg_len = sg->length;
652 int len = (datalen > sg_len) ? sg_len : datalen;
654 if (i == host->dma.len - 1)
655 flags = DDMA_FLAGS_IE;
657 if (host->flags & HOST_F_XMIT) {
658 ret = au1xxx_dbdma_put_source(channel,
659 sg_phys(sg), len, flags);
661 ret = au1xxx_dbdma_put_dest(channel,
662 sg_phys(sg), len, flags);
672 host->pio.offset = 0;
673 host->pio.len = datalen;
675 if (host->flags & HOST_F_XMIT)
676 IRQ_ON(host, SD_CONFIG_TH);
678 IRQ_ON(host, SD_CONFIG_NE);
679 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
685 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
690 /* This actually starts a command or data transaction */
691 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
693 struct au1xmmc_host *host = mmc_priv(mmc);
696 WARN_ON(irqs_disabled());
697 WARN_ON(host->status != HOST_S_IDLE);
700 host->status = HOST_S_CMD;
702 /* fail request immediately if no card is present */
703 if (0 == au1xmmc_card_inserted(mmc)) {
704 mrq->cmd->error = -ENOMEDIUM;
705 au1xmmc_finish_request(host);
711 ret = au1xmmc_prepare_data(host, mrq->data);
715 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
718 mrq->cmd->error = ret;
719 au1xmmc_finish_request(host);
723 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
725 /* Apply the clock */
726 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
729 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
732 au_writel(~0, HOST_STATUS(host));
735 au_writel(0, HOST_BLKSIZE(host));
736 au_writel(0x001fffff, HOST_TIMEOUT(host));
739 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
742 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
745 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
748 /* Configure interrupts */
749 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
754 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
756 struct au1xmmc_host *host = mmc_priv(mmc);
759 if (ios->power_mode == MMC_POWER_OFF)
760 au1xmmc_set_power(host, 0);
761 else if (ios->power_mode == MMC_POWER_ON) {
762 au1xmmc_set_power(host, 1);
765 if (ios->clock && ios->clock != host->clock) {
766 au1xmmc_set_clock(host, ios->clock);
767 host->clock = ios->clock;
770 config2 = au_readl(HOST_CONFIG2(host));
771 switch (ios->bus_width) {
772 case MMC_BUS_WIDTH_8:
773 config2 |= SD_CONFIG2_BB;
775 case MMC_BUS_WIDTH_4:
776 config2 &= ~SD_CONFIG2_BB;
777 config2 |= SD_CONFIG2_WB;
779 case MMC_BUS_WIDTH_1:
780 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
783 au_writel(config2, HOST_CONFIG2(host));
787 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
788 #define STATUS_DATA_IN (SD_STATUS_NE)
789 #define STATUS_DATA_OUT (SD_STATUS_TH)
791 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
793 struct au1xmmc_host *host = dev_id;
796 status = au_readl(HOST_STATUS(host));
798 if (!(status & SD_STATUS_I))
799 return IRQ_NONE; /* not ours */
801 if (status & SD_STATUS_SI) /* SDIO */
802 mmc_signal_sdio_irq(host->mmc);
804 if (host->mrq && (status & STATUS_TIMEOUT)) {
805 if (status & SD_STATUS_RAT)
806 host->mrq->cmd->error = -ETIMEDOUT;
807 else if (status & SD_STATUS_DT)
808 host->mrq->data->error = -ETIMEDOUT;
810 /* In PIO mode, interrupts might still be enabled */
811 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
813 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
814 tasklet_schedule(&host->finish_task);
817 else if (status & SD_STATUS_DD) {
818 /* Sometimes we get a DD before a NE in PIO mode */
819 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
820 au1xmmc_receive_pio(host);
822 au1xmmc_data_complete(host, status);
823 /* tasklet_schedule(&host->data_task); */
827 else if (status & SD_STATUS_CR) {
828 if (host->status == HOST_S_CMD)
829 au1xmmc_cmd_complete(host, status);
831 } else if (!(host->flags & HOST_F_DMA)) {
832 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
833 au1xmmc_send_pio(host);
834 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
835 au1xmmc_receive_pio(host);
837 } else if (status & 0x203F3C70) {
838 DBG("Unhandled status %8.8x\n", host->pdev->id,
842 au_writel(status, HOST_STATUS(host));
848 /* 8bit memory DMA device */
849 static dbdev_tab_t au1xmmc_mem_dbdev = {
850 .dev_id = DSCR_CMD0_ALWAYS,
851 .dev_flags = DEV_FLAGS_ANYUSE,
854 .dev_physaddr = 0x00000000,
856 .dev_intpolarity = 0,
860 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
862 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
864 /* Avoid spurious interrupts */
868 if (host->flags & HOST_F_STOP)
871 tasklet_schedule(&host->data_task);
874 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
876 struct resource *res;
879 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
884 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
892 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
893 au1xmmc_dbdma_callback, (void *)host);
894 if (!host->tx_chan) {
895 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
899 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
900 au1xmmc_dbdma_callback, (void *)host);
901 if (!host->rx_chan) {
902 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
903 au1xxx_dbdma_chan_free(host->tx_chan);
907 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
908 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
910 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
911 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
913 /* DBDMA is good to go */
914 host->flags |= HOST_F_DMA | HOST_F_DBDMA;
919 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
921 if (host->flags & HOST_F_DMA) {
922 host->flags &= ~HOST_F_DMA;
923 au1xxx_dbdma_chan_free(host->tx_chan);
924 au1xxx_dbdma_chan_free(host->rx_chan);
928 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
930 struct au1xmmc_host *host = mmc_priv(mmc);
933 IRQ_ON(host, SD_CONFIG_SI);
935 IRQ_OFF(host, SD_CONFIG_SI);
938 static const struct mmc_host_ops au1xmmc_ops = {
939 .request = au1xmmc_request,
940 .set_ios = au1xmmc_set_ios,
941 .get_ro = au1xmmc_card_readonly,
942 .get_cd = au1xmmc_card_inserted,
943 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
946 static int __devinit au1xmmc_probe(struct platform_device *pdev)
948 struct mmc_host *mmc;
949 struct au1xmmc_host *host;
953 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
955 dev_err(&pdev->dev, "no memory for mmc_host\n");
960 host = mmc_priv(mmc);
962 host->platdata = pdev->dev.platform_data;
966 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
968 dev_err(&pdev->dev, "no mmio defined\n");
972 host->ioarea = request_mem_region(r->start, resource_size(r),
975 dev_err(&pdev->dev, "mmio already in use\n");
979 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
981 dev_err(&pdev->dev, "cannot remap mmio\n");
985 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
987 dev_err(&pdev->dev, "no IRQ defined\n");
990 host->irq = r->start;
992 mmc->ops = &au1xmmc_ops;
995 mmc->f_max = 24000000;
997 mmc->max_blk_size = 2048;
998 mmc->max_blk_count = 512;
1000 mmc->ocr_avail = AU1XMMC_OCR;
1001 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1002 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1004 iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */
1006 switch (alchemy_get_cputype()) {
1007 case ALCHEMY_CPU_AU1100:
1008 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1010 case ALCHEMY_CPU_AU1200:
1011 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1013 case ALCHEMY_CPU_AU1300:
1014 iflag = 0; /* nothing is shared */
1015 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1016 mmc->f_max = 52000000;
1017 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1018 mmc->caps |= MMC_CAP_8_BIT_DATA;
1022 ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1024 dev_err(&pdev->dev, "cannot grab IRQ\n");
1028 host->status = HOST_S_IDLE;
1030 /* board-specific carddetect setup, if any */
1031 if (host->platdata && host->platdata->cd_setup) {
1032 ret = host->platdata->cd_setup(mmc, 1);
1034 dev_warn(&pdev->dev, "board CD setup failed\n");
1035 mmc->caps |= MMC_CAP_NEEDS_POLL;
1038 mmc->caps |= MMC_CAP_NEEDS_POLL;
1040 /* platform may not be able to use all advertised caps */
1042 mmc->caps &= ~(host->platdata->mask_host_caps);
1044 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1045 (unsigned long)host);
1047 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1048 (unsigned long)host);
1051 ret = au1xmmc_dbdma_init(host);
1053 pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1056 #ifdef CONFIG_LEDS_CLASS
1057 if (host->platdata && host->platdata->led) {
1058 struct led_classdev *led = host->platdata->led;
1059 led->name = mmc_hostname(mmc);
1060 led->brightness = LED_OFF;
1061 led->default_trigger = mmc_hostname(mmc);
1062 ret = led_classdev_register(mmc_dev(mmc), led);
1068 au1xmmc_reset_controller(host);
1070 ret = mmc_add_host(mmc);
1072 dev_err(&pdev->dev, "cannot add mmc host\n");
1076 platform_set_drvdata(pdev, host);
1078 pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1079 " (mode=%s)\n", pdev->id, host->iobase,
1080 host->flags & HOST_F_DMA ? "dma" : "pio");
1082 return 0; /* all ok */
1085 #ifdef CONFIG_LEDS_CLASS
1086 if (host->platdata && host->platdata->led)
1087 led_classdev_unregister(host->platdata->led);
1090 au_writel(0, HOST_ENABLE(host));
1091 au_writel(0, HOST_CONFIG(host));
1092 au_writel(0, HOST_CONFIG2(host));
1095 if (host->flags & HOST_F_DBDMA)
1096 au1xmmc_dbdma_shutdown(host);
1098 tasklet_kill(&host->data_task);
1099 tasklet_kill(&host->finish_task);
1101 if (host->platdata && host->platdata->cd_setup &&
1102 !(mmc->caps & MMC_CAP_NEEDS_POLL))
1103 host->platdata->cd_setup(mmc, 0);
1105 free_irq(host->irq, host);
1107 iounmap((void *)host->iobase);
1109 release_resource(host->ioarea);
1110 kfree(host->ioarea);
1117 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1119 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1122 mmc_remove_host(host->mmc);
1124 #ifdef CONFIG_LEDS_CLASS
1125 if (host->platdata && host->platdata->led)
1126 led_classdev_unregister(host->platdata->led);
1129 if (host->platdata && host->platdata->cd_setup &&
1130 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1131 host->platdata->cd_setup(host->mmc, 0);
1133 au_writel(0, HOST_ENABLE(host));
1134 au_writel(0, HOST_CONFIG(host));
1135 au_writel(0, HOST_CONFIG2(host));
1138 tasklet_kill(&host->data_task);
1139 tasklet_kill(&host->finish_task);
1141 if (host->flags & HOST_F_DBDMA)
1142 au1xmmc_dbdma_shutdown(host);
1144 au1xmmc_set_power(host, 0);
1146 free_irq(host->irq, host);
1147 iounmap((void *)host->iobase);
1148 release_resource(host->ioarea);
1149 kfree(host->ioarea);
1151 mmc_free_host(host->mmc);
1152 platform_set_drvdata(pdev, NULL);
1158 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1160 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1163 ret = mmc_suspend_host(host->mmc);
1167 au_writel(0, HOST_CONFIG2(host));
1168 au_writel(0, HOST_CONFIG(host));
1169 au_writel(0xffffffff, HOST_STATUS(host));
1170 au_writel(0, HOST_ENABLE(host));
1176 static int au1xmmc_resume(struct platform_device *pdev)
1178 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1180 au1xmmc_reset_controller(host);
1182 return mmc_resume_host(host->mmc);
1185 #define au1xmmc_suspend NULL
1186 #define au1xmmc_resume NULL
1189 static struct platform_driver au1xmmc_driver = {
1190 .probe = au1xmmc_probe,
1191 .remove = au1xmmc_remove,
1192 .suspend = au1xmmc_suspend,
1193 .resume = au1xmmc_resume,
1195 .name = DRIVER_NAME,
1196 .owner = THIS_MODULE,
1200 static int __init au1xmmc_init(void)
1203 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1204 * of 8 bits. And since devices are shared, we need to create
1205 * our own to avoid freaking out other devices.
1207 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1209 pr_err("au1xmmc: cannot add memory dbdma\n");
1211 return platform_driver_register(&au1xmmc_driver);
1214 static void __exit au1xmmc_exit(void)
1216 if (has_dbdma() && memid)
1217 au1xxx_ddma_del_device(memid);
1219 platform_driver_unregister(&au1xmmc_driver);
1222 module_init(au1xmmc_init);
1223 module_exit(au1xmmc_exit);
1225 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1226 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1227 MODULE_LICENSE("GPL");
1228 MODULE_ALIAS("platform:au1xxx-mmc");