2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why don't we use the SD controllers' carddetect feature?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/leds.h>
43 #include <linux/mmc/host.h>
44 #include <linux/slab.h>
47 #include <asm/mach-au1x00/au1000.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
49 #include <asm/mach-au1x00/au1100_mmc.h>
51 #define DRIVER_NAME "au1xxx-mmc"
53 /* Set this to enable special debugging macros */
57 #define DBG(fmt, idx, args...) \
58 printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
60 #define DBG(fmt, idx, args...) do {} while (0)
63 /* Hardware definitions */
64 #define AU1XMMC_DESCRIPTOR_COUNT 1
66 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
67 #ifdef CONFIG_SOC_AU1100
68 #define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff
70 #define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff
73 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
74 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
75 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
77 /* This gives us a hard value for the stop command that we can write directly
78 * to the command register.
81 (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
83 /* This is the set of interrupts that we configure by default. */
84 #define AU1XMMC_INTERRUPTS \
85 (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
86 SD_CONFIG_CR | SD_CONFIG_I)
88 /* The poll event (looking for insert/remove events runs twice a second. */
89 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
93 struct mmc_request *mrq;
119 struct tasklet_struct finish_task;
120 struct tasklet_struct data_task;
121 struct au1xmmc_platform_data *platdata;
122 struct platform_device *pdev;
123 struct resource *ioarea;
126 /* Status flags used by the host structure */
127 #define HOST_F_XMIT 0x0001
128 #define HOST_F_RECV 0x0002
129 #define HOST_F_DMA 0x0010
130 #define HOST_F_ACTIVE 0x0100
131 #define HOST_F_STOP 0x1000
133 #define HOST_S_IDLE 0x0001
134 #define HOST_S_CMD 0x0002
135 #define HOST_S_DATA 0x0003
136 #define HOST_S_STOP 0x0004
138 /* Easy access macros */
139 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
140 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
141 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
142 #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
143 #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
144 #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
145 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
146 #define HOST_CMD(h) ((h)->iobase + SD_CMD)
147 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
148 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
149 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
151 #define DMA_CHANNEL(h) \
152 (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
154 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
156 u32 val = au_readl(HOST_CONFIG(host));
158 au_writel(val, HOST_CONFIG(host));
162 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
164 u32 val = au_readl(HOST_CONFIG2(host));
166 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
169 /* SEND_STOP will turn off clock control - this re-enables it */
170 val &= ~SD_CONFIG2_DF;
172 au_writel(val, HOST_CONFIG2(host));
176 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
178 u32 val = au_readl(HOST_CONFIG(host));
180 au_writel(val, HOST_CONFIG(host));
184 static inline void SEND_STOP(struct au1xmmc_host *host)
188 WARN_ON(host->status != HOST_S_DATA);
189 host->status = HOST_S_STOP;
191 config2 = au_readl(HOST_CONFIG2(host));
192 au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
195 /* Send the stop commmand */
196 au_writel(STOP_CMD, HOST_CMD(host));
199 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
201 if (host->platdata && host->platdata->set_power)
202 host->platdata->set_power(host->mmc, state);
205 static int au1xmmc_card_inserted(struct mmc_host *mmc)
207 struct au1xmmc_host *host = mmc_priv(mmc);
209 if (host->platdata && host->platdata->card_inserted)
210 return !!host->platdata->card_inserted(host->mmc);
215 static int au1xmmc_card_readonly(struct mmc_host *mmc)
217 struct au1xmmc_host *host = mmc_priv(mmc);
219 if (host->platdata && host->platdata->card_readonly)
220 return !!host->platdata->card_readonly(mmc);
225 static void au1xmmc_finish_request(struct au1xmmc_host *host)
227 struct mmc_request *mrq = host->mrq;
230 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
236 host->pio.offset = 0;
239 host->status = HOST_S_IDLE;
241 mmc_request_done(host->mmc, mrq);
244 static void au1xmmc_tasklet_finish(unsigned long param)
246 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
247 au1xmmc_finish_request(host);
250 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
251 struct mmc_command *cmd, struct mmc_data *data)
253 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
255 switch (mmc_resp_type(cmd)) {
259 mmccmd |= SD_CMD_RT_1;
262 mmccmd |= SD_CMD_RT_1B;
265 mmccmd |= SD_CMD_RT_2;
268 mmccmd |= SD_CMD_RT_3;
271 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
277 if (data->flags & MMC_DATA_READ) {
278 if (data->blocks > 1)
279 mmccmd |= SD_CMD_CT_4;
281 mmccmd |= SD_CMD_CT_2;
282 } else if (data->flags & MMC_DATA_WRITE) {
283 if (data->blocks > 1)
284 mmccmd |= SD_CMD_CT_3;
286 mmccmd |= SD_CMD_CT_1;
290 au_writel(cmd->arg, HOST_CMDARG(host));
294 IRQ_OFF(host, SD_CONFIG_CR);
296 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
299 /* Wait for the command to go on the line */
300 while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
303 /* Wait for the command to come back */
305 u32 status = au_readl(HOST_STATUS(host));
307 while (!(status & SD_STATUS_CR))
308 status = au_readl(HOST_STATUS(host));
310 /* Clear the CR status */
311 au_writel(SD_STATUS_CR, HOST_STATUS(host));
313 IRQ_ON(host, SD_CONFIG_CR);
319 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
321 struct mmc_request *mrq = host->mrq;
322 struct mmc_data *data;
325 WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
327 if (host->mrq == NULL)
330 data = mrq->cmd->data;
333 status = au_readl(HOST_STATUS(host));
335 /* The transaction is really over when the SD_STATUS_DB bit is clear */
336 while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
337 status = au_readl(HOST_STATUS(host));
340 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
342 /* Process any errors */
343 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
344 if (host->flags & HOST_F_XMIT)
345 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
348 data->error = -EILSEQ;
350 /* Clear the CRC bits */
351 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
353 data->bytes_xfered = 0;
356 if (host->flags & HOST_F_DMA) {
357 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
358 u32 chan = DMA_CHANNEL(host);
360 chan_tab_t *c = *((chan_tab_t **)chan);
361 au1x_dma_chan_t *cp = c->chan_ptr;
362 data->bytes_xfered = cp->ddma_bytecnt;
366 (data->blocks * data->blksz) - host->pio.len;
369 au1xmmc_finish_request(host);
372 static void au1xmmc_tasklet_data(unsigned long param)
374 struct au1xmmc_host *host = (struct au1xmmc_host *)param;
376 u32 status = au_readl(HOST_STATUS(host));
377 au1xmmc_data_complete(host, status);
380 #define AU1XMMC_MAX_TRANSFER 8
382 static void au1xmmc_send_pio(struct au1xmmc_host *host)
384 struct mmc_data *data;
385 int sg_len, max, count;
386 unsigned char *sg_ptr, val;
388 struct scatterlist *sg;
390 data = host->mrq->data;
392 if (!(host->flags & HOST_F_XMIT))
395 /* This is the pointer to the data buffer */
396 sg = &data->sg[host->pio.index];
397 sg_ptr = sg_virt(sg) + host->pio.offset;
399 /* This is the space left inside the buffer */
400 sg_len = data->sg[host->pio.index].length - host->pio.offset;
402 /* Check if we need less than the size of the sg_buffer */
403 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
404 if (max > AU1XMMC_MAX_TRANSFER)
405 max = AU1XMMC_MAX_TRANSFER;
407 for (count = 0; count < max; count++) {
408 status = au_readl(HOST_STATUS(host));
410 if (!(status & SD_STATUS_TH))
415 au_writel((unsigned long)val, HOST_TXPORT(host));
419 host->pio.len -= count;
420 host->pio.offset += count;
422 if (count == sg_len) {
424 host->pio.offset = 0;
427 if (host->pio.len == 0) {
428 IRQ_OFF(host, SD_CONFIG_TH);
430 if (host->flags & HOST_F_STOP)
433 tasklet_schedule(&host->data_task);
437 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
439 struct mmc_data *data;
440 int max, count, sg_len = 0;
441 unsigned char *sg_ptr = NULL;
443 struct scatterlist *sg;
445 data = host->mrq->data;
447 if (!(host->flags & HOST_F_RECV))
452 if (host->pio.index < host->dma.len) {
453 sg = &data->sg[host->pio.index];
454 sg_ptr = sg_virt(sg) + host->pio.offset;
456 /* This is the space left inside the buffer */
457 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
459 /* Check if we need less than the size of the sg_buffer */
464 if (max > AU1XMMC_MAX_TRANSFER)
465 max = AU1XMMC_MAX_TRANSFER;
467 for (count = 0; count < max; count++) {
468 status = au_readl(HOST_STATUS(host));
470 if (!(status & SD_STATUS_NE))
473 if (status & SD_STATUS_RC) {
474 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
475 host->pio.len, count);
479 if (status & SD_STATUS_RO) {
480 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
481 host->pio.len, count);
484 else if (status & SD_STATUS_RU) {
485 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
486 host->pio.len, count);
490 val = au_readl(HOST_RXPORT(host));
493 *sg_ptr++ = (unsigned char)(val & 0xFF);
496 host->pio.len -= count;
497 host->pio.offset += count;
499 if (sg_len && count == sg_len) {
501 host->pio.offset = 0;
504 if (host->pio.len == 0) {
505 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
506 IRQ_OFF(host, SD_CONFIG_NE);
508 if (host->flags & HOST_F_STOP)
511 tasklet_schedule(&host->data_task);
515 /* This is called when a command has been completed - grab the response
516 * and check for errors. Then start the data transfer if it is indicated.
518 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
520 struct mmc_request *mrq = host->mrq;
521 struct mmc_command *cmd;
531 if (cmd->flags & MMC_RSP_PRESENT) {
532 if (cmd->flags & MMC_RSP_136) {
533 r[0] = au_readl(host->iobase + SD_RESP3);
534 r[1] = au_readl(host->iobase + SD_RESP2);
535 r[2] = au_readl(host->iobase + SD_RESP1);
536 r[3] = au_readl(host->iobase + SD_RESP0);
538 /* The CRC is omitted from the response, so really
539 * we only got 120 bytes, but the engine expects
540 * 128 bits, so we have to shift things up.
542 for (i = 0; i < 4; i++) {
543 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
545 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
548 /* Techincally, we should be getting all 48 bits of
549 * the response (SD_RESP1 + SD_RESP2), but because
550 * our response omits the CRC, our data ends up
551 * being shifted 8 bits to the right. In this case,
552 * that means that the OSR data starts at bit 31,
553 * so we can just read RESP0 and return that.
555 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
559 /* Figure out errors */
560 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
561 cmd->error = -EILSEQ;
563 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
565 if (!trans || cmd->error) {
566 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
567 tasklet_schedule(&host->finish_task);
571 host->status = HOST_S_DATA;
573 if (host->flags & HOST_F_DMA) {
574 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
575 u32 channel = DMA_CHANNEL(host);
577 /* Start the DMA as soon as the buffer gets something in it */
579 if (host->flags & HOST_F_RECV) {
580 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
582 while((status & mask) != mask)
583 status = au_readl(HOST_STATUS(host));
586 au1xxx_dbdma_start(channel);
591 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
593 unsigned int pbus = get_au1x00_speed();
594 unsigned int divisor;
598 * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
600 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
602 divisor = ((pbus / rate) / 2) - 1;
604 config = au_readl(HOST_CONFIG(host));
606 config &= ~(SD_CONFIG_DIV);
607 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
609 au_writel(config, HOST_CONFIG(host));
613 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
614 struct mmc_data *data)
616 int datalen = data->blocks * data->blksz;
618 if (data->flags & MMC_DATA_READ)
619 host->flags |= HOST_F_RECV;
621 host->flags |= HOST_F_XMIT;
624 host->flags |= HOST_F_STOP;
626 host->dma.dir = DMA_BIDIRECTIONAL;
628 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
629 data->sg_len, host->dma.dir);
631 if (host->dma.len == 0)
634 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
636 if (host->flags & HOST_F_DMA) {
637 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
639 u32 channel = DMA_CHANNEL(host);
641 au1xxx_dbdma_stop(channel);
643 for (i = 0; i < host->dma.len; i++) {
644 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
645 struct scatterlist *sg = &data->sg[i];
646 int sg_len = sg->length;
648 int len = (datalen > sg_len) ? sg_len : datalen;
650 if (i == host->dma.len - 1)
651 flags = DDMA_FLAGS_IE;
653 if (host->flags & HOST_F_XMIT) {
654 ret = au1xxx_dbdma_put_source(channel,
655 sg_phys(sg), len, flags);
657 ret = au1xxx_dbdma_put_dest(channel,
658 sg_phys(sg), len, flags);
669 host->pio.offset = 0;
670 host->pio.len = datalen;
672 if (host->flags & HOST_F_XMIT)
673 IRQ_ON(host, SD_CONFIG_TH);
675 IRQ_ON(host, SD_CONFIG_NE);
676 /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
682 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
687 /* This actually starts a command or data transaction */
688 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
690 struct au1xmmc_host *host = mmc_priv(mmc);
693 WARN_ON(irqs_disabled());
694 WARN_ON(host->status != HOST_S_IDLE);
697 host->status = HOST_S_CMD;
699 /* fail request immediately if no card is present */
700 if (0 == au1xmmc_card_inserted(mmc)) {
701 mrq->cmd->error = -ENOMEDIUM;
702 au1xmmc_finish_request(host);
708 ret = au1xmmc_prepare_data(host, mrq->data);
712 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
715 mrq->cmd->error = ret;
716 au1xmmc_finish_request(host);
720 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
722 /* Apply the clock */
723 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
726 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
729 au_writel(~0, HOST_STATUS(host));
732 au_writel(0, HOST_BLKSIZE(host));
733 au_writel(0x001fffff, HOST_TIMEOUT(host));
736 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
739 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
742 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
745 /* Configure interrupts */
746 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
751 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
753 struct au1xmmc_host *host = mmc_priv(mmc);
756 if (ios->power_mode == MMC_POWER_OFF)
757 au1xmmc_set_power(host, 0);
758 else if (ios->power_mode == MMC_POWER_ON) {
759 au1xmmc_set_power(host, 1);
762 if (ios->clock && ios->clock != host->clock) {
763 au1xmmc_set_clock(host, ios->clock);
764 host->clock = ios->clock;
767 config2 = au_readl(HOST_CONFIG2(host));
768 switch (ios->bus_width) {
769 case MMC_BUS_WIDTH_4:
770 config2 |= SD_CONFIG2_WB;
772 case MMC_BUS_WIDTH_1:
773 config2 &= ~SD_CONFIG2_WB;
776 au_writel(config2, HOST_CONFIG2(host));
780 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
781 #define STATUS_DATA_IN (SD_STATUS_NE)
782 #define STATUS_DATA_OUT (SD_STATUS_TH)
784 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
786 struct au1xmmc_host *host = dev_id;
789 status = au_readl(HOST_STATUS(host));
791 if (!(status & SD_STATUS_I))
792 return IRQ_NONE; /* not ours */
794 if (status & SD_STATUS_SI) /* SDIO */
795 mmc_signal_sdio_irq(host->mmc);
797 if (host->mrq && (status & STATUS_TIMEOUT)) {
798 if (status & SD_STATUS_RAT)
799 host->mrq->cmd->error = -ETIMEDOUT;
800 else if (status & SD_STATUS_DT)
801 host->mrq->data->error = -ETIMEDOUT;
803 /* In PIO mode, interrupts might still be enabled */
804 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
806 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
807 tasklet_schedule(&host->finish_task);
810 else if (status & SD_STATUS_DD) {
811 /* Sometimes we get a DD before a NE in PIO mode */
812 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
813 au1xmmc_receive_pio(host);
815 au1xmmc_data_complete(host, status);
816 /* tasklet_schedule(&host->data_task); */
820 else if (status & SD_STATUS_CR) {
821 if (host->status == HOST_S_CMD)
822 au1xmmc_cmd_complete(host, status);
824 } else if (!(host->flags & HOST_F_DMA)) {
825 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
826 au1xmmc_send_pio(host);
827 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
828 au1xmmc_receive_pio(host);
830 } else if (status & 0x203F3C70) {
831 DBG("Unhandled status %8.8x\n", host->pdev->id,
835 au_writel(status, HOST_STATUS(host));
841 #ifdef CONFIG_SOC_AU1200
842 /* 8bit memory DMA device */
843 static dbdev_tab_t au1xmmc_mem_dbdev = {
844 .dev_id = DSCR_CMD0_ALWAYS,
845 .dev_flags = DEV_FLAGS_ANYUSE,
848 .dev_physaddr = 0x00000000,
850 .dev_intpolarity = 0,
854 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
856 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
858 /* Avoid spurious interrupts */
862 if (host->flags & HOST_F_STOP)
865 tasklet_schedule(&host->data_task);
868 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
870 struct resource *res;
873 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
878 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
886 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
887 au1xmmc_dbdma_callback, (void *)host);
888 if (!host->tx_chan) {
889 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
893 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
894 au1xmmc_dbdma_callback, (void *)host);
895 if (!host->rx_chan) {
896 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
897 au1xxx_dbdma_chan_free(host->tx_chan);
901 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
902 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
904 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
905 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
907 /* DBDMA is good to go */
908 host->flags |= HOST_F_DMA;
913 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
915 if (host->flags & HOST_F_DMA) {
916 host->flags &= ~HOST_F_DMA;
917 au1xxx_dbdma_chan_free(host->tx_chan);
918 au1xxx_dbdma_chan_free(host->rx_chan);
923 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
925 struct au1xmmc_host *host = mmc_priv(mmc);
928 IRQ_ON(host, SD_CONFIG_SI);
930 IRQ_OFF(host, SD_CONFIG_SI);
933 static const struct mmc_host_ops au1xmmc_ops = {
934 .request = au1xmmc_request,
935 .set_ios = au1xmmc_set_ios,
936 .get_ro = au1xmmc_card_readonly,
937 .get_cd = au1xmmc_card_inserted,
938 .enable_sdio_irq = au1xmmc_enable_sdio_irq,
941 static int __devinit au1xmmc_probe(struct platform_device *pdev)
943 struct mmc_host *mmc;
944 struct au1xmmc_host *host;
948 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
950 dev_err(&pdev->dev, "no memory for mmc_host\n");
955 host = mmc_priv(mmc);
957 host->platdata = pdev->dev.platform_data;
961 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963 dev_err(&pdev->dev, "no mmio defined\n");
967 host->ioarea = request_mem_region(r->start, resource_size(r),
970 dev_err(&pdev->dev, "mmio already in use\n");
974 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
976 dev_err(&pdev->dev, "cannot remap mmio\n");
980 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
982 dev_err(&pdev->dev, "no IRQ defined\n");
986 host->irq = r->start;
987 /* IRQ is shared among both SD controllers */
988 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
991 dev_err(&pdev->dev, "cannot grab IRQ\n");
995 mmc->ops = &au1xmmc_ops;
998 mmc->f_max = 24000000;
1000 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
1001 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1003 mmc->max_blk_size = 2048;
1004 mmc->max_blk_count = 512;
1006 mmc->ocr_avail = AU1XMMC_OCR;
1007 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1009 host->status = HOST_S_IDLE;
1011 /* board-specific carddetect setup, if any */
1012 if (host->platdata && host->platdata->cd_setup) {
1013 ret = host->platdata->cd_setup(mmc, 1);
1015 dev_warn(&pdev->dev, "board CD setup failed\n");
1016 mmc->caps |= MMC_CAP_NEEDS_POLL;
1019 mmc->caps |= MMC_CAP_NEEDS_POLL;
1021 /* platform may not be able to use all advertised caps */
1023 mmc->caps &= ~(host->platdata->mask_host_caps);
1025 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1026 (unsigned long)host);
1028 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1029 (unsigned long)host);
1031 #ifdef CONFIG_SOC_AU1200
1032 ret = au1xmmc_dbdma_init(host);
1034 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1037 #ifdef CONFIG_LEDS_CLASS
1038 if (host->platdata && host->platdata->led) {
1039 struct led_classdev *led = host->platdata->led;
1040 led->name = mmc_hostname(mmc);
1041 led->brightness = LED_OFF;
1042 led->default_trigger = mmc_hostname(mmc);
1043 ret = led_classdev_register(mmc_dev(mmc), led);
1049 au1xmmc_reset_controller(host);
1051 ret = mmc_add_host(mmc);
1053 dev_err(&pdev->dev, "cannot add mmc host\n");
1057 platform_set_drvdata(pdev, host);
1059 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1060 " (mode=%s)\n", pdev->id, host->iobase,
1061 host->flags & HOST_F_DMA ? "dma" : "pio");
1063 return 0; /* all ok */
1066 #ifdef CONFIG_LEDS_CLASS
1067 if (host->platdata && host->platdata->led)
1068 led_classdev_unregister(host->platdata->led);
1071 au_writel(0, HOST_ENABLE(host));
1072 au_writel(0, HOST_CONFIG(host));
1073 au_writel(0, HOST_CONFIG2(host));
1076 #ifdef CONFIG_SOC_AU1200
1077 au1xmmc_dbdma_shutdown(host);
1080 tasklet_kill(&host->data_task);
1081 tasklet_kill(&host->finish_task);
1083 if (host->platdata && host->platdata->cd_setup &&
1084 !(mmc->caps & MMC_CAP_NEEDS_POLL))
1085 host->platdata->cd_setup(mmc, 0);
1087 free_irq(host->irq, host);
1089 iounmap((void *)host->iobase);
1091 release_resource(host->ioarea);
1092 kfree(host->ioarea);
1099 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1101 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1104 mmc_remove_host(host->mmc);
1106 #ifdef CONFIG_LEDS_CLASS
1107 if (host->platdata && host->platdata->led)
1108 led_classdev_unregister(host->platdata->led);
1111 if (host->platdata && host->platdata->cd_setup &&
1112 !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1113 host->platdata->cd_setup(host->mmc, 0);
1115 au_writel(0, HOST_ENABLE(host));
1116 au_writel(0, HOST_CONFIG(host));
1117 au_writel(0, HOST_CONFIG2(host));
1120 tasklet_kill(&host->data_task);
1121 tasklet_kill(&host->finish_task);
1123 #ifdef CONFIG_SOC_AU1200
1124 au1xmmc_dbdma_shutdown(host);
1126 au1xmmc_set_power(host, 0);
1128 free_irq(host->irq, host);
1129 iounmap((void *)host->iobase);
1130 release_resource(host->ioarea);
1131 kfree(host->ioarea);
1133 mmc_free_host(host->mmc);
1134 platform_set_drvdata(pdev, NULL);
1140 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1142 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1145 ret = mmc_suspend_host(host->mmc);
1149 au_writel(0, HOST_CONFIG2(host));
1150 au_writel(0, HOST_CONFIG(host));
1151 au_writel(0xffffffff, HOST_STATUS(host));
1152 au_writel(0, HOST_ENABLE(host));
1158 static int au1xmmc_resume(struct platform_device *pdev)
1160 struct au1xmmc_host *host = platform_get_drvdata(pdev);
1162 au1xmmc_reset_controller(host);
1164 return mmc_resume_host(host->mmc);
1167 #define au1xmmc_suspend NULL
1168 #define au1xmmc_resume NULL
1171 static struct platform_driver au1xmmc_driver = {
1172 .probe = au1xmmc_probe,
1173 .remove = au1xmmc_remove,
1174 .suspend = au1xmmc_suspend,
1175 .resume = au1xmmc_resume,
1177 .name = DRIVER_NAME,
1178 .owner = THIS_MODULE,
1182 static int __init au1xmmc_init(void)
1184 #ifdef CONFIG_SOC_AU1200
1185 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1186 * of 8 bits. And since devices are shared, we need to create
1187 * our own to avoid freaking out other devices.
1189 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1191 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1193 return platform_driver_register(&au1xmmc_driver);
1196 static void __exit au1xmmc_exit(void)
1198 #ifdef CONFIG_SOC_AU1200
1200 au1xxx_ddma_del_device(memid);
1202 platform_driver_unregister(&au1xmmc_driver);
1205 module_init(au1xmmc_init);
1206 module_exit(au1xmmc_exit);
1208 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1209 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1210 MODULE_LICENSE("GPL");
1211 MODULE_ALIAS("platform:au1xxx-mmc");