2 * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
4 * Copyright (c) 2005, Advanced Micro Devices, Inc.
6 * Developed with help from the 2.4.30 MMC AU1XXX controller including
7 * the following copyright notices:
8 * Copyright (c) 2003-2004 Embedded Edge, LLC.
9 * Portions Copyright (C) 2002 Embedix, Inc
10 * Copyright 2002 Hewlett-Packard Company
12 * 2.6 version of this driver inspired by:
13 * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
14 * All Rights Reserved.
15 * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
16 * All Rights Reserved.
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
24 /* Why is a timer used to detect insert events?
26 * From the AU1100 MMC application guide:
27 * If the Au1100-based design is intended to support both MultiMediaCards
28 * and 1- or 4-data bit SecureDigital cards, then the solution is to
29 * connect a weak (560KOhm) pull-up resistor to connector pin 1.
30 * In doing so, a MMC card never enters SPI-mode communications,
31 * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
32 * (the low to high transition will not occur).
34 * So we use the timer to check the status manually.
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/scatterlist.h>
44 #include <linux/leds.h>
45 #include <linux/mmc/host.h>
48 #include <asm/mach-au1x00/au1000.h>
49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1100_mmc.h>
55 #define DRIVER_NAME "au1xxx-mmc"
57 /* Set this to enable special debugging macros */
61 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
63 #define DBG(fmt, idx, args...)
66 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
68 u32 val = au_readl(HOST_CONFIG(host));
70 au_writel(val, HOST_CONFIG(host));
74 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
76 u32 val = au_readl(HOST_CONFIG2(host));
78 au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
81 /* SEND_STOP will turn off clock control - this re-enables it */
82 val &= ~SD_CONFIG2_DF;
84 au_writel(val, HOST_CONFIG2(host));
88 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
90 u32 val = au_readl(HOST_CONFIG(host));
92 au_writel(val, HOST_CONFIG(host));
96 static inline void SEND_STOP(struct au1xmmc_host *host)
99 /* We know the value of CONFIG2, so avoid a read we don't need */
100 u32 mask = SD_CONFIG2_EN;
102 WARN_ON(host->status != HOST_S_DATA);
103 host->status = HOST_S_STOP;
105 au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
108 /* Send the stop commmand */
109 au_writel(STOP_CMD, HOST_CMD(host));
112 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
114 if (host->platdata && host->platdata->set_power)
115 host->platdata->set_power(host->mmc, state);
118 static int au1xmmc_card_inserted(struct au1xmmc_host *host)
122 if (host->platdata && host->platdata->card_inserted)
123 ret = host->platdata->card_inserted(host->mmc);
125 ret = 1; /* assume there is a card */
130 static int au1xmmc_card_readonly(struct mmc_host *mmc)
132 struct au1xmmc_host *host = mmc_priv(mmc);
135 if (host->platdata && host->platdata->card_readonly)
136 ret = host->platdata->card_readonly(mmc);
138 ret = 0; /* assume card is read-write */
143 static void au1xmmc_finish_request(struct au1xmmc_host *host)
146 struct mmc_request *mrq = host->mrq;
149 host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
155 host->pio.offset = 0;
158 host->status = HOST_S_IDLE;
160 mmc_request_done(host->mmc, mrq);
163 static void au1xmmc_tasklet_finish(unsigned long param)
165 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
166 au1xmmc_finish_request(host);
169 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
170 struct mmc_command *cmd, struct mmc_data *data)
172 u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
174 switch (mmc_resp_type(cmd)) {
178 mmccmd |= SD_CMD_RT_1;
181 mmccmd |= SD_CMD_RT_1B;
184 mmccmd |= SD_CMD_RT_2;
187 mmccmd |= SD_CMD_RT_3;
190 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
196 if (data->flags & MMC_DATA_READ) {
197 if (data->blocks > 1)
198 mmccmd |= SD_CMD_CT_4;
200 mmccmd |= SD_CMD_CT_2;
201 } else if (data->flags & MMC_DATA_WRITE) {
202 if (data->blocks > 1)
203 mmccmd |= SD_CMD_CT_3;
205 mmccmd |= SD_CMD_CT_1;
209 au_writel(cmd->arg, HOST_CMDARG(host));
213 IRQ_OFF(host, SD_CONFIG_CR);
215 au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
218 /* Wait for the command to go on the line */
221 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
225 /* Wait for the command to come back */
228 u32 status = au_readl(HOST_STATUS(host));
230 while(!(status & SD_STATUS_CR))
231 status = au_readl(HOST_STATUS(host));
233 /* Clear the CR status */
234 au_writel(SD_STATUS_CR, HOST_STATUS(host));
236 IRQ_ON(host, SD_CONFIG_CR);
242 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
245 struct mmc_request *mrq = host->mrq;
246 struct mmc_data *data;
249 WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
251 if (host->mrq == NULL)
254 data = mrq->cmd->data;
257 status = au_readl(HOST_STATUS(host));
259 /* The transaction is really over when the SD_STATUS_DB bit is clear */
261 while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
262 status = au_readl(HOST_STATUS(host));
265 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
267 /* Process any errors */
269 crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
270 if (host->flags & HOST_F_XMIT)
271 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
274 data->error = -EILSEQ;
276 /* Clear the CRC bits */
277 au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
279 data->bytes_xfered = 0;
282 if (host->flags & HOST_F_DMA) {
283 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
284 u32 chan = DMA_CHANNEL(host);
286 chan_tab_t *c = *((chan_tab_t **) chan);
287 au1x_dma_chan_t *cp = c->chan_ptr;
288 data->bytes_xfered = cp->ddma_bytecnt;
293 (data->blocks * data->blksz) -
297 au1xmmc_finish_request(host);
300 static void au1xmmc_tasklet_data(unsigned long param)
302 struct au1xmmc_host *host = (struct au1xmmc_host *) param;
304 u32 status = au_readl(HOST_STATUS(host));
305 au1xmmc_data_complete(host, status);
308 #define AU1XMMC_MAX_TRANSFER 8
310 static void au1xmmc_send_pio(struct au1xmmc_host *host)
313 struct mmc_data *data = 0;
314 int sg_len, max, count = 0;
315 unsigned char *sg_ptr;
317 struct scatterlist *sg;
319 data = host->mrq->data;
321 if (!(host->flags & HOST_F_XMIT))
324 /* This is the pointer to the data buffer */
325 sg = &data->sg[host->pio.index];
326 sg_ptr = sg_virt(sg) + host->pio.offset;
328 /* This is the space left inside the buffer */
329 sg_len = data->sg[host->pio.index].length - host->pio.offset;
331 /* Check to if we need less then the size of the sg_buffer */
333 max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
334 if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
336 for(count = 0; count < max; count++ ) {
339 status = au_readl(HOST_STATUS(host));
341 if (!(status & SD_STATUS_TH))
346 au_writel((unsigned long) val, HOST_TXPORT(host));
350 host->pio.len -= count;
351 host->pio.offset += count;
353 if (count == sg_len) {
355 host->pio.offset = 0;
358 if (host->pio.len == 0) {
359 IRQ_OFF(host, SD_CONFIG_TH);
361 if (host->flags & HOST_F_STOP)
364 tasklet_schedule(&host->data_task);
368 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
371 struct mmc_data *data = 0;
372 int sg_len = 0, max = 0, count = 0;
373 unsigned char *sg_ptr = 0;
375 struct scatterlist *sg;
377 data = host->mrq->data;
379 if (!(host->flags & HOST_F_RECV))
384 if (host->pio.index < host->dma.len) {
385 sg = &data->sg[host->pio.index];
386 sg_ptr = sg_virt(sg) + host->pio.offset;
388 /* This is the space left inside the buffer */
389 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
391 /* Check to if we need less then the size of the sg_buffer */
392 if (sg_len < max) max = sg_len;
395 if (max > AU1XMMC_MAX_TRANSFER)
396 max = AU1XMMC_MAX_TRANSFER;
398 for(count = 0; count < max; count++ ) {
400 status = au_readl(HOST_STATUS(host));
402 if (!(status & SD_STATUS_NE))
405 if (status & SD_STATUS_RC) {
406 DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
407 host->pio.len, count);
411 if (status & SD_STATUS_RO) {
412 DBG("RX Overrun [%d + %d]\n", host->pdev->id,
413 host->pio.len, count);
416 else if (status & SD_STATUS_RU) {
417 DBG("RX Underrun [%d + %d]\n", host->pdev->id,
418 host->pio.len, count);
422 val = au_readl(HOST_RXPORT(host));
425 *sg_ptr++ = (unsigned char) (val & 0xFF);
428 host->pio.len -= count;
429 host->pio.offset += count;
431 if (sg_len && count == sg_len) {
433 host->pio.offset = 0;
436 if (host->pio.len == 0) {
437 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
438 IRQ_OFF(host, SD_CONFIG_NE);
440 if (host->flags & HOST_F_STOP)
443 tasklet_schedule(&host->data_task);
447 /* static void au1xmmc_cmd_complete
448 This is called when a command has been completed - grab the response
449 and check for errors. Then start the data transfer if it is indicated.
452 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
455 struct mmc_request *mrq = host->mrq;
456 struct mmc_command *cmd;
465 if (cmd->flags & MMC_RSP_PRESENT) {
466 if (cmd->flags & MMC_RSP_136) {
470 r[0] = au_readl(host->iobase + SD_RESP3);
471 r[1] = au_readl(host->iobase + SD_RESP2);
472 r[2] = au_readl(host->iobase + SD_RESP1);
473 r[3] = au_readl(host->iobase + SD_RESP0);
475 /* The CRC is omitted from the response, so really
476 * we only got 120 bytes, but the engine expects
477 * 128 bits, so we have to shift things up
480 for(i = 0; i < 4; i++) {
481 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
483 cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
486 /* Techincally, we should be getting all 48 bits of
487 * the response (SD_RESP1 + SD_RESP2), but because
488 * our response omits the CRC, our data ends up
489 * being shifted 8 bits to the right. In this case,
490 * that means that the OSR data starts at bit 31,
491 * so we can just read RESP0 and return that
493 cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
497 /* Figure out errors */
499 if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
500 cmd->error = -EILSEQ;
502 trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
504 if (!trans || cmd->error) {
506 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
507 tasklet_schedule(&host->finish_task);
511 host->status = HOST_S_DATA;
513 if (host->flags & HOST_F_DMA) {
514 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
515 u32 channel = DMA_CHANNEL(host);
517 /* Start the DMA as soon as the buffer gets something in it */
519 if (host->flags & HOST_F_RECV) {
520 u32 mask = SD_STATUS_DB | SD_STATUS_NE;
522 while((status & mask) != mask)
523 status = au_readl(HOST_STATUS(host));
526 au1xxx_dbdma_start(channel);
531 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
534 unsigned int pbus = get_au1x00_speed();
535 unsigned int divisor;
539 divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
542 pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
545 divisor = ((pbus / rate) / 2) - 1;
547 config = au_readl(HOST_CONFIG(host));
549 config &= ~(SD_CONFIG_DIV);
550 config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
552 au_writel(config, HOST_CONFIG(host));
557 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
559 int datalen = data->blocks * data->blksz;
561 if (data->flags & MMC_DATA_READ)
562 host->flags |= HOST_F_RECV;
564 host->flags |= HOST_F_XMIT;
567 host->flags |= HOST_F_STOP;
569 host->dma.dir = DMA_BIDIRECTIONAL;
571 host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
572 data->sg_len, host->dma.dir);
574 if (host->dma.len == 0)
577 au_writel(data->blksz - 1, HOST_BLKSIZE(host));
579 if (host->flags & HOST_F_DMA) {
580 #ifdef CONFIG_SOC_AU1200 /* DBDMA */
582 u32 channel = DMA_CHANNEL(host);
584 au1xxx_dbdma_stop(channel);
586 for(i = 0; i < host->dma.len; i++) {
587 u32 ret = 0, flags = DDMA_FLAGS_NOIE;
588 struct scatterlist *sg = &data->sg[i];
589 int sg_len = sg->length;
591 int len = (datalen > sg_len) ? sg_len : datalen;
593 if (i == host->dma.len - 1)
594 flags = DDMA_FLAGS_IE;
596 if (host->flags & HOST_F_XMIT){
597 ret = au1xxx_dbdma_put_source_flags(channel,
598 (void *) sg_virt(sg), len, flags);
601 ret = au1xxx_dbdma_put_dest_flags(channel,
602 (void *) sg_virt(sg),
615 host->pio.offset = 0;
616 host->pio.len = datalen;
618 if (host->flags & HOST_F_XMIT)
619 IRQ_ON(host, SD_CONFIG_TH);
621 IRQ_ON(host, SD_CONFIG_NE);
622 //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
628 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
633 /* static void au1xmmc_request
634 This actually starts a command or data transaction
637 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
640 struct au1xmmc_host *host = mmc_priv(mmc);
641 unsigned int flags = 0;
644 WARN_ON(irqs_disabled());
645 WARN_ON(host->status != HOST_S_IDLE);
648 host->status = HOST_S_CMD;
652 flags = mrq->data->flags;
653 ret = au1xmmc_prepare_data(host, mrq->data);
657 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
660 mrq->cmd->error = ret;
661 au1xmmc_finish_request(host);
665 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
668 /* Apply the clock */
669 au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
672 au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
675 au_writel(~0, HOST_STATUS(host));
678 au_writel(0, HOST_BLKSIZE(host));
679 au_writel(0x001fffff, HOST_TIMEOUT(host));
682 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
685 au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
688 au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
691 /* Configure interrupts */
692 au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
697 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
699 struct au1xmmc_host *host = mmc_priv(mmc);
701 if (ios->power_mode == MMC_POWER_OFF)
702 au1xmmc_set_power(host, 0);
703 else if (ios->power_mode == MMC_POWER_ON) {
704 au1xmmc_set_power(host, 1);
707 if (ios->clock && ios->clock != host->clock) {
708 au1xmmc_set_clock(host, ios->clock);
709 host->clock = ios->clock;
713 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
714 #define STATUS_DATA_IN (SD_STATUS_NE)
715 #define STATUS_DATA_OUT (SD_STATUS_TH)
717 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
719 struct au1xmmc_host *host = dev_id;
722 status = au_readl(HOST_STATUS(host));
724 if (!(status & SD_STATUS_I))
725 return IRQ_NONE; /* not ours */
727 if (host->mrq && (status & STATUS_TIMEOUT)) {
728 if (status & SD_STATUS_RAT)
729 host->mrq->cmd->error = -ETIMEDOUT;
730 else if (status & SD_STATUS_DT)
731 host->mrq->data->error = -ETIMEDOUT;
733 /* In PIO mode, interrupts might still be enabled */
734 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
736 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
737 tasklet_schedule(&host->finish_task);
740 else if (status & SD_STATUS_DD) {
741 /* Sometimes we get a DD before a NE in PIO mode */
742 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
743 au1xmmc_receive_pio(host);
745 au1xmmc_data_complete(host, status);
746 /* tasklet_schedule(&host->data_task); */
750 else if (status & SD_STATUS_CR) {
751 if (host->status == HOST_S_CMD)
752 au1xmmc_cmd_complete(host, status);
754 } else if (!(host->flags & HOST_F_DMA)) {
755 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
756 au1xmmc_send_pio(host);
757 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
758 au1xmmc_receive_pio(host);
760 } else if (status & 0x203F3C70) {
761 DBG("Unhandled status %8.8x\n", host->pdev->id,
765 au_writel(status, HOST_STATUS(host));
771 #ifdef CONFIG_SOC_AU1200
772 /* 8bit memory DMA device */
773 static dbdev_tab_t au1xmmc_mem_dbdev = {
774 .dev_id = DSCR_CMD0_ALWAYS,
775 .dev_flags = DEV_FLAGS_ANYUSE,
778 .dev_physaddr = 0x00000000,
780 .dev_intpolarity = 0,
784 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
786 struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
788 /* Avoid spurious interrupts */
792 if (host->flags & HOST_F_STOP)
795 tasklet_schedule(&host->data_task);
798 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
800 struct resource *res;
803 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
808 res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
816 host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
817 au1xmmc_dbdma_callback, (void *)host);
818 if (!host->tx_chan) {
819 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
823 host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
824 au1xmmc_dbdma_callback, (void *)host);
825 if (!host->rx_chan) {
826 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
827 au1xxx_dbdma_chan_free(host->tx_chan);
831 au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
832 au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
834 au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
835 au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
837 /* DBDMA is good to go */
838 host->flags |= HOST_F_DMA;
843 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
845 if (host->flags & HOST_F_DMA) {
846 host->flags &= ~HOST_F_DMA;
847 au1xxx_dbdma_chan_free(host->tx_chan);
848 au1xxx_dbdma_chan_free(host->rx_chan);
853 static const struct mmc_host_ops au1xmmc_ops = {
854 .request = au1xmmc_request,
855 .set_ios = au1xmmc_set_ios,
856 .get_ro = au1xmmc_card_readonly,
859 static void au1xmmc_poll_event(unsigned long arg)
861 struct au1xmmc_host *host = (struct au1xmmc_host *)arg;
862 int card = au1xmmc_card_inserted(host);
863 int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
865 if (card != controller) {
866 host->flags &= ~HOST_F_ACTIVE;
868 host->flags |= HOST_F_ACTIVE;
869 mmc_detect_change(host->mmc, 0);
873 if (host->mrq != NULL) {
874 u32 status = au_readl(HOST_STATUS(host));
875 DBG("PENDING - %8.8x\n", host->pdev->id, status);
878 mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
881 static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host)
883 init_timer(&host->timer);
884 host->timer.function = au1xmmc_poll_event;
885 host->timer.data = (unsigned long)host;
886 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
889 static int __devinit au1xmmc_probe(struct platform_device *pdev)
891 struct mmc_host *mmc;
892 struct au1xmmc_host *host;
896 mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
898 dev_err(&pdev->dev, "no memory for mmc_host\n");
903 host = mmc_priv(mmc);
905 host->platdata = pdev->dev.platform_data;
909 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911 dev_err(&pdev->dev, "no mmio defined\n");
915 host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
918 dev_err(&pdev->dev, "mmio already in use\n");
922 host->iobase = (unsigned long)ioremap(r->start, 0x3c);
924 dev_err(&pdev->dev, "cannot remap mmio\n");
928 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
930 dev_err(&pdev->dev, "no IRQ defined\n");
934 host->irq = r->start;
935 /* IRQ is shared among both SD controllers */
936 ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
939 dev_err(&pdev->dev, "cannot grab IRQ\n");
943 mmc->ops = &au1xmmc_ops;
946 mmc->f_max = 24000000;
948 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
949 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
951 mmc->max_blk_size = 2048;
952 mmc->max_blk_count = 512;
954 mmc->ocr_avail = AU1XMMC_OCR;
957 host->status = HOST_S_IDLE;
959 /* board-specific carddetect setup, if any */
960 if (host->platdata && host->platdata->cd_setup) {
961 ret = host->platdata->cd_setup(mmc, 1);
963 dev_err(&pdev->dev, "board CD setup failed\n");
967 /* poll the board-specific is-card-in-socket-? method */
968 au1xmmc_init_cd_poll_timer(host);
971 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
972 (unsigned long)host);
974 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
975 (unsigned long)host);
977 #ifdef CONFIG_SOC_AU1200
978 ret = au1xmmc_dbdma_init(host);
980 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
983 #ifdef CONFIG_LEDS_CLASS
984 if (host->platdata && host->platdata->led) {
985 struct led_classdev *led = host->platdata->led;
986 led->name = mmc_hostname(mmc);
987 led->brightness = LED_OFF;
988 led->default_trigger = mmc_hostname(mmc);
989 ret = led_classdev_register(mmc_dev(mmc), led);
995 au1xmmc_reset_controller(host);
997 ret = mmc_add_host(mmc);
999 dev_err(&pdev->dev, "cannot add mmc host\n");
1003 platform_set_drvdata(pdev, mmc);
1005 /* start the carddetect poll timer if necessary */
1006 if (!(host->platdata && host->platdata->cd_setup))
1007 add_timer(&host->timer);
1009 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1010 " (mode=%s)\n", pdev->id, host->iobase,
1011 host->flags & HOST_F_DMA ? "dma" : "pio");
1013 return 0; /* all ok */
1016 #ifdef CONFIG_LEDS_CLASS
1017 if (host->platdata && host->platdata->led)
1018 led_classdev_unregister(host->platdata->led);
1021 au_writel(0, HOST_ENABLE(host));
1022 au_writel(0, HOST_CONFIG(host));
1023 au_writel(0, HOST_CONFIG2(host));
1026 #ifdef CONFIG_SOC_AU1200
1027 au1xmmc_dbdma_shutdown(host);
1030 tasklet_kill(&host->data_task);
1031 tasklet_kill(&host->finish_task);
1033 if (host->platdata && host->platdata->cd_setup)
1034 host->platdata->cd_setup(mmc, 0);
1036 free_irq(host->irq, host);
1038 iounmap((void *)host->iobase);
1040 release_resource(host->ioarea);
1041 kfree(host->ioarea);
1048 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1050 struct mmc_host *mmc = platform_get_drvdata(pdev);
1051 struct au1xmmc_host *host;
1054 host = mmc_priv(mmc);
1056 mmc_remove_host(mmc);
1058 #ifdef CONFIG_LEDS_CLASS
1059 if (host->platdata && host->platdata->led)
1060 led_classdev_unregister(host->platdata->led);
1063 if (host->platdata && host->platdata->cd_setup)
1064 host->platdata->cd_setup(mmc, 0);
1066 del_timer_sync(&host->timer);
1068 au_writel(0, HOST_ENABLE(host));
1069 au_writel(0, HOST_CONFIG(host));
1070 au_writel(0, HOST_CONFIG2(host));
1073 tasklet_kill(&host->data_task);
1074 tasklet_kill(&host->finish_task);
1076 #ifdef CONFIG_SOC_AU1200
1077 au1xmmc_dbdma_shutdown(host);
1079 au1xmmc_set_power(host, 0);
1081 free_irq(host->irq, host);
1082 iounmap((void *)host->iobase);
1083 release_resource(host->ioarea);
1084 kfree(host->ioarea);
1091 static struct platform_driver au1xmmc_driver = {
1092 .probe = au1xmmc_probe,
1093 .remove = au1xmmc_remove,
1097 .name = DRIVER_NAME,
1098 .owner = THIS_MODULE,
1102 static int __init au1xmmc_init(void)
1104 #ifdef CONFIG_SOC_AU1200
1105 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1106 * of 8 bits. And since devices are shared, we need to create
1107 * our own to avoid freaking out other devices.
1109 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1111 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1113 return platform_driver_register(&au1xmmc_driver);
1116 static void __exit au1xmmc_exit(void)
1118 #ifdef CONFIG_SOC_AU1200
1120 au1xxx_ddma_del_device(memid);
1122 platform_driver_unregister(&au1xmmc_driver);
1125 module_init(au1xmmc_init);
1126 module_exit(au1xmmc_exit);
1128 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1129 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1130 MODULE_LICENSE("GPL");
1131 MODULE_ALIAS("platform:au1xxx-mmc");