2 * bfin_sdh.c - Analog Devices Blackfin SDH Controller
4 * Copyright (C) 2007-2009 Analog Device Inc.
6 * Licensed under the GPL-2 or later.
9 #define DRIVER_NAME "bfin-sdh"
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/proc_fs.h>
20 #include <linux/gfp.h>
22 #include <asm/cacheflush.h>
24 #include <asm/portmux.h>
25 #include <asm/bfin_sdh.h>
27 #if defined(CONFIG_BF51x) || defined(__ADSPBF60x__)
28 #define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
29 #define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
30 #define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
31 #define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
32 #define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
33 #define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
34 #define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
35 #define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
36 #define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
37 #define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
38 #define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
39 #define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
40 #define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
41 #define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
42 #define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
43 #define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
44 #define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
45 #define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
46 #define bfin_write_SDH_E_MASK bfin_write_RSI_E_MASK
47 #define bfin_read_SDH_CFG bfin_read_RSI_CFG
48 #define bfin_write_SDH_CFG bfin_write_RSI_CFG
49 # if defined(__ADSPBF60x__)
50 # define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
51 # define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
53 # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
54 # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
67 struct dma_desc_array *sg_cpu;
73 unsigned int power_mode;
76 struct mmc_request *mrq;
77 struct mmc_command *cmd;
78 struct mmc_data *data;
81 static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
83 return pdev->dev.platform_data;
86 static void sdh_stop_clock(struct sdh_host *host)
88 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
92 static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
96 spin_lock_irqsave(&host->lock, flags);
98 bfin_write_SDH_MASK0(mask);
100 spin_unlock_irqrestore(&host->lock, flags);
103 static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
107 spin_lock_irqsave(&host->lock, flags);
108 host->imask &= ~mask;
109 bfin_write_SDH_MASK0(host->imask);
111 spin_unlock_irqrestore(&host->lock, flags);
114 static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
117 unsigned int data_ctl;
118 unsigned int dma_cfg;
119 unsigned int cycle_ns, timeout;
121 dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
126 length = data->blksz * data->blocks;
127 bfin_write_SDH_DATA_LGTH(length);
129 if (data->flags & MMC_DATA_STREAM)
130 data_ctl |= DTX_MODE;
132 if (data->flags & MMC_DATA_READ)
134 /* Only supports power-of-2 block size */
135 if (data->blksz & (data->blksz - 1))
138 data_ctl |= ((ffs(data->blksz) - 1) << 4);
140 bfin_write_SDH_BLK_SIZE(data->blksz);
143 bfin_write_SDH_DATA_CTL(data_ctl);
144 /* the time of a host clock period in ns */
145 cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1)));
146 timeout = data->timeout_ns / cycle_ns;
147 timeout += data->timeout_clks;
148 bfin_write_SDH_DATA_TIMER(timeout);
151 if (data->flags & MMC_DATA_READ) {
152 host->dma_dir = DMA_FROM_DEVICE;
155 host->dma_dir = DMA_TO_DEVICE;
157 sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
158 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
159 #if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
160 dma_cfg |= DMAFLOW_ARRAY | RESTART | WDSIZE_32 | DMAEN;
162 dma_cfg |= PSIZE_32 | NDSIZE_3;
167 struct scatterlist *sg;
169 for_each_sg(data->sg, sg, host->dma_len, i) {
170 host->sg_cpu[i].start_addr = sg_dma_address(sg);
171 host->sg_cpu[i].cfg = dma_cfg;
172 host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
173 host->sg_cpu[i].x_modify = 4;
174 dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
175 "cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
176 i, host->sg_cpu[i].start_addr,
177 host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
178 host->sg_cpu[i].x_modify);
181 flush_dcache_range((unsigned int)host->sg_cpu,
182 (unsigned int)host->sg_cpu +
183 host->dma_len * sizeof(struct dma_desc_array));
184 /* Set the last descriptor to stop mode */
185 host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
186 host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
188 set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
189 set_dma_x_count(host->dma_ch, 0);
190 set_dma_x_modify(host->dma_ch, 0);
192 set_dma_config(host->dma_ch, dma_cfg);
193 #elif defined(CONFIG_BF51x)
194 /* RSI DMA doesn't work in array mode */
195 dma_cfg |= WDSIZE_32 | DMAEN;
196 set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
197 set_dma_x_count(host->dma_ch, length / 4);
198 set_dma_x_modify(host->dma_ch, 4);
200 set_dma_config(host->dma_ch, dma_cfg);
202 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
206 dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
210 static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
212 unsigned int sdh_cmd;
213 unsigned int stat_mask;
215 dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
216 WARN_ON(host->cmd != NULL);
222 sdh_cmd |= cmd->opcode;
224 if (cmd->flags & MMC_RSP_PRESENT) {
226 stat_mask |= CMD_RESP_END;
228 stat_mask |= CMD_SENT;
231 if (cmd->flags & MMC_RSP_136)
232 sdh_cmd |= CMD_L_RSP;
234 stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
236 sdh_enable_stat_irq(host, stat_mask);
238 bfin_write_SDH_ARGUMENT(cmd->arg);
239 bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
240 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
244 static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
246 dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
250 mmc_request_done(host->mmc, mrq);
253 static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
255 struct mmc_command *cmd = host->cmd;
258 dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
264 if (cmd->flags & MMC_RSP_PRESENT) {
265 cmd->resp[0] = bfin_read_SDH_RESPONSE0();
266 if (cmd->flags & MMC_RSP_136) {
267 cmd->resp[1] = bfin_read_SDH_RESPONSE1();
268 cmd->resp[2] = bfin_read_SDH_RESPONSE2();
269 cmd->resp[3] = bfin_read_SDH_RESPONSE3();
272 if (stat & CMD_TIME_OUT)
273 cmd->error = -ETIMEDOUT;
274 else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
275 cmd->error = -EILSEQ;
277 sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
279 if (host->data && !cmd->error) {
280 if (host->data->flags & MMC_DATA_WRITE) {
281 ret = sdh_setup_data(host, host->data);
286 sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
288 sdh_finish_request(host, host->mrq);
293 static int sdh_data_done(struct sdh_host *host, unsigned int stat)
295 struct mmc_data *data = host->data;
297 dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
301 disable_dma(host->dma_ch);
302 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
305 if (stat & DAT_TIME_OUT)
306 data->error = -ETIMEDOUT;
307 else if (stat & DAT_CRC_FAIL)
308 data->error = -EILSEQ;
309 else if (stat & (RX_OVERRUN | TX_UNDERRUN))
313 data->bytes_xfered = data->blocks * data->blksz;
315 data->bytes_xfered = 0;
317 bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
318 DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
319 bfin_write_SDH_DATA_CTL(0);
323 if (host->mrq->stop) {
324 sdh_stop_clock(host);
325 sdh_start_cmd(host, host->mrq->stop);
327 sdh_finish_request(host, host->mrq);
333 static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
335 struct sdh_host *host = mmc_priv(mmc);
338 dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
339 WARN_ON(host->mrq != NULL);
341 spin_lock(&host->lock);
343 host->data = mrq->data;
345 if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
346 ret = sdh_setup_data(host, mrq->data);
351 sdh_start_cmd(host, mrq->cmd);
353 spin_unlock(&host->lock);
356 static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
358 struct sdh_host *host;
364 host = mmc_priv(mmc);
366 spin_lock(&host->lock);
368 cfg = bfin_read_SDH_CFG();
370 switch (ios->bus_width) {
371 case MMC_BUS_WIDTH_4:
376 /* Enable 4 bit SDIO */
378 clk_ctl |= WIDE_BUS_4;
380 case MMC_BUS_WIDTH_8:
385 /* Disable 4 bit SDIO */
387 clk_ctl |= BYTE_BUS_8;
391 /* Disable 4 bit SDIO */
395 host->power_mode = ios->power_mode;
397 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
399 # ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
400 pwr_ctl |= SD_CMD_OD;
404 if (ios->power_mode != MMC_POWER_OFF)
409 bfin_write_SDH_PWR_CTL(pwr_ctl);
411 # ifndef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
412 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
419 if (ios->power_mode != MMC_POWER_OFF)
424 bfin_write_SDH_CFG(cfg);
428 if (ios->power_mode == MMC_POWER_ON && ios->clock) {
429 unsigned char clk_div;
430 clk_div = (get_sclk() / ios->clock - 1) / 2;
431 clk_div = min_t(unsigned char, clk_div, 0xFF);
434 host->clk_div = clk_div;
435 bfin_write_SDH_CLK_CTL(clk_ctl);
438 sdh_stop_clock(host);
440 /* set up sdh interrupt mask*/
441 if (ios->power_mode == MMC_POWER_ON)
442 bfin_write_SDH_MASK0(DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
443 RX_OVERRUN | TX_UNDERRUN | CMD_SENT | CMD_RESP_END |
444 CMD_TIME_OUT | CMD_CRC_FAIL);
446 bfin_write_SDH_MASK0(0);
449 spin_unlock(&host->lock);
451 dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
453 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
457 static const struct mmc_host_ops sdh_ops = {
458 .request = sdh_request,
459 .set_ios = sdh_set_ios,
462 static irqreturn_t sdh_dma_irq(int irq, void *devid)
464 struct sdh_host *host = devid;
466 dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04lx\n", __func__,
467 get_dma_curr_irqstat(host->dma_ch));
468 clear_dma_irqstat(host->dma_ch);
474 static irqreturn_t sdh_stat_irq(int irq, void *devid)
476 struct sdh_host *host = devid;
480 dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
482 spin_lock(&host->lock);
484 status = bfin_read_SDH_E_STATUS();
485 if (status & SD_CARD_DET) {
486 mmc_detect_change(host->mmc, 0);
487 bfin_write_SDH_E_STATUS(SD_CARD_DET);
489 status = bfin_read_SDH_STATUS();
490 if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
491 handled |= sdh_cmd_done(host, status);
492 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
493 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
497 status = bfin_read_SDH_STATUS();
498 if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
499 handled |= sdh_data_done(host, status);
501 spin_unlock(&host->lock);
503 dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
505 return IRQ_RETVAL(handled);
508 static void sdh_reset(void)
510 #if defined(CONFIG_BF54x)
511 /* Secure Digital Host shares DMA with Nand controller */
512 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
515 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
518 /* Disable card inserting detection pin. set MMC_CAP_NEEDS_POLL, and
519 * mmc stack will do the detection.
521 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
525 static int sdh_probe(struct platform_device *pdev)
527 struct mmc_host *mmc;
528 struct sdh_host *host;
529 struct bfin_sd_host *drv_data = get_sdh_data(pdev);
533 dev_err(&pdev->dev, "missing platform driver data\n");
538 mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
545 #if defined(CONFIG_BF51x)
548 mmc->max_segs = PAGE_SIZE / sizeof(struct dma_desc_array);
551 mmc->max_seg_size = -1;
553 mmc->max_seg_size = 1 << 16;
555 mmc->max_blk_size = 1 << 11;
556 mmc->max_blk_count = 1 << 11;
557 mmc->max_req_size = PAGE_SIZE;
558 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
559 mmc->f_max = get_sclk();
560 mmc->f_min = mmc->f_max >> 9;
561 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
562 host = mmc_priv(mmc);
564 host->sclk = get_sclk();
566 spin_lock_init(&host->lock);
567 host->irq = drv_data->irq_int0;
568 host->dma_ch = drv_data->dma_chan;
570 ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
572 dev_err(&pdev->dev, "unable to request DMA channel\n");
576 ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
578 dev_err(&pdev->dev, "unable to request DMA irq\n");
582 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
583 if (host->sg_cpu == NULL) {
588 platform_set_drvdata(pdev, mmc);
590 ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
592 dev_err(&pdev->dev, "unable to request status irq\n");
596 ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
598 dev_err(&pdev->dev, "unable to request peripheral pins\n");
608 free_irq(host->irq, host);
610 mmc_remove_host(mmc);
611 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
613 free_dma(host->dma_ch);
620 static int sdh_remove(struct platform_device *pdev)
622 struct mmc_host *mmc = platform_get_drvdata(pdev);
625 struct sdh_host *host = mmc_priv(mmc);
627 mmc_remove_host(mmc);
629 sdh_stop_clock(host);
630 free_irq(host->irq, host);
631 free_dma(host->dma_ch);
632 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
641 static int sdh_suspend(struct platform_device *dev, pm_message_t state)
643 struct mmc_host *mmc = platform_get_drvdata(dev);
644 struct bfin_sd_host *drv_data = get_sdh_data(dev);
648 ret = mmc_suspend_host(mmc);
650 peripheral_free_list(drv_data->pin_req);
655 static int sdh_resume(struct platform_device *dev)
657 struct mmc_host *mmc = platform_get_drvdata(dev);
658 struct bfin_sd_host *drv_data = get_sdh_data(dev);
661 ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
663 dev_err(&dev->dev, "unable to request peripheral pins\n");
670 ret = mmc_resume_host(mmc);
675 # define sdh_suspend NULL
676 # define sdh_resume NULL
679 static struct platform_driver sdh_driver = {
681 .remove = sdh_remove,
682 .suspend = sdh_suspend,
683 .resume = sdh_resume,
689 module_platform_driver(sdh_driver);
691 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
692 MODULE_AUTHOR("Cliff Cai, Roy Huang");
693 MODULE_LICENSE("GPL");