drivers/mmc/host/dw_mmc-exynos.c

   1 /*
   2  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2012, Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/dw_mmc.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include "dw_mmc.h"
  21 #include "dw_mmc-pltfm.h"
  22
  23 #define NUM_PINS(x)                     (x + 2)
  24
  25 #define SDMMC_CLKSEL                    0x09C
  26 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)     (((x) & 7) << 0)
  27 #define SDMMC_CLKSEL_CCLK_DRIVE(x)      (((x) & 7) << 16)
  28 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)    (((x) & 7) << 24)
  29 #define SDMMC_CLKSEL_GET_DRV_WD3(x)     (((x) >> 16) & 0x7)
  30 #define SDMMC_CLKSEL_TIMING(x, y, z)    (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
  31                                         SDMMC_CLKSEL_CCLK_DRIVE(y) |    \
  32                                         SDMMC_CLKSEL_CCLK_DIVIDER(z))
  33
  34 #define EXYNOS4210_FIXED_CIU_CLK_DIV    2
  35 #define EXYNOS4412_FIXED_CIU_CLK_DIV    4
  36
  37 /* Variations in Exynos specific dw-mshc controller */
  38 enum dw_mci_exynos_type {
  39         DW_MCI_TYPE_EXYNOS4210,
  40         DW_MCI_TYPE_EXYNOS4412,
  41         DW_MCI_TYPE_EXYNOS5250,
  42 };
  43
  44 /* Exynos implementation specific driver private data */
  45 struct dw_mci_exynos_priv_data {
  46         enum dw_mci_exynos_type         ctrl_type;
  47         u8                              ciu_div;
  48         u32                             sdr_timing;
  49         u32                             ddr_timing;
  50 };
  51
  52 static struct dw_mci_exynos_compatible {
  53         char                            *compatible;
  54         enum dw_mci_exynos_type         ctrl_type;
  55 } exynos_compat[] = {
  56         {
  57                 .compatible     = "samsung,exynos4210-dw-mshc",
  58                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4210,
  59         }, {
  60                 .compatible     = "samsung,exynos4412-dw-mshc",
  61                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4412,
  62         }, {
  63                 .compatible     = "samsung,exynos5250-dw-mshc",
  64                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5250,
  65         },
  66 };
  67
  68 static int dw_mci_exynos_priv_init(struct dw_mci *host)
  69 {
  70         struct dw_mci_exynos_priv_data *priv;
  71         int idx;
  72
  73         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  74         if (!priv) {
  75                 dev_err(host->dev, "mem alloc failed for private data\n");
  76                 return -ENOMEM;
  77         }
  78
  79         for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
  80                 if (of_device_is_compatible(host->dev->of_node,
  81                                         exynos_compat[idx].compatible))
  82                         priv->ctrl_type = exynos_compat[idx].ctrl_type;
  83         }
  84
  85         host->priv = priv;
  86         return 0;
  87 }
  88
  89 static int dw_mci_exynos_setup_clock(struct dw_mci *host)
  90 {
  91         struct dw_mci_exynos_priv_data *priv = host->priv;
  92
  93         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
  94                 host->bus_hz /= (priv->ciu_div + 1);
  95         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  96                 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
  97         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
  98                 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
  99
 100         return 0;
 101 }
 102
 103 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
 104 {
 105         /*
 106          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 107          * use of bit 29 (which is reserved on standard MSHC controllers) for
 108          * optionally bypassing the HOLD register for command and data. The
 109          * HOLD register should be bypassed in case there is no phase shift
 110          * applied on CMD/DATA that is sent to the card.
 111          */
 112         if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
 113                 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
 114 }
 115
 116 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 117 {
 118         struct dw_mci_exynos_priv_data *priv = host->priv;
 119
 120         if (ios->timing == MMC_TIMING_UHS_DDR50)
 121                 mci_writel(host, CLKSEL, priv->ddr_timing);
 122         else
 123                 mci_writel(host, CLKSEL, priv->sdr_timing);
 124 }
 125
 126 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 127 {
 128         struct dw_mci_exynos_priv_data *priv = host->priv;
 129         struct device_node *np = host->dev->of_node;
 130         u32 timing[2];
 131         u32 div = 0;
 132         int ret;
 133
 134         of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 135         priv->ciu_div = div;
 136
 137         ret = of_property_read_u32_array(np,
 138                         "samsung,dw-mshc-sdr-timing", timing, 2);
 139         if (ret)
 140                 return ret;
 141
 142         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 143
 144         ret = of_property_read_u32_array(np,
 145                         "samsung,dw-mshc-ddr-timing", timing, 2);
 146         if (ret)
 147                 return ret;
 148
 149         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 150         return 0;
 151 }
 152
 153 /* Common capabilities of Exynos4/Exynos5 SoC */
 154 static unsigned long exynos_dwmmc_caps[4] = {
 155         MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
 156                 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 157         MMC_CAP_CMD23,
 158         MMC_CAP_CMD23,
 159         MMC_CAP_CMD23,
 160 };
 161
 162 static const struct dw_mci_drv_data exynos_drv_data = {
 163         .caps                   = exynos_dwmmc_caps,
 164         .init                   = dw_mci_exynos_priv_init,
 165         .setup_clock            = dw_mci_exynos_setup_clock,
 166         .prepare_command        = dw_mci_exynos_prepare_command,
 167         .set_ios                = dw_mci_exynos_set_ios,
 168         .parse_dt               = dw_mci_exynos_parse_dt,
 169 };
 170
 171 static const struct of_device_id dw_mci_exynos_match[] = {
 172         { .compatible = "samsung,exynos4412-dw-mshc",
 173                         .data = &exynos_drv_data, },
 174         { .compatible = "samsung,exynos5250-dw-mshc",
 175                         .data = &exynos_drv_data, },
 176         {},
 177 };
 178 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
 179
 180 static int dw_mci_exynos_probe(struct platform_device *pdev)
 181 {
 182         const struct dw_mci_drv_data *drv_data;
 183         const struct of_device_id *match;
 184
 185         match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
 186         drv_data = match->data;
 187         return dw_mci_pltfm_register(pdev, drv_data);
 188 }
 189
 190 static struct platform_driver dw_mci_exynos_pltfm_driver = {
 191         .probe          = dw_mci_exynos_probe,
 192         .remove         = __exit_p(dw_mci_pltfm_remove),
 193         .driver         = {
 194                 .name           = "dwmmc_exynos",
 195                 .of_match_table = dw_mci_exynos_match,
 196                 .pm             = &dw_mci_pltfm_pmops,
 197         },
 198 };
 199
 200 module_platform_driver(dw_mci_exynos_pltfm_driver);
 201
 202 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
 203 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
 204 MODULE_LICENSE("GPL v2");
 205 MODULE_ALIAS("platform:dwmmc-exynos");