2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/dw_mmc.h>
15 #include <linux/of_address.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/slab.h>
20 #include "dw_mmc-pltfm.h"
22 #define RK3288_CLKGEN_DIV 2
24 struct dw_mci_rockchip_priv_data {
26 struct clk *sample_clk;
27 int default_sample_phase;
30 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
32 struct dw_mci_rockchip_priv_data *priv = host->priv;
41 * cclkin: source clock of mmc controller
42 * bus_hz: card interface clock generated by CLKGEN
43 * bus_hz = cclkin / RK3288_CLKGEN_DIV
44 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
46 * Note: div can only be 0 or 1
47 * if DDR50 8bit mode(only emmc work in 8bit mode),
50 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
51 ios->timing == MMC_TIMING_MMC_DDR52)
52 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
54 cclkin = ios->clock * RK3288_CLKGEN_DIV;
56 ret = clk_set_rate(host->ciu_clk, cclkin);
58 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
60 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
61 if (bus_hz != host->bus_hz) {
62 host->bus_hz = bus_hz;
63 /* force dw_mci_setup_bus() */
64 host->current_speed = 0;
67 /* Make sure we use phases which we can enumerate with */
68 if (!IS_ERR(priv->sample_clk))
69 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
72 * Set the drive phase offset based on speed mode to achieve hold times.
74 * NOTE: this is _not_ a value that is dynamically tuned and is also
75 * _not_ a value that will vary from board to board. It is a value
76 * that could vary between different SoC models if they had massively
77 * different output clock delays inside their dw_mmc IP block (delay_o),
78 * but since it's OK to overshoot a little we don't need to do complex
79 * calculations and can pick values that will just work for everyone.
81 * When picking values we'll stick with picking 0/90/180/270 since
82 * those can be made very accurately on all known Rockchip SoCs.
84 * Note that these values match values from the DesignWare Databook
85 * tables for the most part except for SDR12 and "ID mode". For those
86 * two modes the databook calculations assume a clock in of 50MHz. As
87 * seen above, we always use a clock in rate that is exactly the
88 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
89 * back out before the controller sees it).
91 * From measurement of a single device, it appears that delay_o is
92 * about .5 ns. Since we try to leave a bit of margin, it's expected
93 * that numbers here will be fine even with much larger delay_o
94 * (the 1.4 ns assumed by the DesignWare Databook would result in the
95 * same results, for instance).
97 if (!IS_ERR(priv->drv_clk)) {
101 * In almost all cases a 90 degree phase offset will provide
102 * sufficient hold times across all valid input clock rates
103 * assuming delay_o is not absurd for a given SoC. We'll use
108 switch (ios->timing) {
109 case MMC_TIMING_MMC_DDR52:
111 * Since clock in rate with MMC_DDR52 is doubled when
112 * bus width is 8 we need to double the phase offset
113 * to get the same timings.
115 if (ios->bus_width == MMC_BUS_WIDTH_8)
118 case MMC_TIMING_UHS_SDR104:
119 case MMC_TIMING_MMC_HS200:
121 * In the case of 150 MHz clock (typical max for
122 * Rockchip SoCs), 90 degree offset will add a delay
123 * of 1.67 ns. That will meet min hold time of .8 ns
124 * as long as clock output delay is < .87 ns. On
125 * SoCs measured this seems to be OK, but it doesn't
126 * hurt to give margin here, so we use 180.
132 clk_set_phase(priv->drv_clk, phase);
136 #define NUM_PHASES 360
137 #define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES))
139 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
141 struct dw_mci *host = slot->host;
142 struct dw_mci_rockchip_priv_data *priv = host->priv;
143 struct mmc_host *mmc = slot->mmc;
146 bool v, prev_v = 0, first_v;
149 int end; /* inclusive */
151 struct range_t *ranges;
152 unsigned int range_count = 0;
153 int longest_range_len = -1;
154 int longest_range = -1;
157 if (IS_ERR(priv->sample_clk)) {
158 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
162 ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
166 /* Try each phase and extract good ranges */
167 for (i = 0; i < NUM_PHASES; ) {
168 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
170 v = !mmc_send_tuning(mmc, opcode, NULL);
175 if ((!prev_v) && v) {
177 ranges[range_count-1].start = i;
180 ranges[range_count-1].end = i;
182 } else if (i == NUM_PHASES - 1) {
183 /* No extra skipping rules if we're at the end */
187 * No need to check too close to an invalid
188 * one since testing bad phases is slow. Skip
191 i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
193 /* Always test the last one */
201 if (range_count == 0) {
202 dev_warn(host->dev, "All phases bad!");
207 /* wrap around case, merge the end points */
208 if ((range_count > 1) && first_v && v) {
209 ranges[0].start = ranges[range_count-1].start;
213 if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
214 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
215 dev_info(host->dev, "All phases work, using default phase %d.",
216 priv->default_sample_phase);
220 /* Find the longest range */
221 for (i = 0; i < range_count; i++) {
222 int len = (ranges[i].end - ranges[i].start + 1);
227 if (longest_range_len < len) {
228 longest_range_len = len;
232 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
233 TUNING_ITERATION_TO_PHASE(ranges[i].start),
234 TUNING_ITERATION_TO_PHASE(ranges[i].end),
239 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
240 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
241 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
245 middle_phase = ranges[longest_range].start + longest_range_len / 2;
246 middle_phase %= NUM_PHASES;
247 dev_info(host->dev, "Successfully tuned phase to %d\n",
248 TUNING_ITERATION_TO_PHASE(middle_phase));
250 clk_set_phase(priv->sample_clk,
251 TUNING_ITERATION_TO_PHASE(middle_phase));
258 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
260 struct device_node *np = host->dev->of_node;
261 struct dw_mci_rockchip_priv_data *priv;
263 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
267 if (of_property_read_u32(np, "rockchip,default-sample-phase",
268 &priv->default_sample_phase))
269 priv->default_sample_phase = 0;
271 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
272 if (IS_ERR(priv->drv_clk))
273 dev_dbg(host->dev, "ciu_drv not available\n");
275 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
276 if (IS_ERR(priv->sample_clk))
277 dev_dbg(host->dev, "ciu_sample not available\n");
284 static int dw_mci_rockchip_init(struct dw_mci *host)
286 /* It is slot 8 on Rockchip SoCs */
289 if (of_device_is_compatible(host->dev->of_node,
290 "rockchip,rk3288-dw-mshc"))
291 host->bus_hz /= RK3288_CLKGEN_DIV;
296 /* Common capabilities of RK3288 SoC */
297 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
304 static const struct dw_mci_drv_data rk2928_drv_data = {
305 .init = dw_mci_rockchip_init,
308 static const struct dw_mci_drv_data rk3288_drv_data = {
309 .caps = dw_mci_rk3288_dwmmc_caps,
310 .set_ios = dw_mci_rk3288_set_ios,
311 .execute_tuning = dw_mci_rk3288_execute_tuning,
312 .parse_dt = dw_mci_rk3288_parse_dt,
313 .init = dw_mci_rockchip_init,
316 static const struct of_device_id dw_mci_rockchip_match[] = {
317 { .compatible = "rockchip,rk2928-dw-mshc",
318 .data = &rk2928_drv_data },
319 { .compatible = "rockchip,rk3288-dw-mshc",
320 .data = &rk3288_drv_data },
323 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
325 static int dw_mci_rockchip_probe(struct platform_device *pdev)
327 const struct dw_mci_drv_data *drv_data;
328 const struct of_device_id *match;
331 if (!pdev->dev.of_node)
334 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
335 drv_data = match->data;
337 pm_runtime_get_noresume(&pdev->dev);
338 pm_runtime_set_active(&pdev->dev);
339 pm_runtime_enable(&pdev->dev);
340 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
341 pm_runtime_use_autosuspend(&pdev->dev);
343 ret = dw_mci_pltfm_register(pdev, drv_data);
345 pm_runtime_disable(&pdev->dev);
346 pm_runtime_set_suspended(&pdev->dev);
347 pm_runtime_put_noidle(&pdev->dev);
351 pm_runtime_put_autosuspend(&pdev->dev);
356 static int dw_mci_rockchip_remove(struct platform_device *pdev)
358 pm_runtime_get_sync(&pdev->dev);
359 pm_runtime_disable(&pdev->dev);
360 pm_runtime_put_noidle(&pdev->dev);
362 return dw_mci_pltfm_remove(pdev);
365 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
366 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
367 pm_runtime_force_resume)
368 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
369 dw_mci_runtime_resume,
373 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
374 .probe = dw_mci_rockchip_probe,
375 .remove = dw_mci_rockchip_remove,
377 .name = "dwmmc_rockchip",
378 .of_match_table = dw_mci_rockchip_match,
379 .pm = &dw_mci_rockchip_dev_pm_ops,
383 module_platform_driver(dw_mci_rockchip_pltfm_driver);
385 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
386 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
387 MODULE_ALIAS("platform:dwmmc_rockchip");
388 MODULE_LICENSE("GPL v2");