drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/mmc/dw_mmc.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/workqueue.h>
  36
  37 #include "dw_mmc.h"
  38
  39 /* Common flag combinations */
  40 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  41                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  42                                  SDMMC_INT_EBE)
  43 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  44                                  SDMMC_INT_RESP_ERR)
  45 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  46                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  47 #define DW_MCI_SEND_STATUS      1
  48 #define DW_MCI_RECV_STATUS      2
  49 #define DW_MCI_DMA_THRESHOLD    16
  50
  51 #ifdef CONFIG_MMC_DW_IDMAC
  52 struct idmac_desc {
  53         u32             des0;   /* Control Descriptor */
  54 #define IDMAC_DES0_DIC  BIT(1)
  55 #define IDMAC_DES0_LD   BIT(2)
  56 #define IDMAC_DES0_FD   BIT(3)
  57 #define IDMAC_DES0_CH   BIT(4)
  58 #define IDMAC_DES0_ER   BIT(5)
  59 #define IDMAC_DES0_CES  BIT(30)
  60 #define IDMAC_DES0_OWN  BIT(31)
  61
  62         u32             des1;   /* Buffer sizes */
  63 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  64         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  65
  66         u32             des2;   /* buffer 1 physical address */
  67
  68         u32             des3;   /* buffer 2 physical address */
  69 };
  70 #endif /* CONFIG_MMC_DW_IDMAC */
  71
  72 /**
  73  * struct dw_mci_slot - MMC slot state
  74  * @mmc: The mmc_host representing this slot.
  75  * @host: The MMC controller this slot is using.
  76  * @ctype: Card type for this slot.
  77  * @mrq: mmc_request currently being processed or waiting to be
  78  *      processed, or NULL when the slot is idle.
  79  * @queue_node: List node for placing this node in the @queue list of
  80  *      &struct dw_mci.
  81  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  82  * @flags: Random state bits associated with the slot.
  83  * @id: Number of this slot.
  84  * @last_detect_state: Most recently observed card detect state.
  85  */
  86 struct dw_mci_slot {
  87         struct mmc_host         *mmc;
  88         struct dw_mci           *host;
  89
  90         u32                     ctype;
  91
  92         struct mmc_request      *mrq;
  93         struct list_head        queue_node;
  94
  95         unsigned int            clock;
  96         unsigned long           flags;
  97 #define DW_MMC_CARD_PRESENT     0
  98 #define DW_MMC_CARD_NEED_INIT   1
  99         int                     id;
 100         int                     last_detect_state;
 101 };
 102
 103 #if defined(CONFIG_DEBUG_FS)
 104 static int dw_mci_req_show(struct seq_file *s, void *v)
 105 {
 106         struct dw_mci_slot *slot = s->private;
 107         struct mmc_request *mrq;
 108         struct mmc_command *cmd;
 109         struct mmc_command *stop;
 110         struct mmc_data *data;
 111
 112         /* Make sure we get a consistent snapshot */
 113         spin_lock_bh(&slot->host->lock);
 114         mrq = slot->mrq;
 115
 116         if (mrq) {
 117                 cmd = mrq->cmd;
 118                 data = mrq->data;
 119                 stop = mrq->stop;
 120
 121                 if (cmd)
 122                         seq_printf(s,
 123                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 124                                    cmd->opcode, cmd->arg, cmd->flags,
 125                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 126                                    cmd->resp[2], cmd->error);
 127                 if (data)
 128                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 129                                    data->bytes_xfered, data->blocks,
 130                                    data->blksz, data->flags, data->error);
 131                 if (stop)
 132                         seq_printf(s,
 133                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 134                                    stop->opcode, stop->arg, stop->flags,
 135                                    stop->resp[0], stop->resp[1], stop->resp[2],
 136                                    stop->resp[2], stop->error);
 137         }
 138
 139         spin_unlock_bh(&slot->host->lock);
 140
 141         return 0;
 142 }
 143
 144 static int dw_mci_req_open(struct inode *inode, struct file *file)
 145 {
 146         return single_open(file, dw_mci_req_show, inode->i_private);
 147 }
 148
 149 static const struct file_operations dw_mci_req_fops = {
 150         .owner          = THIS_MODULE,
 151         .open           = dw_mci_req_open,
 152         .read           = seq_read,
 153         .llseek         = seq_lseek,
 154         .release        = single_release,
 155 };
 156
 157 static int dw_mci_regs_show(struct seq_file *s, void *v)
 158 {
 159         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 160         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 161         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 162         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 163         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 164         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 165
 166         return 0;
 167 }
 168
 169 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 170 {
 171         return single_open(file, dw_mci_regs_show, inode->i_private);
 172 }
 173
 174 static const struct file_operations dw_mci_regs_fops = {
 175         .owner          = THIS_MODULE,
 176         .open           = dw_mci_regs_open,
 177         .read           = seq_read,
 178         .llseek         = seq_lseek,
 179         .release        = single_release,
 180 };
 181
 182 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 183 {
 184         struct mmc_host *mmc = slot->mmc;
 185         struct dw_mci *host = slot->host;
 186         struct dentry *root;
 187         struct dentry *node;
 188
 189         root = mmc->debugfs_root;
 190         if (!root)
 191                 return;
 192
 193         node = debugfs_create_file("regs", S_IRUSR, root, host,
 194                                    &dw_mci_regs_fops);
 195         if (!node)
 196                 goto err;
 197
 198         node = debugfs_create_file("req", S_IRUSR, root, slot,
 199                                    &dw_mci_req_fops);
 200         if (!node)
 201                 goto err;
 202
 203         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 208                                   (u32 *)&host->pending_events);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 213                                   (u32 *)&host->completed_events);
 214         if (!node)
 215                 goto err;
 216
 217         return;
 218
 219 err:
 220         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 221 }
 222 #endif /* defined(CONFIG_DEBUG_FS) */
 223
 224 static void dw_mci_set_timeout(struct dw_mci *host)
 225 {
 226         /* timeout (maximum) */
 227         mci_writel(host, TMOUT, 0xffffffff);
 228 }
 229
 230 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 231 {
 232         struct mmc_data *data;
 233         u32 cmdr;
 234         cmd->error = -EINPROGRESS;
 235
 236         cmdr = cmd->opcode;
 237
 238         if (cmdr == MMC_STOP_TRANSMISSION)
 239                 cmdr |= SDMMC_CMD_STOP;
 240         else
 241                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 242
 243         if (cmd->flags & MMC_RSP_PRESENT) {
 244                 /* We expect a response, so set this bit */
 245                 cmdr |= SDMMC_CMD_RESP_EXP;
 246                 if (cmd->flags & MMC_RSP_136)
 247                         cmdr |= SDMMC_CMD_RESP_LONG;
 248         }
 249
 250         if (cmd->flags & MMC_RSP_CRC)
 251                 cmdr |= SDMMC_CMD_RESP_CRC;
 252
 253         data = cmd->data;
 254         if (data) {
 255                 cmdr |= SDMMC_CMD_DAT_EXP;
 256                 if (data->flags & MMC_DATA_STREAM)
 257                         cmdr |= SDMMC_CMD_STRM_MODE;
 258                 if (data->flags & MMC_DATA_WRITE)
 259                         cmdr |= SDMMC_CMD_DAT_WR;
 260         }
 261
 262         return cmdr;
 263 }
 264
 265 static void dw_mci_start_command(struct dw_mci *host,
 266                                  struct mmc_command *cmd, u32 cmd_flags)
 267 {
 268         host->cmd = cmd;
 269         dev_vdbg(&host->dev,
 270                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 271                  cmd->arg, cmd_flags);
 272
 273         mci_writel(host, CMDARG, cmd->arg);
 274         wmb();
 275
 276         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 277 }
 278
 279 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 280 {
 281         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 282 }
 283
 284 /* DMA interface functions */
 285 static void dw_mci_stop_dma(struct dw_mci *host)
 286 {
 287         if (host->using_dma) {
 288                 host->dma_ops->stop(host);
 289                 host->dma_ops->cleanup(host);
 290         } else {
 291                 /* Data transfer was stopped by the interrupt handler */
 292                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 293         }
 294 }
 295
 296 static int dw_mci_get_dma_dir(struct mmc_data *data)
 297 {
 298         if (data->flags & MMC_DATA_WRITE)
 299                 return DMA_TO_DEVICE;
 300         else
 301                 return DMA_FROM_DEVICE;
 302 }
 303
 304 #ifdef CONFIG_MMC_DW_IDMAC
 305 static void dw_mci_dma_cleanup(struct dw_mci *host)
 306 {
 307         struct mmc_data *data = host->data;
 308
 309         if (data)
 310                 if (!data->host_cookie)
 311                         dma_unmap_sg(&host->dev,
 312                                      data->sg,
 313                                      data->sg_len,
 314                                      dw_mci_get_dma_dir(data));
 315 }
 316
 317 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 318 {
 319         u32 temp;
 320
 321         /* Disable and reset the IDMAC interface */
 322         temp = mci_readl(host, CTRL);
 323         temp &= ~SDMMC_CTRL_USE_IDMAC;
 324         temp |= SDMMC_CTRL_DMA_RESET;
 325         mci_writel(host, CTRL, temp);
 326
 327         /* Stop the IDMAC running */
 328         temp = mci_readl(host, BMOD);
 329         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 330         mci_writel(host, BMOD, temp);
 331 }
 332
 333 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 334 {
 335         struct mmc_data *data = host->data;
 336
 337         dev_vdbg(&host->dev, "DMA complete\n");
 338
 339         host->dma_ops->cleanup(host);
 340
 341         /*
 342          * If the card was removed, data will be NULL. No point in trying to
 343          * send the stop command or waiting for NBUSY in this case.
 344          */
 345         if (data) {
 346                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 347                 tasklet_schedule(&host->tasklet);
 348         }
 349 }
 350
 351 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 352                                     unsigned int sg_len)
 353 {
 354         int i;
 355         struct idmac_desc *desc = host->sg_cpu;
 356
 357         for (i = 0; i < sg_len; i++, desc++) {
 358                 unsigned int length = sg_dma_len(&data->sg[i]);
 359                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 360
 361                 /* Set the OWN bit and disable interrupts for this descriptor */
 362                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 363
 364                 /* Buffer length */
 365                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 366
 367                 /* Physical address to DMA to/from */
 368                 desc->des2 = mem_addr;
 369         }
 370
 371         /* Set first descriptor */
 372         desc = host->sg_cpu;
 373         desc->des0 |= IDMAC_DES0_FD;
 374
 375         /* Set last descriptor */
 376         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 377         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 378         desc->des0 |= IDMAC_DES0_LD;
 379
 380         wmb();
 381 }
 382
 383 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 384 {
 385         u32 temp;
 386
 387         dw_mci_translate_sglist(host, host->data, sg_len);
 388
 389         /* Select IDMAC interface */
 390         temp = mci_readl(host, CTRL);
 391         temp |= SDMMC_CTRL_USE_IDMAC;
 392         mci_writel(host, CTRL, temp);
 393
 394         wmb();
 395
 396         /* Enable the IDMAC */
 397         temp = mci_readl(host, BMOD);
 398         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 399         mci_writel(host, BMOD, temp);
 400
 401         /* Start it running */
 402         mci_writel(host, PLDMND, 1);
 403 }
 404
 405 static int dw_mci_idmac_init(struct dw_mci *host)
 406 {
 407         struct idmac_desc *p;
 408         int i;
 409
 410         /* Number of descriptors in the ring buffer */
 411         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 412
 413         /* Forward link the descriptor list */
 414         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 415                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 416
 417         /* Set the last descriptor as the end-of-ring descriptor */
 418         p->des3 = host->sg_dma;
 419         p->des0 = IDMAC_DES0_ER;
 420
 421         /* Mask out interrupts - get Tx & Rx complete only */
 422         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 423                    SDMMC_IDMAC_INT_TI);
 424
 425         /* Set the descriptor base address */
 426         mci_writel(host, DBADDR, host->sg_dma);
 427         return 0;
 428 }
 429
 430 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 431         .init = dw_mci_idmac_init,
 432         .start = dw_mci_idmac_start_dma,
 433         .stop = dw_mci_idmac_stop_dma,
 434         .complete = dw_mci_idmac_complete_dma,
 435         .cleanup = dw_mci_dma_cleanup,
 436 };
 437 #endif /* CONFIG_MMC_DW_IDMAC */
 438
 439 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 440                                    struct mmc_data *data,
 441                                    bool next)
 442 {
 443         struct scatterlist *sg;
 444         unsigned int i, sg_len;
 445
 446         if (!next && data->host_cookie)
 447                 return data->host_cookie;
 448
 449         /*
 450          * We don't do DMA on "complex" transfers, i.e. with
 451          * non-word-aligned buffers or lengths. Also, we don't bother
 452          * with all the DMA setup overhead for short transfers.
 453          */
 454         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 455                 return -EINVAL;
 456
 457         if (data->blksz & 3)
 458                 return -EINVAL;
 459
 460         for_each_sg(data->sg, sg, data->sg_len, i) {
 461                 if (sg->offset & 3 || sg->length & 3)
 462                         return -EINVAL;
 463         }
 464
 465         sg_len = dma_map_sg(&host->dev,
 466                             data->sg,
 467                             data->sg_len,
 468                             dw_mci_get_dma_dir(data));
 469         if (sg_len == 0)
 470                 return -EINVAL;
 471
 472         if (next)
 473                 data->host_cookie = sg_len;
 474
 475         return sg_len;
 476 }
 477
 478 static void dw_mci_pre_req(struct mmc_host *mmc,
 479                            struct mmc_request *mrq,
 480                            bool is_first_req)
 481 {
 482         struct dw_mci_slot *slot = mmc_priv(mmc);
 483         struct mmc_data *data = mrq->data;
 484
 485         if (!slot->host->use_dma || !data)
 486                 return;
 487
 488         if (data->host_cookie) {
 489                 data->host_cookie = 0;
 490                 return;
 491         }
 492
 493         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 494                 data->host_cookie = 0;
 495 }
 496
 497 static void dw_mci_post_req(struct mmc_host *mmc,
 498                             struct mmc_request *mrq,
 499                             int err)
 500 {
 501         struct dw_mci_slot *slot = mmc_priv(mmc);
 502         struct mmc_data *data = mrq->data;
 503
 504         if (!slot->host->use_dma || !data)
 505                 return;
 506
 507         if (data->host_cookie)
 508                 dma_unmap_sg(&slot->host->dev,
 509                              data->sg,
 510                              data->sg_len,
 511                              dw_mci_get_dma_dir(data));
 512         data->host_cookie = 0;
 513 }
 514
 515 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 516 {
 517         int sg_len;
 518         u32 temp;
 519
 520         host->using_dma = 0;
 521
 522         /* If we don't have a channel, we can't do DMA */
 523         if (!host->use_dma)
 524                 return -ENODEV;
 525
 526         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 527         if (sg_len < 0) {
 528                 host->dma_ops->stop(host);
 529                 return sg_len;
 530         }
 531
 532         host->using_dma = 1;
 533
 534         dev_vdbg(&host->dev,
 535                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 536                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 537                  sg_len);
 538
 539         /* Enable the DMA interface */
 540         temp = mci_readl(host, CTRL);
 541         temp |= SDMMC_CTRL_DMA_ENABLE;
 542         mci_writel(host, CTRL, temp);
 543
 544         /* Disable RX/TX IRQs, let DMA handle it */
 545         temp = mci_readl(host, INTMASK);
 546         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 547         mci_writel(host, INTMASK, temp);
 548
 549         host->dma_ops->start(host, sg_len);
 550
 551         return 0;
 552 }
 553
 554 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 555 {
 556         u32 temp;
 557
 558         data->error = -EINPROGRESS;
 559
 560         WARN_ON(host->data);
 561         host->sg = NULL;
 562         host->data = data;
 563
 564         if (data->flags & MMC_DATA_READ)
 565                 host->dir_status = DW_MCI_RECV_STATUS;
 566         else
 567                 host->dir_status = DW_MCI_SEND_STATUS;
 568
 569         if (dw_mci_submit_data_dma(host, data)) {
 570                 int flags = SG_MITER_ATOMIC;
 571                 if (host->data->flags & MMC_DATA_READ)
 572                         flags |= SG_MITER_TO_SG;
 573                 else
 574                         flags |= SG_MITER_FROM_SG;
 575
 576                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 577                 host->sg = data->sg;
 578                 host->part_buf_start = 0;
 579                 host->part_buf_count = 0;
 580
 581                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 582                 temp = mci_readl(host, INTMASK);
 583                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 584                 mci_writel(host, INTMASK, temp);
 585
 586                 temp = mci_readl(host, CTRL);
 587                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 588                 mci_writel(host, CTRL, temp);
 589         }
 590 }
 591
 592 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 593 {
 594         struct dw_mci *host = slot->host;
 595         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 596         unsigned int cmd_status = 0;
 597
 598         mci_writel(host, CMDARG, arg);
 599         wmb();
 600         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 601
 602         while (time_before(jiffies, timeout)) {
 603                 cmd_status = mci_readl(host, CMD);
 604                 if (!(cmd_status & SDMMC_CMD_START))
 605                         return;
 606         }
 607         dev_err(&slot->mmc->class_dev,
 608                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 609                 cmd, arg, cmd_status);
 610 }
 611
 612 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 613 {
 614         struct dw_mci *host = slot->host;
 615         u32 div;
 616
 617         if (slot->clock != host->current_speed) {
 618                 if (host->bus_hz % slot->clock)
 619                         /*
 620                          * move the + 1 after the divide to prevent
 621                          * over-clocking the card.
 622                          */
 623                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 624                 else
 625                         div = (host->bus_hz  / slot->clock) >> 1;
 626
 627                 dev_info(&slot->mmc->class_dev,
 628                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 629                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 630                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 631
 632                 /* disable clock */
 633                 mci_writel(host, CLKENA, 0);
 634                 mci_writel(host, CLKSRC, 0);
 635
 636                 /* inform CIU */
 637                 mci_send_cmd(slot,
 638                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 639
 640                 /* set clock to desired speed */
 641                 mci_writel(host, CLKDIV, div);
 642
 643                 /* inform CIU */
 644                 mci_send_cmd(slot,
 645                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 646
 647                 /* enable clock */
 648                 mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
 649                            SDMMC_CLKEN_LOW_PWR) << slot->id));
 650
 651                 /* inform CIU */
 652                 mci_send_cmd(slot,
 653                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 654
 655                 host->current_speed = slot->clock;
 656         }
 657
 658         /* Set the current slot bus width */
 659         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 660 }
 661
 662 static void __dw_mci_start_request(struct dw_mci *host,
 663                                    struct dw_mci_slot *slot,
 664                                    struct mmc_command *cmd)
 665 {
 666         struct mmc_request *mrq;
 667         struct mmc_data *data;
 668         u32 cmdflags;
 669
 670         mrq = slot->mrq;
 671         if (host->pdata->select_slot)
 672                 host->pdata->select_slot(slot->id);
 673
 674         /* Slot specific timing and width adjustment */
 675         dw_mci_setup_bus(slot);
 676
 677         host->cur_slot = slot;
 678         host->mrq = mrq;
 679
 680         host->pending_events = 0;
 681         host->completed_events = 0;
 682         host->data_status = 0;
 683
 684         data = cmd->data;
 685         if (data) {
 686                 dw_mci_set_timeout(host);
 687                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 688                 mci_writel(host, BLKSIZ, data->blksz);
 689         }
 690
 691         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 692
 693         /* this is the first command, send the initialization clock */
 694         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 695                 cmdflags |= SDMMC_CMD_INIT;
 696
 697         if (data) {
 698                 dw_mci_submit_data(host, data);
 699                 wmb();
 700         }
 701
 702         dw_mci_start_command(host, cmd, cmdflags);
 703
 704         if (mrq->stop)
 705                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 706 }
 707
 708 static void dw_mci_start_request(struct dw_mci *host,
 709                                  struct dw_mci_slot *slot)
 710 {
 711         struct mmc_request *mrq = slot->mrq;
 712         struct mmc_command *cmd;
 713
 714         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 715         __dw_mci_start_request(host, slot, cmd);
 716 }
 717
 718 /* must be called with host->lock held */
 719 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 720                                  struct mmc_request *mrq)
 721 {
 722         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 723                  host->state);
 724
 725         slot->mrq = mrq;
 726
 727         if (host->state == STATE_IDLE) {
 728                 host->state = STATE_SENDING_CMD;
 729                 dw_mci_start_request(host, slot);
 730         } else {
 731                 list_add_tail(&slot->queue_node, &host->queue);
 732         }
 733 }
 734
 735 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 736 {
 737         struct dw_mci_slot *slot = mmc_priv(mmc);
 738         struct dw_mci *host = slot->host;
 739
 740         WARN_ON(slot->mrq);
 741
 742         /*
 743          * The check for card presence and queueing of the request must be
 744          * atomic, otherwise the card could be removed in between and the
 745          * request wouldn't fail until another card was inserted.
 746          */
 747         spin_lock_bh(&host->lock);
 748
 749         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 750                 spin_unlock_bh(&host->lock);
 751                 mrq->cmd->error = -ENOMEDIUM;
 752                 mmc_request_done(mmc, mrq);
 753                 return;
 754         }
 755
 756         dw_mci_queue_request(host, slot, mrq);
 757
 758         spin_unlock_bh(&host->lock);
 759 }
 760
 761 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 762 {
 763         struct dw_mci_slot *slot = mmc_priv(mmc);
 764         u32 regs;
 765
 766         /* set default 1 bit mode */
 767         slot->ctype = SDMMC_CTYPE_1BIT;
 768
 769         switch (ios->bus_width) {
 770         case MMC_BUS_WIDTH_1:
 771                 slot->ctype = SDMMC_CTYPE_1BIT;
 772                 break;
 773         case MMC_BUS_WIDTH_4:
 774                 slot->ctype = SDMMC_CTYPE_4BIT;
 775                 break;
 776         case MMC_BUS_WIDTH_8:
 777                 slot->ctype = SDMMC_CTYPE_8BIT;
 778                 break;
 779         }
 780
 781         regs = mci_readl(slot->host, UHS_REG);
 782
 783         /* DDR mode set */
 784         if (ios->timing == MMC_TIMING_UHS_DDR50)
 785                 regs |= (0x1 << slot->id) << 16;
 786         else
 787                 regs &= ~(0x1 << slot->id) << 16;
 788
 789         mci_writel(slot->host, UHS_REG, regs);
 790
 791         if (ios->clock) {
 792                 /*
 793                  * Use mirror of ios->clock to prevent race with mmc
 794                  * core ios update when finding the minimum.
 795                  */
 796                 slot->clock = ios->clock;
 797         }
 798
 799         switch (ios->power_mode) {
 800         case MMC_POWER_UP:
 801                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 802                 break;
 803         default:
 804                 break;
 805         }
 806 }
 807
 808 static int dw_mci_get_ro(struct mmc_host *mmc)
 809 {
 810         int read_only;
 811         struct dw_mci_slot *slot = mmc_priv(mmc);
 812         struct dw_mci_board *brd = slot->host->pdata;
 813
 814         /* Use platform get_ro function, else try on board write protect */
 815         if (brd->get_ro)
 816                 read_only = brd->get_ro(slot->id);
 817         else
 818                 read_only =
 819                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 820
 821         dev_dbg(&mmc->class_dev, "card is %s\n",
 822                 read_only ? "read-only" : "read-write");
 823
 824         return read_only;
 825 }
 826
 827 static int dw_mci_get_cd(struct mmc_host *mmc)
 828 {
 829         int present;
 830         struct dw_mci_slot *slot = mmc_priv(mmc);
 831         struct dw_mci_board *brd = slot->host->pdata;
 832
 833         /* Use platform get_cd function, else try onboard card detect */
 834         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 835                 present = 1;
 836         else if (brd->get_cd)
 837                 present = !brd->get_cd(slot->id);
 838         else
 839                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 840                         == 0 ? 1 : 0;
 841
 842         if (present)
 843                 dev_dbg(&mmc->class_dev, "card is present\n");
 844         else
 845                 dev_dbg(&mmc->class_dev, "card is not present\n");
 846
 847         return present;
 848 }
 849
 850 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 851 {
 852         struct dw_mci_slot *slot = mmc_priv(mmc);
 853         struct dw_mci *host = slot->host;
 854         u32 int_mask;
 855
 856         /* Enable/disable Slot Specific SDIO interrupt */
 857         int_mask = mci_readl(host, INTMASK);
 858         if (enb) {
 859                 mci_writel(host, INTMASK,
 860                            (int_mask | SDMMC_INT_SDIO(slot->id)));
 861         } else {
 862                 mci_writel(host, INTMASK,
 863                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 864         }
 865 }
 866
 867 static const struct mmc_host_ops dw_mci_ops = {
 868         .request                = dw_mci_request,
 869         .pre_req                = dw_mci_pre_req,
 870         .post_req               = dw_mci_post_req,
 871         .set_ios                = dw_mci_set_ios,
 872         .get_ro                 = dw_mci_get_ro,
 873         .get_cd                 = dw_mci_get_cd,
 874         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 875 };
 876
 877 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 878         __releases(&host->lock)
 879         __acquires(&host->lock)
 880 {
 881         struct dw_mci_slot *slot;
 882         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 883
 884         WARN_ON(host->cmd || host->data);
 885
 886         host->cur_slot->mrq = NULL;
 887         host->mrq = NULL;
 888         if (!list_empty(&host->queue)) {
 889                 slot = list_entry(host->queue.next,
 890                                   struct dw_mci_slot, queue_node);
 891                 list_del(&slot->queue_node);
 892                 dev_vdbg(&host->dev, "list not empty: %s is next\n",
 893                          mmc_hostname(slot->mmc));
 894                 host->state = STATE_SENDING_CMD;
 895                 dw_mci_start_request(host, slot);
 896         } else {
 897                 dev_vdbg(&host->dev, "list empty\n");
 898                 host->state = STATE_IDLE;
 899         }
 900
 901         spin_unlock(&host->lock);
 902         mmc_request_done(prev_mmc, mrq);
 903         spin_lock(&host->lock);
 904 }
 905
 906 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 907 {
 908         u32 status = host->cmd_status;
 909
 910         host->cmd_status = 0;
 911
 912         /* Read the response from the card (up to 16 bytes) */
 913         if (cmd->flags & MMC_RSP_PRESENT) {
 914                 if (cmd->flags & MMC_RSP_136) {
 915                         cmd->resp[3] = mci_readl(host, RESP0);
 916                         cmd->resp[2] = mci_readl(host, RESP1);
 917                         cmd->resp[1] = mci_readl(host, RESP2);
 918                         cmd->resp[0] = mci_readl(host, RESP3);
 919                 } else {
 920                         cmd->resp[0] = mci_readl(host, RESP0);
 921                         cmd->resp[1] = 0;
 922                         cmd->resp[2] = 0;
 923                         cmd->resp[3] = 0;
 924                 }
 925         }
 926
 927         if (status & SDMMC_INT_RTO)
 928                 cmd->error = -ETIMEDOUT;
 929         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 930                 cmd->error = -EILSEQ;
 931         else if (status & SDMMC_INT_RESP_ERR)
 932                 cmd->error = -EIO;
 933         else
 934                 cmd->error = 0;
 935
 936         if (cmd->error) {
 937                 /* newer ip versions need a delay between retries */
 938                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 939                         mdelay(20);
 940
 941                 if (cmd->data) {
 942                         host->data = NULL;
 943                         dw_mci_stop_dma(host);
 944                 }
 945         }
 946 }
 947
 948 static void dw_mci_tasklet_func(unsigned long priv)
 949 {
 950         struct dw_mci *host = (struct dw_mci *)priv;
 951         struct mmc_data *data;
 952         struct mmc_command *cmd;
 953         enum dw_mci_state state;
 954         enum dw_mci_state prev_state;
 955         u32 status, ctrl;
 956
 957         spin_lock(&host->lock);
 958
 959         state = host->state;
 960         data = host->data;
 961
 962         do {
 963                 prev_state = state;
 964
 965                 switch (state) {
 966                 case STATE_IDLE:
 967                         break;
 968
 969                 case STATE_SENDING_CMD:
 970                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 971                                                 &host->pending_events))
 972                                 break;
 973
 974                         cmd = host->cmd;
 975                         host->cmd = NULL;
 976                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 977                         dw_mci_command_complete(host, cmd);
 978                         if (cmd == host->mrq->sbc && !cmd->error) {
 979                                 prev_state = state = STATE_SENDING_CMD;
 980                                 __dw_mci_start_request(host, host->cur_slot,
 981                                                        host->mrq->cmd);
 982                                 goto unlock;
 983                         }
 984
 985                         if (!host->mrq->data || cmd->error) {
 986                                 dw_mci_request_end(host, host->mrq);
 987                                 goto unlock;
 988                         }
 989
 990                         prev_state = state = STATE_SENDING_DATA;
 991                         /* fall through */
 992
 993                 case STATE_SENDING_DATA:
 994                         if (test_and_clear_bit(EVENT_DATA_ERROR,
 995                                                &host->pending_events)) {
 996                                 dw_mci_stop_dma(host);
 997                                 if (data->stop)
 998                                         send_stop_cmd(host, data);
 999                                 state = STATE_DATA_ERROR;
1000                                 break;
1001                         }
1002
1003                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1004                                                 &host->pending_events))
1005                                 break;
1006
1007                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1008                         prev_state = state = STATE_DATA_BUSY;
1009                         /* fall through */
1010
1011                 case STATE_DATA_BUSY:
1012                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1013                                                 &host->pending_events))
1014                                 break;
1015
1016                         host->data = NULL;
1017                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1018                         status = host->data_status;
1019
1020                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1021                                 if (status & SDMMC_INT_DTO) {
1022                                         data->error = -ETIMEDOUT;
1023                                 } else if (status & SDMMC_INT_DCRC) {
1024                                         data->error = -EILSEQ;
1025                                 } else if (status & SDMMC_INT_EBE &&
1026                                            host->dir_status ==
1027                                                         DW_MCI_SEND_STATUS) {
1028                                         /*
1029                                          * No data CRC status was returned.
1030                                          * The number of bytes transferred will
1031                                          * be exaggerated in PIO mode.
1032                                          */
1033                                         data->bytes_xfered = 0;
1034                                         data->error = -ETIMEDOUT;
1035                                 } else {
1036                                         dev_err(&host->dev,
1037                                                 "data FIFO error "
1038                                                 "(status=%08x)\n",
1039                                                 status);
1040                                         data->error = -EIO;
1041                                 }
1042                                 /*
1043                                  * After an error, there may be data lingering
1044                                  * in the FIFO, so reset it - doing so
1045                                  * generates a block interrupt, hence setting
1046                                  * the scatter-gather pointer to NULL.
1047                                  */
1048                                 sg_miter_stop(&host->sg_miter);
1049                                 host->sg = NULL;
1050                                 ctrl = mci_readl(host, CTRL);
1051                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1052                                 mci_writel(host, CTRL, ctrl);
1053                         } else {
1054                                 data->bytes_xfered = data->blocks * data->blksz;
1055                                 data->error = 0;
1056                         }
1057
1058                         if (!data->stop) {
1059                                 dw_mci_request_end(host, host->mrq);
1060                                 goto unlock;
1061                         }
1062
1063                         if (host->mrq->sbc && !data->error) {
1064                                 data->stop->error = 0;
1065                                 dw_mci_request_end(host, host->mrq);
1066                                 goto unlock;
1067                         }
1068
1069                         prev_state = state = STATE_SENDING_STOP;
1070                         if (!data->error)
1071                                 send_stop_cmd(host, data);
1072                         /* fall through */
1073
1074                 case STATE_SENDING_STOP:
1075                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1076                                                 &host->pending_events))
1077                                 break;
1078
1079                         host->cmd = NULL;
1080                         dw_mci_command_complete(host, host->mrq->stop);
1081                         dw_mci_request_end(host, host->mrq);
1082                         goto unlock;
1083
1084                 case STATE_DATA_ERROR:
1085                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1086                                                 &host->pending_events))
1087                                 break;
1088
1089                         state = STATE_DATA_BUSY;
1090                         break;
1091                 }
1092         } while (state != prev_state);
1093
1094         host->state = state;
1095 unlock:
1096         spin_unlock(&host->lock);
1097
1098 }
1099
1100 /* push final bytes to part_buf, only use during push */
1101 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1102 {
1103         memcpy((void *)&host->part_buf, buf, cnt);
1104         host->part_buf_count = cnt;
1105 }
1106
1107 /* append bytes to part_buf, only use during push */
1108 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1109 {
1110         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1111         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1112         host->part_buf_count += cnt;
1113         return cnt;
1114 }
1115
1116 /* pull first bytes from part_buf, only use during pull */
1117 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1118 {
1119         cnt = min(cnt, (int)host->part_buf_count);
1120         if (cnt) {
1121                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1122                        cnt);
1123                 host->part_buf_count -= cnt;
1124                 host->part_buf_start += cnt;
1125         }
1126         return cnt;
1127 }
1128
1129 /* pull final bytes from the part_buf, assuming it's just been filled */
1130 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1131 {
1132         memcpy(buf, &host->part_buf, cnt);
1133         host->part_buf_start = cnt;
1134         host->part_buf_count = (1 << host->data_shift) - cnt;
1135 }
1136
1137 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1138 {
1139         /* try and push anything in the part_buf */
1140         if (unlikely(host->part_buf_count)) {
1141                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1142                 buf += len;
1143                 cnt -= len;
1144                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1145                         mci_writew(host, DATA(host->data_offset),
1146                                         host->part_buf16);
1147                         host->part_buf_count = 0;
1148                 }
1149         }
1150 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1151         if (unlikely((unsigned long)buf & 0x1)) {
1152                 while (cnt >= 2) {
1153                         u16 aligned_buf[64];
1154                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1155                         int items = len >> 1;
1156                         int i;
1157                         /* memcpy from input buffer into aligned buffer */
1158                         memcpy(aligned_buf, buf, len);
1159                         buf += len;
1160                         cnt -= len;
1161                         /* push data from aligned buffer into fifo */
1162                         for (i = 0; i < items; ++i)
1163                                 mci_writew(host, DATA(host->data_offset),
1164                                                 aligned_buf[i]);
1165                 }
1166         } else
1167 #endif
1168         {
1169                 u16 *pdata = buf;
1170                 for (; cnt >= 2; cnt -= 2)
1171                         mci_writew(host, DATA(host->data_offset), *pdata++);
1172                 buf = pdata;
1173         }
1174         /* put anything remaining in the part_buf */
1175         if (cnt) {
1176                 dw_mci_set_part_bytes(host, buf, cnt);
1177                 if (!sg_next(host->sg))
1178                         mci_writew(host, DATA(host->data_offset),
1179                                         host->part_buf16);
1180         }
1181 }
1182
1183 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1184 {
1185 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1186         if (unlikely((unsigned long)buf & 0x1)) {
1187                 while (cnt >= 2) {
1188                         /* pull data from fifo into aligned buffer */
1189                         u16 aligned_buf[64];
1190                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1191                         int items = len >> 1;
1192                         int i;
1193                         for (i = 0; i < items; ++i)
1194                                 aligned_buf[i] = mci_readw(host,
1195                                                 DATA(host->data_offset));
1196                         /* memcpy from aligned buffer into output buffer */
1197                         memcpy(buf, aligned_buf, len);
1198                         buf += len;
1199                         cnt -= len;
1200                 }
1201         } else
1202 #endif
1203         {
1204                 u16 *pdata = buf;
1205                 for (; cnt >= 2; cnt -= 2)
1206                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1207                 buf = pdata;
1208         }
1209         if (cnt) {
1210                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1211                 dw_mci_pull_final_bytes(host, buf, cnt);
1212         }
1213 }
1214
1215 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1216 {
1217         /* try and push anything in the part_buf */
1218         if (unlikely(host->part_buf_count)) {
1219                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1220                 buf += len;
1221                 cnt -= len;
1222                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1223                         mci_writel(host, DATA(host->data_offset),
1224                                         host->part_buf32);
1225                         host->part_buf_count = 0;
1226                 }
1227         }
1228 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1229         if (unlikely((unsigned long)buf & 0x3)) {
1230                 while (cnt >= 4) {
1231                         u32 aligned_buf[32];
1232                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1233                         int items = len >> 2;
1234                         int i;
1235                         /* memcpy from input buffer into aligned buffer */
1236                         memcpy(aligned_buf, buf, len);
1237                         buf += len;
1238                         cnt -= len;
1239                         /* push data from aligned buffer into fifo */
1240                         for (i = 0; i < items; ++i)
1241                                 mci_writel(host, DATA(host->data_offset),
1242                                                 aligned_buf[i]);
1243                 }
1244         } else
1245 #endif
1246         {
1247                 u32 *pdata = buf;
1248                 for (; cnt >= 4; cnt -= 4)
1249                         mci_writel(host, DATA(host->data_offset), *pdata++);
1250                 buf = pdata;
1251         }
1252         /* put anything remaining in the part_buf */
1253         if (cnt) {
1254                 dw_mci_set_part_bytes(host, buf, cnt);
1255                 if (!sg_next(host->sg))
1256                         mci_writel(host, DATA(host->data_offset),
1257                                                 host->part_buf32);
1258         }
1259 }
1260
1261 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1262 {
1263 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1264         if (unlikely((unsigned long)buf & 0x3)) {
1265                 while (cnt >= 4) {
1266                         /* pull data from fifo into aligned buffer */
1267                         u32 aligned_buf[32];
1268                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1269                         int items = len >> 2;
1270                         int i;
1271                         for (i = 0; i < items; ++i)
1272                                 aligned_buf[i] = mci_readl(host,
1273                                                 DATA(host->data_offset));
1274                         /* memcpy from aligned buffer into output buffer */
1275                         memcpy(buf, aligned_buf, len);
1276                         buf += len;
1277                         cnt -= len;
1278                 }
1279         } else
1280 #endif
1281         {
1282                 u32 *pdata = buf;
1283                 for (; cnt >= 4; cnt -= 4)
1284                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1285                 buf = pdata;
1286         }
1287         if (cnt) {
1288                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1289                 dw_mci_pull_final_bytes(host, buf, cnt);
1290         }
1291 }
1292
1293 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1294 {
1295         /* try and push anything in the part_buf */
1296         if (unlikely(host->part_buf_count)) {
1297                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1298                 buf += len;
1299                 cnt -= len;
1300                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1301                         mci_writew(host, DATA(host->data_offset),
1302                                         host->part_buf);
1303                         host->part_buf_count = 0;
1304                 }
1305         }
1306 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1307         if (unlikely((unsigned long)buf & 0x7)) {
1308                 while (cnt >= 8) {
1309                         u64 aligned_buf[16];
1310                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1311                         int items = len >> 3;
1312                         int i;
1313                         /* memcpy from input buffer into aligned buffer */
1314                         memcpy(aligned_buf, buf, len);
1315                         buf += len;
1316                         cnt -= len;
1317                         /* push data from aligned buffer into fifo */
1318                         for (i = 0; i < items; ++i)
1319                                 mci_writeq(host, DATA(host->data_offset),
1320                                                 aligned_buf[i]);
1321                 }
1322         } else
1323 #endif
1324         {
1325                 u64 *pdata = buf;
1326                 for (; cnt >= 8; cnt -= 8)
1327                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1328                 buf = pdata;
1329         }
1330         /* put anything remaining in the part_buf */
1331         if (cnt) {
1332                 dw_mci_set_part_bytes(host, buf, cnt);
1333                 if (!sg_next(host->sg))
1334                         mci_writeq(host, DATA(host->data_offset),
1335                                         host->part_buf);
1336         }
1337 }
1338
1339 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1340 {
1341 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1342         if (unlikely((unsigned long)buf & 0x7)) {
1343                 while (cnt >= 8) {
1344                         /* pull data from fifo into aligned buffer */
1345                         u64 aligned_buf[16];
1346                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1347                         int items = len >> 3;
1348                         int i;
1349                         for (i = 0; i < items; ++i)
1350                                 aligned_buf[i] = mci_readq(host,
1351                                                 DATA(host->data_offset));
1352                         /* memcpy from aligned buffer into output buffer */
1353                         memcpy(buf, aligned_buf, len);
1354                         buf += len;
1355                         cnt -= len;
1356                 }
1357         } else
1358 #endif
1359         {
1360                 u64 *pdata = buf;
1361                 for (; cnt >= 8; cnt -= 8)
1362                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1363                 buf = pdata;
1364         }
1365         if (cnt) {
1366                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1367                 dw_mci_pull_final_bytes(host, buf, cnt);
1368         }
1369 }
1370
1371 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1372 {
1373         int len;
1374
1375         /* get remaining partial bytes */
1376         len = dw_mci_pull_part_bytes(host, buf, cnt);
1377         if (unlikely(len == cnt))
1378                 return;
1379         buf += len;
1380         cnt -= len;
1381
1382         /* get the rest of the data */
1383         host->pull_data(host, buf, cnt);
1384 }
1385
1386 static void dw_mci_read_data_pio(struct dw_mci *host)
1387 {
1388         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1389         void *buf;
1390         unsigned int offset;
1391         struct mmc_data *data = host->data;
1392         int shift = host->data_shift;
1393         u32 status;
1394         unsigned int nbytes = 0, len;
1395         unsigned int remain, fcnt;
1396
1397         do {
1398                 if (!sg_miter_next(sg_miter))
1399                         goto done;
1400
1401                 host->sg = sg_miter->__sg;
1402                 buf = sg_miter->addr;
1403                 remain = sg_miter->length;
1404                 offset = 0;
1405
1406                 do {
1407                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1408                                         << shift) + host->part_buf_count;
1409                         len = min(remain, fcnt);
1410                         if (!len)
1411                                 break;
1412                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1413                         offset += len;
1414                         nbytes += len;
1415                         remain -= len;
1416                 } while (remain);
1417                 sg_miter->consumed = offset;
1418
1419                 status = mci_readl(host, MINTSTS);
1420                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1421                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1422                         host->data_status = status;
1423                         data->bytes_xfered += nbytes;
1424                         sg_miter_stop(sg_miter);
1425                         host->sg = NULL;
1426                         smp_wmb();
1427
1428                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1429
1430                         tasklet_schedule(&host->tasklet);
1431                         return;
1432                 }
1433         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1434         data->bytes_xfered += nbytes;
1435
1436         if (!remain) {
1437                 if (!sg_miter_next(sg_miter))
1438                         goto done;
1439                 sg_miter->consumed = 0;
1440         }
1441         sg_miter_stop(sg_miter);
1442         return;
1443
1444 done:
1445         data->bytes_xfered += nbytes;
1446         sg_miter_stop(sg_miter);
1447         host->sg = NULL;
1448         smp_wmb();
1449         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1450 }
1451
1452 static void dw_mci_write_data_pio(struct dw_mci *host)
1453 {
1454         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1455         void *buf;
1456         unsigned int offset;
1457         struct mmc_data *data = host->data;
1458         int shift = host->data_shift;
1459         u32 status;
1460         unsigned int nbytes = 0, len;
1461         unsigned int fifo_depth = host->fifo_depth;
1462         unsigned int remain, fcnt;
1463
1464         do {
1465                 if (!sg_miter_next(sg_miter))
1466                         goto done;
1467
1468                 host->sg = sg_miter->__sg;
1469                 buf = sg_miter->addr;
1470                 remain = sg_miter->length;
1471                 offset = 0;
1472
1473                 do {
1474                         fcnt = ((fifo_depth -
1475                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1476                                         << shift) - host->part_buf_count;
1477                         len = min(remain, fcnt);
1478                         if (!len)
1479                                 break;
1480                         host->push_data(host, (void *)(buf + offset), len);
1481                         offset += len;
1482                         nbytes += len;
1483                         remain -= len;
1484                 } while (remain);
1485                 sg_miter->consumed = offset;
1486
1487                 status = mci_readl(host, MINTSTS);
1488                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1489                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1490                         host->data_status = status;
1491                         data->bytes_xfered += nbytes;
1492                         sg_miter_stop(sg_miter);
1493                         host->sg = NULL;
1494
1495                         smp_wmb();
1496
1497                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1498
1499                         tasklet_schedule(&host->tasklet);
1500                         return;
1501                 }
1502         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1503         data->bytes_xfered += nbytes;
1504
1505         if (!remain) {
1506                 if (!sg_miter_next(sg_miter))
1507                         goto done;
1508                 sg_miter->consumed = 0;
1509         }
1510         sg_miter_stop(sg_miter);
1511         return;
1512
1513 done:
1514         data->bytes_xfered += nbytes;
1515         sg_miter_stop(sg_miter);
1516         host->sg = NULL;
1517         smp_wmb();
1518         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1519 }
1520
1521 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1522 {
1523         if (!host->cmd_status)
1524                 host->cmd_status = status;
1525
1526         smp_wmb();
1527
1528         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1529         tasklet_schedule(&host->tasklet);
1530 }
1531
1532 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1533 {
1534         struct dw_mci *host = dev_id;
1535         u32 status, pending;
1536         unsigned int pass_count = 0;
1537         int i;
1538
1539         do {
1540                 status = mci_readl(host, RINTSTS);
1541                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1542
1543                 /*
1544                  * DTO fix - version 2.10a and below, and only if internal DMA
1545                  * is configured.
1546                  */
1547                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1548                         if (!pending &&
1549                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1550                                 pending |= SDMMC_INT_DATA_OVER;
1551                 }
1552
1553                 if (!pending)
1554                         break;
1555
1556                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1557                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1558                         host->cmd_status = status;
1559                         smp_wmb();
1560                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1561                 }
1562
1563                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1564                         /* if there is an error report DATA_ERROR */
1565                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1566                         host->data_status = status;
1567                         smp_wmb();
1568                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1569                         if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1570                                          SDMMC_INT_SBE | SDMMC_INT_EBE)))
1571                                 tasklet_schedule(&host->tasklet);
1572                 }
1573
1574                 if (pending & SDMMC_INT_DATA_OVER) {
1575                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1576                         if (!host->data_status)
1577                                 host->data_status = status;
1578                         smp_wmb();
1579                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1580                                 if (host->sg != NULL)
1581                                         dw_mci_read_data_pio(host);
1582                         }
1583                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1584                         tasklet_schedule(&host->tasklet);
1585                 }
1586
1587                 if (pending & SDMMC_INT_RXDR) {
1588                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1589                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1590                                 dw_mci_read_data_pio(host);
1591                 }
1592
1593                 if (pending & SDMMC_INT_TXDR) {
1594                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1595                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1596                                 dw_mci_write_data_pio(host);
1597                 }
1598
1599                 if (pending & SDMMC_INT_CMD_DONE) {
1600                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1601                         dw_mci_cmd_interrupt(host, status);
1602                 }
1603
1604                 if (pending & SDMMC_INT_CD) {
1605                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1606                         queue_work(host->card_workqueue, &host->card_work);
1607                 }
1608
1609                 /* Handle SDIO Interrupts */
1610                 for (i = 0; i < host->num_slots; i++) {
1611                         struct dw_mci_slot *slot = host->slot[i];
1612                         if (pending & SDMMC_INT_SDIO(i)) {
1613                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1614                                 mmc_signal_sdio_irq(slot->mmc);
1615                         }
1616                 }
1617
1618         } while (pass_count++ < 5);
1619
1620 #ifdef CONFIG_MMC_DW_IDMAC
1621         /* Handle DMA interrupts */
1622         pending = mci_readl(host, IDSTS);
1623         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1624                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1625                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1626                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1627                 host->dma_ops->complete(host);
1628         }
1629 #endif
1630
1631         return IRQ_HANDLED;
1632 }
1633
1634 static void dw_mci_work_routine_card(struct work_struct *work)
1635 {
1636         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1637         int i;
1638
1639         for (i = 0; i < host->num_slots; i++) {
1640                 struct dw_mci_slot *slot = host->slot[i];
1641                 struct mmc_host *mmc = slot->mmc;
1642                 struct mmc_request *mrq;
1643                 int present;
1644                 u32 ctrl;
1645
1646                 present = dw_mci_get_cd(mmc);
1647                 while (present != slot->last_detect_state) {
1648                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1649                                 present ? "inserted" : "removed");
1650
1651                         /* Power up slot (before spin_lock, may sleep) */
1652                         if (present != 0 && host->pdata->setpower)
1653                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1654
1655                         spin_lock_bh(&host->lock);
1656
1657                         /* Card change detected */
1658                         slot->last_detect_state = present;
1659
1660                         /* Mark card as present if applicable */
1661                         if (present != 0)
1662                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1663
1664                         /* Clean up queue if present */
1665                         mrq = slot->mrq;
1666                         if (mrq) {
1667                                 if (mrq == host->mrq) {
1668                                         host->data = NULL;
1669                                         host->cmd = NULL;
1670
1671                                         switch (host->state) {
1672                                         case STATE_IDLE:
1673                                                 break;
1674                                         case STATE_SENDING_CMD:
1675                                                 mrq->cmd->error = -ENOMEDIUM;
1676                                                 if (!mrq->data)
1677                                                         break;
1678                                                 /* fall through */
1679                                         case STATE_SENDING_DATA:
1680                                                 mrq->data->error = -ENOMEDIUM;
1681                                                 dw_mci_stop_dma(host);
1682                                                 break;
1683                                         case STATE_DATA_BUSY:
1684                                         case STATE_DATA_ERROR:
1685                                                 if (mrq->data->error == -EINPROGRESS)
1686                                                         mrq->data->error = -ENOMEDIUM;
1687                                                 if (!mrq->stop)
1688                                                         break;
1689                                                 /* fall through */
1690                                         case STATE_SENDING_STOP:
1691                                                 mrq->stop->error = -ENOMEDIUM;
1692                                                 break;
1693                                         }
1694
1695                                         dw_mci_request_end(host, mrq);
1696                                 } else {
1697                                         list_del(&slot->queue_node);
1698                                         mrq->cmd->error = -ENOMEDIUM;
1699                                         if (mrq->data)
1700                                                 mrq->data->error = -ENOMEDIUM;
1701                                         if (mrq->stop)
1702                                                 mrq->stop->error = -ENOMEDIUM;
1703
1704                                         spin_unlock(&host->lock);
1705                                         mmc_request_done(slot->mmc, mrq);
1706                                         spin_lock(&host->lock);
1707                                 }
1708                         }
1709
1710                         /* Power down slot */
1711                         if (present == 0) {
1712                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1713
1714                                 /*
1715                                  * Clear down the FIFO - doing so generates a
1716                                  * block interrupt, hence setting the
1717                                  * scatter-gather pointer to NULL.
1718                                  */
1719                                 sg_miter_stop(&host->sg_miter);
1720                                 host->sg = NULL;
1721
1722                                 ctrl = mci_readl(host, CTRL);
1723                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1724                                 mci_writel(host, CTRL, ctrl);
1725
1726 #ifdef CONFIG_MMC_DW_IDMAC
1727                                 ctrl = mci_readl(host, BMOD);
1728                                 ctrl |= 0x01; /* Software reset of DMA */
1729                                 mci_writel(host, BMOD, ctrl);
1730 #endif
1731
1732                         }
1733
1734                         spin_unlock_bh(&host->lock);
1735
1736                         /* Power down slot (after spin_unlock, may sleep) */
1737                         if (present == 0 && host->pdata->setpower)
1738                                 host->pdata->setpower(slot->id, 0);
1739
1740                         present = dw_mci_get_cd(mmc);
1741                 }
1742
1743                 mmc_detect_change(slot->mmc,
1744                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1745         }
1746 }
1747
1748 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1749 {
1750         struct mmc_host *mmc;
1751         struct dw_mci_slot *slot;
1752
1753         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev);
1754         if (!mmc)
1755                 return -ENOMEM;
1756
1757         slot = mmc_priv(mmc);
1758         slot->id = id;
1759         slot->mmc = mmc;
1760         slot->host = host;
1761
1762         mmc->ops = &dw_mci_ops;
1763         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1764         mmc->f_max = host->bus_hz;
1765
1766         if (host->pdata->get_ocr)
1767                 mmc->ocr_avail = host->pdata->get_ocr(id);
1768         else
1769                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1770
1771         /*
1772          * Start with slot power disabled, it will be enabled when a card
1773          * is detected.
1774          */
1775         if (host->pdata->setpower)
1776                 host->pdata->setpower(id, 0);
1777
1778         if (host->pdata->caps)
1779                 mmc->caps = host->pdata->caps;
1780
1781         if (host->pdata->caps2)
1782                 mmc->caps2 = host->pdata->caps2;
1783
1784         if (host->pdata->get_bus_wd)
1785                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1786                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1787
1788         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1789                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1790
1791         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1792                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1793         else
1794                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1795
1796         if (host->pdata->blk_settings) {
1797                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1798                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1799                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1800                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1801                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1802         } else {
1803                 /* Useful defaults if platform data is unset. */
1804 #ifdef CONFIG_MMC_DW_IDMAC
1805                 mmc->max_segs = host->ring_size;
1806                 mmc->max_blk_size = 65536;
1807                 mmc->max_blk_count = host->ring_size;
1808                 mmc->max_seg_size = 0x1000;
1809                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1810 #else
1811                 mmc->max_segs = 64;
1812                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1813                 mmc->max_blk_count = 512;
1814                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1815                 mmc->max_seg_size = mmc->max_req_size;
1816 #endif /* CONFIG_MMC_DW_IDMAC */
1817         }
1818
1819         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1820         if (IS_ERR(host->vmmc)) {
1821                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1822                 host->vmmc = NULL;
1823         } else
1824                 regulator_enable(host->vmmc);
1825
1826         if (dw_mci_get_cd(mmc))
1827                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1828         else
1829                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1830
1831         host->slot[id] = slot;
1832         mmc_add_host(mmc);
1833
1834 #if defined(CONFIG_DEBUG_FS)
1835         dw_mci_init_debugfs(slot);
1836 #endif
1837
1838         /* Card initially undetected */
1839         slot->last_detect_state = 0;
1840
1841         /*
1842          * Card may have been plugged in prior to boot so we
1843          * need to run the detect tasklet
1844          */
1845         queue_work(host->card_workqueue, &host->card_work);
1846
1847         return 0;
1848 }
1849
1850 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1851 {
1852         /* Shutdown detect IRQ */
1853         if (slot->host->pdata->exit)
1854                 slot->host->pdata->exit(id);
1855
1856         /* Debugfs stuff is cleaned up by mmc core */
1857         mmc_remove_host(slot->mmc);
1858         slot->host->slot[id] = NULL;
1859         mmc_free_host(slot->mmc);
1860 }
1861
1862 static void dw_mci_init_dma(struct dw_mci *host)
1863 {
1864         /* Alloc memory for sg translation */
1865         host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE,
1866                                           &host->sg_dma, GFP_KERNEL);
1867         if (!host->sg_cpu) {
1868                 dev_err(&host->dev, "%s: could not alloc DMA memory\n",
1869                         __func__);
1870                 goto no_dma;
1871         }
1872
1873         /* Determine which DMA interface to use */
1874 #ifdef CONFIG_MMC_DW_IDMAC
1875         host->dma_ops = &dw_mci_idmac_ops;
1876         dev_info(&host->dev, "Using internal DMA controller.\n");
1877 #endif
1878
1879         if (!host->dma_ops)
1880                 goto no_dma;
1881
1882         if (host->dma_ops->init && host->dma_ops->start &&
1883             host->dma_ops->stop && host->dma_ops->cleanup) {
1884                 if (host->dma_ops->init(host)) {
1885                         dev_err(&host->dev, "%s: Unable to initialize "
1886                                 "DMA Controller.\n", __func__);
1887                         goto no_dma;
1888                 }
1889         } else {
1890                 dev_err(&host->dev, "DMA initialization not found.\n");
1891                 goto no_dma;
1892         }
1893
1894         host->use_dma = 1;
1895         return;
1896
1897 no_dma:
1898         dev_info(&host->dev, "Using PIO mode.\n");
1899         host->use_dma = 0;
1900         return;
1901 }
1902
1903 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1904 {
1905         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1906         unsigned int ctrl;
1907
1908         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1909                                 SDMMC_CTRL_DMA_RESET));
1910
1911         /* wait till resets clear */
1912         do {
1913                 ctrl = mci_readl(host, CTRL);
1914                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1915                               SDMMC_CTRL_DMA_RESET)))
1916                         return true;
1917         } while (time_before(jiffies, timeout));
1918
1919         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1920
1921         return false;
1922 }
1923
1924 int dw_mci_probe(struct dw_mci *host)
1925 {
1926         int width, i, ret = 0;
1927         u32 fifo_size;
1928
1929         if (!host->pdata || !host->pdata->init) {
1930                 dev_err(&host->dev,
1931                         "Platform data must supply init function\n");
1932                 return -ENODEV;
1933         }
1934
1935         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
1936                 dev_err(&host->dev,
1937                         "Platform data must supply select_slot function\n");
1938                 return -ENODEV;
1939         }
1940
1941         if (!host->pdata->bus_hz) {
1942                 dev_err(&host->dev,
1943                         "Platform data must supply bus speed\n");
1944                 return -ENODEV;
1945         }
1946
1947         host->bus_hz = host->pdata->bus_hz;
1948         host->quirks = host->pdata->quirks;
1949
1950         spin_lock_init(&host->lock);
1951         INIT_LIST_HEAD(&host->queue);
1952
1953
1954         host->dma_ops = host->pdata->dma_ops;
1955         dw_mci_init_dma(host);
1956
1957         /*
1958          * Get the host data width - this assumes that HCON has been set with
1959          * the correct values.
1960          */
1961         i = (mci_readl(host, HCON) >> 7) & 0x7;
1962         if (!i) {
1963                 host->push_data = dw_mci_push_data16;
1964                 host->pull_data = dw_mci_pull_data16;
1965                 width = 16;
1966                 host->data_shift = 1;
1967         } else if (i == 2) {
1968                 host->push_data = dw_mci_push_data64;
1969                 host->pull_data = dw_mci_pull_data64;
1970                 width = 64;
1971                 host->data_shift = 3;
1972         } else {
1973                 /* Check for a reserved value, and warn if it is */
1974                 WARN((i != 1),
1975                      "HCON reports a reserved host data width!\n"
1976                      "Defaulting to 32-bit access.\n");
1977                 host->push_data = dw_mci_push_data32;
1978                 host->pull_data = dw_mci_pull_data32;
1979                 width = 32;
1980                 host->data_shift = 2;
1981         }
1982
1983         /* Reset all blocks */
1984         if (!mci_wait_reset(&host->dev, host)) {
1985                 ret = -ENODEV;
1986                 goto err_dmaunmap;
1987         }
1988
1989         /* Clear the interrupts for the host controller */
1990         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1991         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1992
1993         /* Put in max timeout */
1994         mci_writel(host, TMOUT, 0xFFFFFFFF);
1995
1996         /*
1997          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1998          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1999          */
2000         if (!host->pdata->fifo_depth) {
2001                 /*
2002                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2003                  * have been overwritten by the bootloader, just like we're
2004                  * about to do, so if you know the value for your hardware, you
2005                  * should put it in the platform data.
2006                  */
2007                 fifo_size = mci_readl(host, FIFOTH);
2008                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2009         } else {
2010                 fifo_size = host->pdata->fifo_depth;
2011         }
2012         host->fifo_depth = fifo_size;
2013         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2014                         ((fifo_size/2) << 0));
2015         mci_writel(host, FIFOTH, host->fifoth_val);
2016
2017         /* disable clock to CIU */
2018         mci_writel(host, CLKENA, 0);
2019         mci_writel(host, CLKSRC, 0);
2020
2021         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2022         host->card_workqueue = alloc_workqueue("dw-mci-card",
2023                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2024         if (!host->card_workqueue)
2025                 goto err_dmaunmap;
2026         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2027         ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
2028         if (ret)
2029                 goto err_workqueue;
2030
2031         if (host->pdata->num_slots)
2032                 host->num_slots = host->pdata->num_slots;
2033         else
2034                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2035
2036         /* We need at least one slot to succeed */
2037         for (i = 0; i < host->num_slots; i++) {
2038                 ret = dw_mci_init_slot(host, i);
2039                 if (ret) {
2040                         ret = -ENODEV;
2041                         goto err_init_slot;
2042                 }
2043         }
2044
2045         /*
2046          * In 2.40a spec, Data offset is changed.
2047          * Need to check the version-id and set data-offset for DATA register.
2048          */
2049         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2050         dev_info(&host->dev, "Version ID is %04x\n", host->verid);
2051
2052         if (host->verid < DW_MMC_240A)
2053                 host->data_offset = DATA_OFFSET;
2054         else
2055                 host->data_offset = DATA_240A_OFFSET;
2056
2057         /*
2058          * Enable interrupts for command done, data over, data empty, card det,
2059          * receive ready and error such as transmit, receive timeout, crc error
2060          */
2061         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2062         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2063                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2064                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2065         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2066
2067         dev_info(&host->dev, "DW MMC controller at irq %d, "
2068                  "%d bit host data width, "
2069                  "%u deep fifo\n",
2070                  host->irq, width, fifo_size);
2071         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2072                 dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n");
2073
2074         return 0;
2075
2076 err_init_slot:
2077         /* De-init any initialized slots */
2078         while (i > 0) {
2079                 if (host->slot[i])
2080                         dw_mci_cleanup_slot(host->slot[i], i);
2081                 i--;
2082         }
2083         free_irq(host->irq, host);
2084
2085 err_workqueue:
2086         destroy_workqueue(host->card_workqueue);
2087
2088 err_dmaunmap:
2089         if (host->use_dma && host->dma_ops->exit)
2090                 host->dma_ops->exit(host);
2091         dma_free_coherent(&host->dev, PAGE_SIZE,
2092                           host->sg_cpu, host->sg_dma);
2093
2094         if (host->vmmc) {
2095                 regulator_disable(host->vmmc);
2096                 regulator_put(host->vmmc);
2097         }
2098         return ret;
2099 }
2100 EXPORT_SYMBOL(dw_mci_probe);
2101
2102 void dw_mci_remove(struct dw_mci *host)
2103 {
2104         int i;
2105
2106         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2107         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2108
2109         for (i = 0; i < host->num_slots; i++) {
2110                 dev_dbg(&host->dev, "remove slot %d\n", i);
2111                 if (host->slot[i])
2112                         dw_mci_cleanup_slot(host->slot[i], i);
2113         }
2114
2115         /* disable clock to CIU */
2116         mci_writel(host, CLKENA, 0);
2117         mci_writel(host, CLKSRC, 0);
2118
2119         free_irq(host->irq, host);
2120         destroy_workqueue(host->card_workqueue);
2121         dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2122
2123         if (host->use_dma && host->dma_ops->exit)
2124                 host->dma_ops->exit(host);
2125
2126         if (host->vmmc) {
2127                 regulator_disable(host->vmmc);
2128                 regulator_put(host->vmmc);
2129         }
2130
2131 }
2132 EXPORT_SYMBOL(dw_mci_remove);
2133
2134
2135
2136 #ifdef CONFIG_PM_SLEEP
2137 /*
2138  * TODO: we should probably disable the clock to the card in the suspend path.
2139  */
2140 int dw_mci_suspend(struct dw_mci *host)
2141 {
2142         int i, ret = 0;
2143
2144         for (i = 0; i < host->num_slots; i++) {
2145                 struct dw_mci_slot *slot = host->slot[i];
2146                 if (!slot)
2147                         continue;
2148                 ret = mmc_suspend_host(slot->mmc);
2149                 if (ret < 0) {
2150                         while (--i >= 0) {
2151                                 slot = host->slot[i];
2152                                 if (slot)
2153                                         mmc_resume_host(host->slot[i]->mmc);
2154                         }
2155                         return ret;
2156                 }
2157         }
2158
2159         if (host->vmmc)
2160                 regulator_disable(host->vmmc);
2161
2162         return 0;
2163 }
2164 EXPORT_SYMBOL(dw_mci_suspend);
2165
2166 int dw_mci_resume(struct dw_mci *host)
2167 {
2168         int i, ret;
2169
2170         if (host->vmmc)
2171                 regulator_enable(host->vmmc);
2172
2173         if (host->dma_ops->init)
2174                 host->dma_ops->init(host);
2175
2176         if (!mci_wait_reset(&host->dev, host)) {
2177                 ret = -ENODEV;
2178                 return ret;
2179         }
2180
2181         /* Restore the old value at FIFOTH register */
2182         mci_writel(host, FIFOTH, host->fifoth_val);
2183
2184         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2185         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2186                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2187                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2188         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2189
2190         for (i = 0; i < host->num_slots; i++) {
2191                 struct dw_mci_slot *slot = host->slot[i];
2192                 if (!slot)
2193                         continue;
2194                 ret = mmc_resume_host(host->slot[i]->mmc);
2195                 if (ret < 0)
2196                         return ret;
2197         }
2198         return 0;
2199 }
2200 EXPORT_SYMBOL(dw_mci_resume);
2201 #endif /* CONFIG_PM_SLEEP */
2202
2203 static int __init dw_mci_init(void)
2204 {
2205         printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2206         return 0;
2207 }
2208
2209 static void __exit dw_mci_exit(void)
2210 {
2211 }
2212
2213 module_init(dw_mci_init);
2214 module_exit(dw_mci_exit);
2215
2216 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2217 MODULE_AUTHOR("NXP Semiconductor VietNam");
2218 MODULE_AUTHOR("Imagination Technologies Ltd");
2219 MODULE_LICENSE("GPL v2");