drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/bitops.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/of.h>
  38 #include <linux/of_gpio.h>
  39 #include <linux/mmc/slot-gpio.h>
  40
  41 #include "dw_mmc.h"
  42
  43 /* Common flag combinations */
  44 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  45                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  46                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  47 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  48                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  49 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  50                                  DW_MCI_CMD_ERROR_FLAGS)
  51 #define DW_MCI_SEND_STATUS      1
  52 #define DW_MCI_RECV_STATUS      2
  53 #define DW_MCI_DMA_THRESHOLD    16
  54
  55 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  56 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  57
  58 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  59                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  60                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  61                                  SDMMC_IDMAC_INT_TI)
  62
  63 #define DESC_RING_BUF_SZ        PAGE_SIZE
  64
  65 struct idmac_desc_64addr {
  66         u32             des0;   /* Control Descriptor */
  67
  68         u32             des1;   /* Reserved */
  69
  70         u32             des2;   /*Buffer sizes */
  71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  72         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  73          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  74
  75         u32             des3;   /* Reserved */
  76
  77         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  78         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  79
  80         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  81         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  82 };
  83
  84 struct idmac_desc {
  85         __le32          des0;   /* Control Descriptor */
  86 #define IDMAC_DES0_DIC  BIT(1)
  87 #define IDMAC_DES0_LD   BIT(2)
  88 #define IDMAC_DES0_FD   BIT(3)
  89 #define IDMAC_DES0_CH   BIT(4)
  90 #define IDMAC_DES0_ER   BIT(5)
  91 #define IDMAC_DES0_CES  BIT(30)
  92 #define IDMAC_DES0_OWN  BIT(31)
  93
  94         __le32          des1;   /* Buffer sizes */
  95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  96         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  97
  98         __le32          des2;   /* buffer 1 physical address */
  99
 100         __le32          des3;   /* buffer 2 physical address */
 101 };
 102
 103 /* Each descriptor can transfer up to 4KB of data in chained mode */
 104 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 105
 106 static bool dw_mci_reset(struct dw_mci *host);
 107 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 108 static int dw_mci_card_busy(struct mmc_host *mmc);
 109 static int dw_mci_get_cd(struct mmc_host *mmc);
 110
 111 #if defined(CONFIG_DEBUG_FS)
 112 static int dw_mci_req_show(struct seq_file *s, void *v)
 113 {
 114         struct dw_mci_slot *slot = s->private;
 115         struct mmc_request *mrq;
 116         struct mmc_command *cmd;
 117         struct mmc_command *stop;
 118         struct mmc_data *data;
 119
 120         /* Make sure we get a consistent snapshot */
 121         spin_lock_bh(&slot->host->lock);
 122         mrq = slot->mrq;
 123
 124         if (mrq) {
 125                 cmd = mrq->cmd;
 126                 data = mrq->data;
 127                 stop = mrq->stop;
 128
 129                 if (cmd)
 130                         seq_printf(s,
 131                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 132                                    cmd->opcode, cmd->arg, cmd->flags,
 133                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 134                                    cmd->resp[2], cmd->error);
 135                 if (data)
 136                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 137                                    data->bytes_xfered, data->blocks,
 138                                    data->blksz, data->flags, data->error);
 139                 if (stop)
 140                         seq_printf(s,
 141                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 142                                    stop->opcode, stop->arg, stop->flags,
 143                                    stop->resp[0], stop->resp[1], stop->resp[2],
 144                                    stop->resp[2], stop->error);
 145         }
 146
 147         spin_unlock_bh(&slot->host->lock);
 148
 149         return 0;
 150 }
 151
 152 static int dw_mci_req_open(struct inode *inode, struct file *file)
 153 {
 154         return single_open(file, dw_mci_req_show, inode->i_private);
 155 }
 156
 157 static const struct file_operations dw_mci_req_fops = {
 158         .owner          = THIS_MODULE,
 159         .open           = dw_mci_req_open,
 160         .read           = seq_read,
 161         .llseek         = seq_lseek,
 162         .release        = single_release,
 163 };
 164
 165 static int dw_mci_regs_show(struct seq_file *s, void *v)
 166 {
 167         struct dw_mci *host = s->private;
 168
 169         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 170         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 171         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 172         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 173         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 174         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 175
 176         return 0;
 177 }
 178
 179 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 180 {
 181         return single_open(file, dw_mci_regs_show, inode->i_private);
 182 }
 183
 184 static const struct file_operations dw_mci_regs_fops = {
 185         .owner          = THIS_MODULE,
 186         .open           = dw_mci_regs_open,
 187         .read           = seq_read,
 188         .llseek         = seq_lseek,
 189         .release        = single_release,
 190 };
 191
 192 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 193 {
 194         struct mmc_host *mmc = slot->mmc;
 195         struct dw_mci *host = slot->host;
 196         struct dentry *root;
 197         struct dentry *node;
 198
 199         root = mmc->debugfs_root;
 200         if (!root)
 201                 return;
 202
 203         node = debugfs_create_file("regs", S_IRUSR, root, host,
 204                                    &dw_mci_regs_fops);
 205         if (!node)
 206                 goto err;
 207
 208         node = debugfs_create_file("req", S_IRUSR, root, slot,
 209                                    &dw_mci_req_fops);
 210         if (!node)
 211                 goto err;
 212
 213         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 214         if (!node)
 215                 goto err;
 216
 217         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 218                                   (u32 *)&host->pending_events);
 219         if (!node)
 220                 goto err;
 221
 222         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 223                                   (u32 *)&host->completed_events);
 224         if (!node)
 225                 goto err;
 226
 227         return;
 228
 229 err:
 230         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 231 }
 232 #endif /* defined(CONFIG_DEBUG_FS) */
 233
 234 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 235
 236 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 237 {
 238         struct dw_mci_slot *slot = mmc_priv(mmc);
 239         struct dw_mci *host = slot->host;
 240         u32 cmdr;
 241
 242         cmd->error = -EINPROGRESS;
 243         cmdr = cmd->opcode;
 244
 245         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 246             cmd->opcode == MMC_GO_IDLE_STATE ||
 247             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 248             (cmd->opcode == SD_IO_RW_DIRECT &&
 249              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 250                 cmdr |= SDMMC_CMD_STOP;
 251         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 252                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 253
 254         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 255                 u32 clk_en_a;
 256
 257                 /* Special bit makes CMD11 not die */
 258                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 259
 260                 /* Change state to continue to handle CMD11 weirdness */
 261                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 262                 slot->host->state = STATE_SENDING_CMD11;
 263
 264                 /*
 265                  * We need to disable low power mode (automatic clock stop)
 266                  * while doing voltage switch so we don't confuse the card,
 267                  * since stopping the clock is a specific part of the UHS
 268                  * voltage change dance.
 269                  *
 270                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 271                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 272                  * ever called with a non-zero clock.  That shouldn't happen
 273                  * until the voltage change is all done.
 274                  */
 275                 clk_en_a = mci_readl(host, CLKENA);
 276                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 277                 mci_writel(host, CLKENA, clk_en_a);
 278                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 279                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 280         }
 281
 282         if (cmd->flags & MMC_RSP_PRESENT) {
 283                 /* We expect a response, so set this bit */
 284                 cmdr |= SDMMC_CMD_RESP_EXP;
 285                 if (cmd->flags & MMC_RSP_136)
 286                         cmdr |= SDMMC_CMD_RESP_LONG;
 287         }
 288
 289         if (cmd->flags & MMC_RSP_CRC)
 290                 cmdr |= SDMMC_CMD_RESP_CRC;
 291
 292         if (cmd->data) {
 293                 cmdr |= SDMMC_CMD_DAT_EXP;
 294                 if (cmd->data->flags & MMC_DATA_WRITE)
 295                         cmdr |= SDMMC_CMD_DAT_WR;
 296         }
 297
 298         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 299                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 300
 301         return cmdr;
 302 }
 303
 304 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 305 {
 306         struct mmc_command *stop;
 307         u32 cmdr;
 308
 309         if (!cmd->data)
 310                 return 0;
 311
 312         stop = &host->stop_abort;
 313         cmdr = cmd->opcode;
 314         memset(stop, 0, sizeof(struct mmc_command));
 315
 316         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 317             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 318             cmdr == MMC_WRITE_BLOCK ||
 319             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 320             cmdr == MMC_SEND_TUNING_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 322                 stop->opcode = MMC_STOP_TRANSMISSION;
 323                 stop->arg = 0;
 324                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 325         } else if (cmdr == SD_IO_RW_EXTENDED) {
 326                 stop->opcode = SD_IO_RW_DIRECT;
 327                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 328                              ((cmd->arg >> 28) & 0x7);
 329                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 330         } else {
 331                 return 0;
 332         }
 333
 334         cmdr = stop->opcode | SDMMC_CMD_STOP |
 335                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 336
 337         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
 338                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 339
 340         return cmdr;
 341 }
 342
 343 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 344 {
 345         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 346
 347         /*
 348          * Databook says that before issuing a new data transfer command
 349          * we need to check to see if the card is busy.  Data transfer commands
 350          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 351          *
 352          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 353          * expected.
 354          */
 355         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 356             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 357                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 358                         if (time_after(jiffies, timeout)) {
 359                                 /* Command will fail; we'll pass error then */
 360                                 dev_err(host->dev, "Busy; trying anyway\n");
 361                                 break;
 362                         }
 363                         udelay(10);
 364                 }
 365         }
 366 }
 367
 368 static void dw_mci_start_command(struct dw_mci *host,
 369                                  struct mmc_command *cmd, u32 cmd_flags)
 370 {
 371         host->cmd = cmd;
 372         dev_vdbg(host->dev,
 373                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 374                  cmd->arg, cmd_flags);
 375
 376         mci_writel(host, CMDARG, cmd->arg);
 377         wmb(); /* drain writebuffer */
 378         dw_mci_wait_while_busy(host, cmd_flags);
 379
 380         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 381 }
 382
 383 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 384 {
 385         struct mmc_command *stop = &host->stop_abort;
 386
 387         dw_mci_start_command(host, stop, host->stop_cmdr);
 388 }
 389
 390 /* DMA interface functions */
 391 static void dw_mci_stop_dma(struct dw_mci *host)
 392 {
 393         if (host->using_dma) {
 394                 host->dma_ops->stop(host);
 395                 host->dma_ops->cleanup(host);
 396         }
 397
 398         /* Data transfer was stopped by the interrupt handler */
 399         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 400 }
 401
 402 static int dw_mci_get_dma_dir(struct mmc_data *data)
 403 {
 404         if (data->flags & MMC_DATA_WRITE)
 405                 return DMA_TO_DEVICE;
 406         else
 407                 return DMA_FROM_DEVICE;
 408 }
 409
 410 static void dw_mci_dma_cleanup(struct dw_mci *host)
 411 {
 412         struct mmc_data *data = host->data;
 413
 414         if (data && data->host_cookie == COOKIE_MAPPED) {
 415                 dma_unmap_sg(host->dev,
 416                              data->sg,
 417                              data->sg_len,
 418                              dw_mci_get_dma_dir(data));
 419                 data->host_cookie = COOKIE_UNMAPPED;
 420         }
 421 }
 422
 423 static void dw_mci_idmac_reset(struct dw_mci *host)
 424 {
 425         u32 bmod = mci_readl(host, BMOD);
 426         /* Software reset of DMA */
 427         bmod |= SDMMC_IDMAC_SWRESET;
 428         mci_writel(host, BMOD, bmod);
 429 }
 430
 431 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 432 {
 433         u32 temp;
 434
 435         /* Disable and reset the IDMAC interface */
 436         temp = mci_readl(host, CTRL);
 437         temp &= ~SDMMC_CTRL_USE_IDMAC;
 438         temp |= SDMMC_CTRL_DMA_RESET;
 439         mci_writel(host, CTRL, temp);
 440
 441         /* Stop the IDMAC running */
 442         temp = mci_readl(host, BMOD);
 443         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 444         temp |= SDMMC_IDMAC_SWRESET;
 445         mci_writel(host, BMOD, temp);
 446 }
 447
 448 static void dw_mci_dmac_complete_dma(void *arg)
 449 {
 450         struct dw_mci *host = arg;
 451         struct mmc_data *data = host->data;
 452
 453         dev_vdbg(host->dev, "DMA complete\n");
 454
 455         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 456             data && (data->flags & MMC_DATA_READ))
 457                 /* Invalidate cache after read */
 458                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 459                                     data->sg,
 460                                     data->sg_len,
 461                                     DMA_FROM_DEVICE);
 462
 463         host->dma_ops->cleanup(host);
 464
 465         /*
 466          * If the card was removed, data will be NULL. No point in trying to
 467          * send the stop command or waiting for NBUSY in this case.
 468          */
 469         if (data) {
 470                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 471                 tasklet_schedule(&host->tasklet);
 472         }
 473 }
 474
 475 static int dw_mci_idmac_init(struct dw_mci *host)
 476 {
 477         int i;
 478
 479         if (host->dma_64bit_address == 1) {
 480                 struct idmac_desc_64addr *p;
 481                 /* Number of descriptors in the ring buffer */
 482                 host->ring_size =
 483                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 484
 485                 /* Forward link the descriptor list */
 486                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 487                                                                 i++, p++) {
 488                         p->des6 = (host->sg_dma +
 489                                         (sizeof(struct idmac_desc_64addr) *
 490                                                         (i + 1))) & 0xffffffff;
 491
 492                         p->des7 = (u64)(host->sg_dma +
 493                                         (sizeof(struct idmac_desc_64addr) *
 494                                                         (i + 1))) >> 32;
 495                         /* Initialize reserved and buffer size fields to "0" */
 496                         p->des1 = 0;
 497                         p->des2 = 0;
 498                         p->des3 = 0;
 499                 }
 500
 501                 /* Set the last descriptor as the end-of-ring descriptor */
 502                 p->des6 = host->sg_dma & 0xffffffff;
 503                 p->des7 = (u64)host->sg_dma >> 32;
 504                 p->des0 = IDMAC_DES0_ER;
 505
 506         } else {
 507                 struct idmac_desc *p;
 508                 /* Number of descriptors in the ring buffer */
 509                 host->ring_size =
 510                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 511
 512                 /* Forward link the descriptor list */
 513                 for (i = 0, p = host->sg_cpu;
 514                      i < host->ring_size - 1;
 515                      i++, p++) {
 516                         p->des3 = cpu_to_le32(host->sg_dma +
 517                                         (sizeof(struct idmac_desc) * (i + 1)));
 518                         p->des1 = 0;
 519                 }
 520
 521                 /* Set the last descriptor as the end-of-ring descriptor */
 522                 p->des3 = cpu_to_le32(host->sg_dma);
 523                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 524         }
 525
 526         dw_mci_idmac_reset(host);
 527
 528         if (host->dma_64bit_address == 1) {
 529                 /* Mask out interrupts - get Tx & Rx complete only */
 530                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 531                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 532                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 533
 534                 /* Set the descriptor base address */
 535                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 536                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 537
 538         } else {
 539                 /* Mask out interrupts - get Tx & Rx complete only */
 540                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 541                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 542                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 543
 544                 /* Set the descriptor base address */
 545                 mci_writel(host, DBADDR, host->sg_dma);
 546         }
 547
 548         return 0;
 549 }
 550
 551 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 552                                          struct mmc_data *data,
 553                                          unsigned int sg_len)
 554 {
 555         unsigned int desc_len;
 556         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 557         unsigned long timeout;
 558         int i;
 559
 560         desc_first = desc_last = desc = host->sg_cpu;
 561
 562         for (i = 0; i < sg_len; i++) {
 563                 unsigned int length = sg_dma_len(&data->sg[i]);
 564
 565                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 566
 567                 for ( ; length ; desc++) {
 568                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 569                                    length : DW_MCI_DESC_DATA_LENGTH;
 570
 571                         length -= desc_len;
 572
 573                         /*
 574                          * Wait for the former clear OWN bit operation
 575                          * of IDMAC to make sure that this descriptor
 576                          * isn't still owned by IDMAC as IDMAC's write
 577                          * ops and CPU's read ops are asynchronous.
 578                          */
 579                         timeout = jiffies + msecs_to_jiffies(100);
 580                         while (readl(&desc->des0) & IDMAC_DES0_OWN) {
 581                                 if (time_after(jiffies, timeout))
 582                                         goto err_own_bit;
 583                                 udelay(10);
 584                         }
 585
 586                         /*
 587                          * Set the OWN bit and disable interrupts
 588                          * for this descriptor
 589                          */
 590                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 591                                                 IDMAC_DES0_CH;
 592
 593                         /* Buffer length */
 594                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 595
 596                         /* Physical address to DMA to/from */
 597                         desc->des4 = mem_addr & 0xffffffff;
 598                         desc->des5 = mem_addr >> 32;
 599
 600                         /* Update physical address for the next desc */
 601                         mem_addr += desc_len;
 602
 603                         /* Save pointer to the last descriptor */
 604                         desc_last = desc;
 605                 }
 606         }
 607
 608         /* Set first descriptor */
 609         desc_first->des0 |= IDMAC_DES0_FD;
 610
 611         /* Set last descriptor */
 612         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 613         desc_last->des0 |= IDMAC_DES0_LD;
 614
 615         return 0;
 616 err_own_bit:
 617         /* restore the descriptor chain as it's polluted */
 618         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 619         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 620         dw_mci_idmac_init(host);
 621         return -EINVAL;
 622 }
 623
 624
 625 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 626                                          struct mmc_data *data,
 627                                          unsigned int sg_len)
 628 {
 629         unsigned int desc_len;
 630         struct idmac_desc *desc_first, *desc_last, *desc;
 631         unsigned long timeout;
 632         int i;
 633
 634         desc_first = desc_last = desc = host->sg_cpu;
 635
 636         for (i = 0; i < sg_len; i++) {
 637                 unsigned int length = sg_dma_len(&data->sg[i]);
 638
 639                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 640
 641                 for ( ; length ; desc++) {
 642                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 643                                    length : DW_MCI_DESC_DATA_LENGTH;
 644
 645                         length -= desc_len;
 646
 647                         /*
 648                          * Wait for the former clear OWN bit operation
 649                          * of IDMAC to make sure that this descriptor
 650                          * isn't still owned by IDMAC as IDMAC's write
 651                          * ops and CPU's read ops are asynchronous.
 652                          */
 653                         timeout = jiffies + msecs_to_jiffies(100);
 654                         while (readl(&desc->des0) &
 655                                cpu_to_le32(IDMAC_DES0_OWN)) {
 656                                 if (time_after(jiffies, timeout))
 657                                         goto err_own_bit;
 658                                 udelay(10);
 659                         }
 660
 661                         /*
 662                          * Set the OWN bit and disable interrupts
 663                          * for this descriptor
 664                          */
 665                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 666                                                  IDMAC_DES0_DIC |
 667                                                  IDMAC_DES0_CH);
 668
 669                         /* Buffer length */
 670                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 671
 672                         /* Physical address to DMA to/from */
 673                         desc->des2 = cpu_to_le32(mem_addr);
 674
 675                         /* Update physical address for the next desc */
 676                         mem_addr += desc_len;
 677
 678                         /* Save pointer to the last descriptor */
 679                         desc_last = desc;
 680                 }
 681         }
 682
 683         /* Set first descriptor */
 684         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 685
 686         /* Set last descriptor */
 687         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 688                                        IDMAC_DES0_DIC));
 689         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 690
 691         return 0;
 692 err_own_bit:
 693         /* restore the descriptor chain as it's polluted */
 694         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 695         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 696         dw_mci_idmac_init(host);
 697         return -EINVAL;
 698 }
 699
 700 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 701 {
 702         u32 temp;
 703         int ret;
 704
 705         if (host->dma_64bit_address == 1)
 706                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 707         else
 708                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 709
 710         if (ret)
 711                 goto out;
 712
 713         /* drain writebuffer */
 714         wmb();
 715
 716         /* Make sure to reset DMA in case we did PIO before this */
 717         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 718         dw_mci_idmac_reset(host);
 719
 720         /* Select IDMAC interface */
 721         temp = mci_readl(host, CTRL);
 722         temp |= SDMMC_CTRL_USE_IDMAC;
 723         mci_writel(host, CTRL, temp);
 724
 725         /* drain writebuffer */
 726         wmb();
 727
 728         /* Enable the IDMAC */
 729         temp = mci_readl(host, BMOD);
 730         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 731         mci_writel(host, BMOD, temp);
 732
 733         /* Start it running */
 734         mci_writel(host, PLDMND, 1);
 735
 736 out:
 737         return ret;
 738 }
 739
 740 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 741         .init = dw_mci_idmac_init,
 742         .start = dw_mci_idmac_start_dma,
 743         .stop = dw_mci_idmac_stop_dma,
 744         .complete = dw_mci_dmac_complete_dma,
 745         .cleanup = dw_mci_dma_cleanup,
 746 };
 747
 748 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 749 {
 750         dmaengine_terminate_async(host->dms->ch);
 751 }
 752
 753 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 754                                             unsigned int sg_len)
 755 {
 756         struct dma_slave_config cfg;
 757         struct dma_async_tx_descriptor *desc = NULL;
 758         struct scatterlist *sgl = host->data->sg;
 759         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 760         u32 sg_elems = host->data->sg_len;
 761         u32 fifoth_val;
 762         u32 fifo_offset = host->fifo_reg - host->regs;
 763         int ret = 0;
 764
 765         /* Set external dma config: burst size, burst width */
 766         cfg.dst_addr = host->phy_regs + fifo_offset;
 767         cfg.src_addr = cfg.dst_addr;
 768         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 769         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 770
 771         /* Match burst msize with external dma config */
 772         fifoth_val = mci_readl(host, FIFOTH);
 773         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 774         cfg.src_maxburst = cfg.dst_maxburst;
 775
 776         if (host->data->flags & MMC_DATA_WRITE)
 777                 cfg.direction = DMA_MEM_TO_DEV;
 778         else
 779                 cfg.direction = DMA_DEV_TO_MEM;
 780
 781         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 782         if (ret) {
 783                 dev_err(host->dev, "Failed to config edmac.\n");
 784                 return -EBUSY;
 785         }
 786
 787         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 788                                        sg_len, cfg.direction,
 789                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 790         if (!desc) {
 791                 dev_err(host->dev, "Can't prepare slave sg.\n");
 792                 return -EBUSY;
 793         }
 794
 795         /* Set dw_mci_dmac_complete_dma as callback */
 796         desc->callback = dw_mci_dmac_complete_dma;
 797         desc->callback_param = (void *)host;
 798         dmaengine_submit(desc);
 799
 800         /* Flush cache before write */
 801         if (host->data->flags & MMC_DATA_WRITE)
 802                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 803                                        sg_elems, DMA_TO_DEVICE);
 804
 805         dma_async_issue_pending(host->dms->ch);
 806
 807         return 0;
 808 }
 809
 810 static int dw_mci_edmac_init(struct dw_mci *host)
 811 {
 812         /* Request external dma channel */
 813         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 814         if (!host->dms)
 815                 return -ENOMEM;
 816
 817         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 818         if (!host->dms->ch) {
 819                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 820                 kfree(host->dms);
 821                 host->dms = NULL;
 822                 return -ENXIO;
 823         }
 824
 825         return 0;
 826 }
 827
 828 static void dw_mci_edmac_exit(struct dw_mci *host)
 829 {
 830         if (host->dms) {
 831                 if (host->dms->ch) {
 832                         dma_release_channel(host->dms->ch);
 833                         host->dms->ch = NULL;
 834                 }
 835                 kfree(host->dms);
 836                 host->dms = NULL;
 837         }
 838 }
 839
 840 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 841         .init = dw_mci_edmac_init,
 842         .exit = dw_mci_edmac_exit,
 843         .start = dw_mci_edmac_start_dma,
 844         .stop = dw_mci_edmac_stop_dma,
 845         .complete = dw_mci_dmac_complete_dma,
 846         .cleanup = dw_mci_dma_cleanup,
 847 };
 848
 849 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 850                                    struct mmc_data *data,
 851                                    int cookie)
 852 {
 853         struct scatterlist *sg;
 854         unsigned int i, sg_len;
 855
 856         if (data->host_cookie == COOKIE_PRE_MAPPED)
 857                 return data->sg_len;
 858
 859         /*
 860          * We don't do DMA on "complex" transfers, i.e. with
 861          * non-word-aligned buffers or lengths. Also, we don't bother
 862          * with all the DMA setup overhead for short transfers.
 863          */
 864         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 865                 return -EINVAL;
 866
 867         if (data->blksz & 3)
 868                 return -EINVAL;
 869
 870         for_each_sg(data->sg, sg, data->sg_len, i) {
 871                 if (sg->offset & 3 || sg->length & 3)
 872                         return -EINVAL;
 873         }
 874
 875         sg_len = dma_map_sg(host->dev,
 876                             data->sg,
 877                             data->sg_len,
 878                             dw_mci_get_dma_dir(data));
 879         if (sg_len == 0)
 880                 return -EINVAL;
 881
 882         data->host_cookie = cookie;
 883
 884         return sg_len;
 885 }
 886
 887 static void dw_mci_pre_req(struct mmc_host *mmc,
 888                            struct mmc_request *mrq)
 889 {
 890         struct dw_mci_slot *slot = mmc_priv(mmc);
 891         struct mmc_data *data = mrq->data;
 892
 893         if (!slot->host->use_dma || !data)
 894                 return;
 895
 896         /* This data might be unmapped at this time */
 897         data->host_cookie = COOKIE_UNMAPPED;
 898
 899         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 900                                 COOKIE_PRE_MAPPED) < 0)
 901                 data->host_cookie = COOKIE_UNMAPPED;
 902 }
 903
 904 static void dw_mci_post_req(struct mmc_host *mmc,
 905                             struct mmc_request *mrq,
 906                             int err)
 907 {
 908         struct dw_mci_slot *slot = mmc_priv(mmc);
 909         struct mmc_data *data = mrq->data;
 910
 911         if (!slot->host->use_dma || !data)
 912                 return;
 913
 914         if (data->host_cookie != COOKIE_UNMAPPED)
 915                 dma_unmap_sg(slot->host->dev,
 916                              data->sg,
 917                              data->sg_len,
 918                              dw_mci_get_dma_dir(data));
 919         data->host_cookie = COOKIE_UNMAPPED;
 920 }
 921
 922 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 923 {
 924         unsigned int blksz = data->blksz;
 925         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 926         u32 fifo_width = 1 << host->data_shift;
 927         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 928         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 929         int idx = ARRAY_SIZE(mszs) - 1;
 930
 931         /* pio should ship this scenario */
 932         if (!host->use_dma)
 933                 return;
 934
 935         tx_wmark = (host->fifo_depth) / 2;
 936         tx_wmark_invers = host->fifo_depth - tx_wmark;
 937
 938         /*
 939          * MSIZE is '1',
 940          * if blksz is not a multiple of the FIFO width
 941          */
 942         if (blksz % fifo_width)
 943                 goto done;
 944
 945         do {
 946                 if (!((blksz_depth % mszs[idx]) ||
 947                      (tx_wmark_invers % mszs[idx]))) {
 948                         msize = idx;
 949                         rx_wmark = mszs[idx] - 1;
 950                         break;
 951                 }
 952         } while (--idx > 0);
 953         /*
 954          * If idx is '0', it won't be tried
 955          * Thus, initial values are uesed
 956          */
 957 done:
 958         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 959         mci_writel(host, FIFOTH, fifoth_val);
 960 }
 961
 962 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
 963 {
 964         unsigned int blksz = data->blksz;
 965         u32 blksz_depth, fifo_depth;
 966         u16 thld_size;
 967         u8 enable;
 968
 969         /*
 970          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 971          * in the FIFO region, so we really shouldn't access it).
 972          */
 973         if (host->verid < DW_MMC_240A ||
 974                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
 975                 return;
 976
 977         /*
 978          * Card write Threshold is introduced since 2.80a
 979          * It's used when HS400 mode is enabled.
 980          */
 981         if (data->flags & MMC_DATA_WRITE &&
 982                 !(host->timing != MMC_TIMING_MMC_HS400))
 983                 return;
 984
 985         if (data->flags & MMC_DATA_WRITE)
 986                 enable = SDMMC_CARD_WR_THR_EN;
 987         else
 988                 enable = SDMMC_CARD_RD_THR_EN;
 989
 990         if (host->timing != MMC_TIMING_MMC_HS200 &&
 991             host->timing != MMC_TIMING_UHS_SDR104)
 992                 goto disable;
 993
 994         blksz_depth = blksz / (1 << host->data_shift);
 995         fifo_depth = host->fifo_depth;
 996
 997         if (blksz_depth > fifo_depth)
 998                 goto disable;
 999
1000         /*
1001          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1002          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1003          * Currently just choose blksz.
1004          */
1005         thld_size = blksz;
1006         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1007         return;
1008
1009 disable:
1010         mci_writel(host, CDTHRCTL, 0);
1011 }
1012
1013 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1014 {
1015         unsigned long irqflags;
1016         int sg_len;
1017         u32 temp;
1018
1019         host->using_dma = 0;
1020
1021         /* If we don't have a channel, we can't do DMA */
1022         if (!host->use_dma)
1023                 return -ENODEV;
1024
1025         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1026         if (sg_len < 0) {
1027                 host->dma_ops->stop(host);
1028                 return sg_len;
1029         }
1030
1031         host->using_dma = 1;
1032
1033         if (host->use_dma == TRANS_MODE_IDMAC)
1034                 dev_vdbg(host->dev,
1035                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1036                          (unsigned long)host->sg_cpu,
1037                          (unsigned long)host->sg_dma,
1038                          sg_len);
1039
1040         /*
1041          * Decide the MSIZE and RX/TX Watermark.
1042          * If current block size is same with previous size,
1043          * no need to update fifoth.
1044          */
1045         if (host->prev_blksz != data->blksz)
1046                 dw_mci_adjust_fifoth(host, data);
1047
1048         /* Enable the DMA interface */
1049         temp = mci_readl(host, CTRL);
1050         temp |= SDMMC_CTRL_DMA_ENABLE;
1051         mci_writel(host, CTRL, temp);
1052
1053         /* Disable RX/TX IRQs, let DMA handle it */
1054         spin_lock_irqsave(&host->irq_lock, irqflags);
1055         temp = mci_readl(host, INTMASK);
1056         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1057         mci_writel(host, INTMASK, temp);
1058         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1059
1060         if (host->dma_ops->start(host, sg_len)) {
1061                 host->dma_ops->stop(host);
1062                 /* We can't do DMA, try PIO for this one */
1063                 dev_dbg(host->dev,
1064                         "%s: fall back to PIO mode for current transfer\n",
1065                         __func__);
1066                 return -ENODEV;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1073 {
1074         unsigned long irqflags;
1075         int flags = SG_MITER_ATOMIC;
1076         u32 temp;
1077
1078         data->error = -EINPROGRESS;
1079
1080         WARN_ON(host->data);
1081         host->sg = NULL;
1082         host->data = data;
1083
1084         if (data->flags & MMC_DATA_READ)
1085                 host->dir_status = DW_MCI_RECV_STATUS;
1086         else
1087                 host->dir_status = DW_MCI_SEND_STATUS;
1088
1089         dw_mci_ctrl_thld(host, data);
1090
1091         if (dw_mci_submit_data_dma(host, data)) {
1092                 if (host->data->flags & MMC_DATA_READ)
1093                         flags |= SG_MITER_TO_SG;
1094                 else
1095                         flags |= SG_MITER_FROM_SG;
1096
1097                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1098                 host->sg = data->sg;
1099                 host->part_buf_start = 0;
1100                 host->part_buf_count = 0;
1101
1102                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1103
1104                 spin_lock_irqsave(&host->irq_lock, irqflags);
1105                 temp = mci_readl(host, INTMASK);
1106                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1107                 mci_writel(host, INTMASK, temp);
1108                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1109
1110                 temp = mci_readl(host, CTRL);
1111                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1112                 mci_writel(host, CTRL, temp);
1113
1114                 /*
1115                  * Use the initial fifoth_val for PIO mode. If wm_algined
1116                  * is set, we set watermark same as data size.
1117                  * If next issued data may be transfered by DMA mode,
1118                  * prev_blksz should be invalidated.
1119                  */
1120                 if (host->wm_aligned)
1121                         dw_mci_adjust_fifoth(host, data);
1122                 else
1123                         mci_writel(host, FIFOTH, host->fifoth_val);
1124                 host->prev_blksz = 0;
1125         } else {
1126                 /*
1127                  * Keep the current block size.
1128                  * It will be used to decide whether to update
1129                  * fifoth register next time.
1130                  */
1131                 host->prev_blksz = data->blksz;
1132         }
1133 }
1134
1135 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1136 {
1137         struct dw_mci *host = slot->host;
1138         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1139         unsigned int cmd_status = 0;
1140
1141         mci_writel(host, CMDARG, arg);
1142         wmb(); /* drain writebuffer */
1143         dw_mci_wait_while_busy(host, cmd);
1144         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1145
1146         while (time_before(jiffies, timeout)) {
1147                 cmd_status = mci_readl(host, CMD);
1148                 if (!(cmd_status & SDMMC_CMD_START))
1149                         return;
1150         }
1151         dev_err(&slot->mmc->class_dev,
1152                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1153                 cmd, arg, cmd_status);
1154 }
1155
1156 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1157 {
1158         struct dw_mci *host = slot->host;
1159         unsigned int clock = slot->clock;
1160         u32 div;
1161         u32 clk_en_a;
1162         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1163
1164         /* We must continue to set bit 28 in CMD until the change is complete */
1165         if (host->state == STATE_WAITING_CMD11_DONE)
1166                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1167
1168         if (!clock) {
1169                 mci_writel(host, CLKENA, 0);
1170                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1171         } else if (clock != host->current_speed || force_clkinit) {
1172                 div = host->bus_hz / clock;
1173                 if (host->bus_hz % clock && host->bus_hz > clock)
1174                         /*
1175                          * move the + 1 after the divide to prevent
1176                          * over-clocking the card.
1177                          */
1178                         div += 1;
1179
1180                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1181
1182                 if ((clock != slot->__clk_old &&
1183                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1184                         force_clkinit) {
1185                         /* Silent the verbose log if calling from PM context */
1186                         if (!force_clkinit)
1187                                 dev_info(&slot->mmc->class_dev,
1188                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1189                                          slot->id, host->bus_hz, clock,
1190                                          div ? ((host->bus_hz / div) >> 1) :
1191                                          host->bus_hz, div);
1192
1193                         /*
1194                          * If card is polling, display the message only
1195                          * one time at boot time.
1196                          */
1197                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1198                                         slot->mmc->f_min == clock)
1199                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1200                 }
1201
1202                 /* disable clock */
1203                 mci_writel(host, CLKENA, 0);
1204                 mci_writel(host, CLKSRC, 0);
1205
1206                 /* inform CIU */
1207                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1208
1209                 /* set clock to desired speed */
1210                 mci_writel(host, CLKDIV, div);
1211
1212                 /* inform CIU */
1213                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1214
1215                 /* enable clock; only low power if no SDIO */
1216                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1217                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1218                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1219                 mci_writel(host, CLKENA, clk_en_a);
1220
1221                 /* inform CIU */
1222                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1223
1224                 /* keep the last clock value that was requested from core */
1225                 slot->__clk_old = clock;
1226         }
1227
1228         host->current_speed = clock;
1229
1230         /* Set the current slot bus width */
1231         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1232 }
1233
1234 static void __dw_mci_start_request(struct dw_mci *host,
1235                                    struct dw_mci_slot *slot,
1236                                    struct mmc_command *cmd)
1237 {
1238         struct mmc_request *mrq;
1239         struct mmc_data *data;
1240         u32 cmdflags;
1241
1242         mrq = slot->mrq;
1243
1244         host->cur_slot = slot;
1245         host->mrq = mrq;
1246
1247         host->pending_events = 0;
1248         host->completed_events = 0;
1249         host->cmd_status = 0;
1250         host->data_status = 0;
1251         host->dir_status = 0;
1252
1253         data = cmd->data;
1254         if (data) {
1255                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1256                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1257                 mci_writel(host, BLKSIZ, data->blksz);
1258         }
1259
1260         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1261
1262         /* this is the first command, send the initialization clock */
1263         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1264                 cmdflags |= SDMMC_CMD_INIT;
1265
1266         if (data) {
1267                 dw_mci_submit_data(host, data);
1268                 wmb(); /* drain writebuffer */
1269         }
1270
1271         dw_mci_start_command(host, cmd, cmdflags);
1272
1273         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1274                 unsigned long irqflags;
1275
1276                 /*
1277                  * Databook says to fail after 2ms w/ no response, but evidence
1278                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1279                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1280                  * is just about to roll over.
1281                  *
1282                  * We do this whole thing under spinlock and only if the
1283                  * command hasn't already completed (indicating the the irq
1284                  * already ran so we don't want the timeout).
1285                  */
1286                 spin_lock_irqsave(&host->irq_lock, irqflags);
1287                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1288                         mod_timer(&host->cmd11_timer,
1289                                 jiffies + msecs_to_jiffies(500) + 1);
1290                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1291         }
1292
1293         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1294 }
1295
1296 static void dw_mci_start_request(struct dw_mci *host,
1297                                  struct dw_mci_slot *slot)
1298 {
1299         struct mmc_request *mrq = slot->mrq;
1300         struct mmc_command *cmd;
1301
1302         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1303         __dw_mci_start_request(host, slot, cmd);
1304 }
1305
1306 /* must be called with host->lock held */
1307 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1308                                  struct mmc_request *mrq)
1309 {
1310         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1311                  host->state);
1312
1313         slot->mrq = mrq;
1314
1315         if (host->state == STATE_WAITING_CMD11_DONE) {
1316                 dev_warn(&slot->mmc->class_dev,
1317                          "Voltage change didn't complete\n");
1318                 /*
1319                  * this case isn't expected to happen, so we can
1320                  * either crash here or just try to continue on
1321                  * in the closest possible state
1322                  */
1323                 host->state = STATE_IDLE;
1324         }
1325
1326         if (host->state == STATE_IDLE) {
1327                 host->state = STATE_SENDING_CMD;
1328                 dw_mci_start_request(host, slot);
1329         } else {
1330                 list_add_tail(&slot->queue_node, &host->queue);
1331         }
1332 }
1333
1334 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1335 {
1336         struct dw_mci_slot *slot = mmc_priv(mmc);
1337         struct dw_mci *host = slot->host;
1338
1339         WARN_ON(slot->mrq);
1340
1341         /*
1342          * The check for card presence and queueing of the request must be
1343          * atomic, otherwise the card could be removed in between and the
1344          * request wouldn't fail until another card was inserted.
1345          */
1346
1347         if (!dw_mci_get_cd(mmc)) {
1348                 mrq->cmd->error = -ENOMEDIUM;
1349                 mmc_request_done(mmc, mrq);
1350                 return;
1351         }
1352
1353         spin_lock_bh(&host->lock);
1354
1355         dw_mci_queue_request(host, slot, mrq);
1356
1357         spin_unlock_bh(&host->lock);
1358 }
1359
1360 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1361 {
1362         struct dw_mci_slot *slot = mmc_priv(mmc);
1363         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1364         u32 regs;
1365         int ret;
1366
1367         switch (ios->bus_width) {
1368         case MMC_BUS_WIDTH_4:
1369                 slot->ctype = SDMMC_CTYPE_4BIT;
1370                 break;
1371         case MMC_BUS_WIDTH_8:
1372                 slot->ctype = SDMMC_CTYPE_8BIT;
1373                 break;
1374         default:
1375                 /* set default 1 bit mode */
1376                 slot->ctype = SDMMC_CTYPE_1BIT;
1377         }
1378
1379         regs = mci_readl(slot->host, UHS_REG);
1380
1381         /* DDR mode set */
1382         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1383             ios->timing == MMC_TIMING_UHS_DDR50 ||
1384             ios->timing == MMC_TIMING_MMC_HS400)
1385                 regs |= ((0x1 << slot->id) << 16);
1386         else
1387                 regs &= ~((0x1 << slot->id) << 16);
1388
1389         mci_writel(slot->host, UHS_REG, regs);
1390         slot->host->timing = ios->timing;
1391
1392         /*
1393          * Use mirror of ios->clock to prevent race with mmc
1394          * core ios update when finding the minimum.
1395          */
1396         slot->clock = ios->clock;
1397
1398         if (drv_data && drv_data->set_ios)
1399                 drv_data->set_ios(slot->host, ios);
1400
1401         switch (ios->power_mode) {
1402         case MMC_POWER_UP:
1403                 if (!IS_ERR(mmc->supply.vmmc)) {
1404                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1405                                         ios->vdd);
1406                         if (ret) {
1407                                 dev_err(slot->host->dev,
1408                                         "failed to enable vmmc regulator\n");
1409                                 /*return, if failed turn on vmmc*/
1410                                 return;
1411                         }
1412                 }
1413                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1414                 regs = mci_readl(slot->host, PWREN);
1415                 regs |= (1 << slot->id);
1416                 mci_writel(slot->host, PWREN, regs);
1417                 break;
1418         case MMC_POWER_ON:
1419                 if (!slot->host->vqmmc_enabled) {
1420                         if (!IS_ERR(mmc->supply.vqmmc)) {
1421                                 ret = regulator_enable(mmc->supply.vqmmc);
1422                                 if (ret < 0)
1423                                         dev_err(slot->host->dev,
1424                                                 "failed to enable vqmmc\n");
1425                                 else
1426                                         slot->host->vqmmc_enabled = true;
1427
1428                         } else {
1429                                 /* Keep track so we don't reset again */
1430                                 slot->host->vqmmc_enabled = true;
1431                         }
1432
1433                         /* Reset our state machine after powering on */
1434                         dw_mci_ctrl_reset(slot->host,
1435                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1436                 }
1437
1438                 /* Adjust clock / bus width after power is up */
1439                 dw_mci_setup_bus(slot, false);
1440
1441                 break;
1442         case MMC_POWER_OFF:
1443                 /* Turn clock off before power goes down */
1444                 dw_mci_setup_bus(slot, false);
1445
1446                 if (!IS_ERR(mmc->supply.vmmc))
1447                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1448
1449                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1450                         regulator_disable(mmc->supply.vqmmc);
1451                 slot->host->vqmmc_enabled = false;
1452
1453                 regs = mci_readl(slot->host, PWREN);
1454                 regs &= ~(1 << slot->id);
1455                 mci_writel(slot->host, PWREN, regs);
1456                 break;
1457         default:
1458                 break;
1459         }
1460
1461         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1462                 slot->host->state = STATE_IDLE;
1463 }
1464
1465 static int dw_mci_card_busy(struct mmc_host *mmc)
1466 {
1467         struct dw_mci_slot *slot = mmc_priv(mmc);
1468         u32 status;
1469
1470         /*
1471          * Check the busy bit which is low when DAT[3:0]
1472          * (the data lines) are 0000
1473          */
1474         status = mci_readl(slot->host, STATUS);
1475
1476         return !!(status & SDMMC_STATUS_BUSY);
1477 }
1478
1479 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1480 {
1481         struct dw_mci_slot *slot = mmc_priv(mmc);
1482         struct dw_mci *host = slot->host;
1483         const struct dw_mci_drv_data *drv_data = host->drv_data;
1484         u32 uhs;
1485         u32 v18 = SDMMC_UHS_18V << slot->id;
1486         int ret;
1487
1488         if (drv_data && drv_data->switch_voltage)
1489                 return drv_data->switch_voltage(mmc, ios);
1490
1491         /*
1492          * Program the voltage.  Note that some instances of dw_mmc may use
1493          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1494          * does no harm but you need to set the regulator directly.  Try both.
1495          */
1496         uhs = mci_readl(host, UHS_REG);
1497         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1498                 uhs &= ~v18;
1499         else
1500                 uhs |= v18;
1501
1502         if (!IS_ERR(mmc->supply.vqmmc)) {
1503                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1504
1505                 if (ret) {
1506                         dev_dbg(&mmc->class_dev,
1507                                          "Regulator set error %d - %s V\n",
1508                                          ret, uhs & v18 ? "1.8" : "3.3");
1509                         return ret;
1510                 }
1511         }
1512         mci_writel(host, UHS_REG, uhs);
1513
1514         return 0;
1515 }
1516
1517 static int dw_mci_get_ro(struct mmc_host *mmc)
1518 {
1519         int read_only;
1520         struct dw_mci_slot *slot = mmc_priv(mmc);
1521         int gpio_ro = mmc_gpio_get_ro(mmc);
1522
1523         /* Use platform get_ro function, else try on board write protect */
1524         if (gpio_ro >= 0)
1525                 read_only = gpio_ro;
1526         else
1527                 read_only =
1528                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1529
1530         dev_dbg(&mmc->class_dev, "card is %s\n",
1531                 read_only ? "read-only" : "read-write");
1532
1533         return read_only;
1534 }
1535
1536 static int dw_mci_get_cd(struct mmc_host *mmc)
1537 {
1538         int present;
1539         struct dw_mci_slot *slot = mmc_priv(mmc);
1540         struct dw_mci *host = slot->host;
1541         int gpio_cd = mmc_gpio_get_cd(mmc);
1542
1543         /* Use platform get_cd function, else try onboard card detect */
1544         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1545                                 || !mmc_card_is_removable(mmc))) {
1546                 present = 1;
1547
1548                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1549                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1550                                 dev_info(&mmc->class_dev,
1551                                         "card is polling.\n");
1552                         } else {
1553                                 dev_info(&mmc->class_dev,
1554                                         "card is non-removable.\n");
1555                         }
1556                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1557                 }
1558
1559                 return present;
1560         } else if (gpio_cd >= 0)
1561                 present = gpio_cd;
1562         else
1563                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1564                         == 0 ? 1 : 0;
1565
1566         spin_lock_bh(&host->lock);
1567         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1568                 dev_dbg(&mmc->class_dev, "card is present\n");
1569         else if (!present &&
1570                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1571                 dev_dbg(&mmc->class_dev, "card is not present\n");
1572         spin_unlock_bh(&host->lock);
1573
1574         return present;
1575 }
1576
1577 static void dw_mci_hw_reset(struct mmc_host *mmc)
1578 {
1579         struct dw_mci_slot *slot = mmc_priv(mmc);
1580         struct dw_mci *host = slot->host;
1581         int reset;
1582
1583         if (host->use_dma == TRANS_MODE_IDMAC)
1584                 dw_mci_idmac_reset(host);
1585
1586         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1587                                      SDMMC_CTRL_FIFO_RESET))
1588                 return;
1589
1590         /*
1591          * According to eMMC spec, card reset procedure:
1592          * tRstW >= 1us:   RST_n pulse width
1593          * tRSCA >= 200us: RST_n to Command time
1594          * tRSTH >= 1us:   RST_n high period
1595          */
1596         reset = mci_readl(host, RST_N);
1597         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1598         mci_writel(host, RST_N, reset);
1599         usleep_range(1, 2);
1600         reset |= SDMMC_RST_HWACTIVE << slot->id;
1601         mci_writel(host, RST_N, reset);
1602         usleep_range(200, 300);
1603 }
1604
1605 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1606 {
1607         struct dw_mci_slot *slot = mmc_priv(mmc);
1608         struct dw_mci *host = slot->host;
1609
1610         /*
1611          * Low power mode will stop the card clock when idle.  According to the
1612          * description of the CLKENA register we should disable low power mode
1613          * for SDIO cards if we need SDIO interrupts to work.
1614          */
1615         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1616                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1617                 u32 clk_en_a_old;
1618                 u32 clk_en_a;
1619
1620                 clk_en_a_old = mci_readl(host, CLKENA);
1621
1622                 if (card->type == MMC_TYPE_SDIO ||
1623                     card->type == MMC_TYPE_SD_COMBO) {
1624                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1625                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1626                 } else {
1627                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1628                         clk_en_a = clk_en_a_old | clken_low_pwr;
1629                 }
1630
1631                 if (clk_en_a != clk_en_a_old) {
1632                         mci_writel(host, CLKENA, clk_en_a);
1633                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1634                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1635                 }
1636         }
1637 }
1638
1639 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1640 {
1641         struct dw_mci_slot *slot = mmc_priv(mmc);
1642         struct dw_mci *host = slot->host;
1643         unsigned long irqflags;
1644         u32 int_mask;
1645
1646         spin_lock_irqsave(&host->irq_lock, irqflags);
1647
1648         /* Enable/disable Slot Specific SDIO interrupt */
1649         int_mask = mci_readl(host, INTMASK);
1650         if (enb)
1651                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1652         else
1653                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1654         mci_writel(host, INTMASK, int_mask);
1655
1656         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1657 }
1658
1659 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1660 {
1661         struct dw_mci_slot *slot = mmc_priv(mmc);
1662         struct dw_mci *host = slot->host;
1663         const struct dw_mci_drv_data *drv_data = host->drv_data;
1664         int err = -EINVAL;
1665
1666         if (drv_data && drv_data->execute_tuning)
1667                 err = drv_data->execute_tuning(slot, opcode);
1668         return err;
1669 }
1670
1671 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1672                                        struct mmc_ios *ios)
1673 {
1674         struct dw_mci_slot *slot = mmc_priv(mmc);
1675         struct dw_mci *host = slot->host;
1676         const struct dw_mci_drv_data *drv_data = host->drv_data;
1677
1678         if (drv_data && drv_data->prepare_hs400_tuning)
1679                 return drv_data->prepare_hs400_tuning(host, ios);
1680
1681         return 0;
1682 }
1683
1684 static const struct mmc_host_ops dw_mci_ops = {
1685         .request                = dw_mci_request,
1686         .pre_req                = dw_mci_pre_req,
1687         .post_req               = dw_mci_post_req,
1688         .set_ios                = dw_mci_set_ios,
1689         .get_ro                 = dw_mci_get_ro,
1690         .get_cd                 = dw_mci_get_cd,
1691         .hw_reset               = dw_mci_hw_reset,
1692         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1693         .execute_tuning         = dw_mci_execute_tuning,
1694         .card_busy              = dw_mci_card_busy,
1695         .start_signal_voltage_switch = dw_mci_switch_voltage,
1696         .init_card              = dw_mci_init_card,
1697         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1698 };
1699
1700 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1701         __releases(&host->lock)
1702         __acquires(&host->lock)
1703 {
1704         struct dw_mci_slot *slot;
1705         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1706
1707         WARN_ON(host->cmd || host->data);
1708
1709         host->cur_slot->mrq = NULL;
1710         host->mrq = NULL;
1711         if (!list_empty(&host->queue)) {
1712                 slot = list_entry(host->queue.next,
1713                                   struct dw_mci_slot, queue_node);
1714                 list_del(&slot->queue_node);
1715                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1716                          mmc_hostname(slot->mmc));
1717                 host->state = STATE_SENDING_CMD;
1718                 dw_mci_start_request(host, slot);
1719         } else {
1720                 dev_vdbg(host->dev, "list empty\n");
1721
1722                 if (host->state == STATE_SENDING_CMD11)
1723                         host->state = STATE_WAITING_CMD11_DONE;
1724                 else
1725                         host->state = STATE_IDLE;
1726         }
1727
1728         spin_unlock(&host->lock);
1729         mmc_request_done(prev_mmc, mrq);
1730         spin_lock(&host->lock);
1731 }
1732
1733 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1734 {
1735         u32 status = host->cmd_status;
1736
1737         host->cmd_status = 0;
1738
1739         /* Read the response from the card (up to 16 bytes) */
1740         if (cmd->flags & MMC_RSP_PRESENT) {
1741                 if (cmd->flags & MMC_RSP_136) {
1742                         cmd->resp[3] = mci_readl(host, RESP0);
1743                         cmd->resp[2] = mci_readl(host, RESP1);
1744                         cmd->resp[1] = mci_readl(host, RESP2);
1745                         cmd->resp[0] = mci_readl(host, RESP3);
1746                 } else {
1747                         cmd->resp[0] = mci_readl(host, RESP0);
1748                         cmd->resp[1] = 0;
1749                         cmd->resp[2] = 0;
1750                         cmd->resp[3] = 0;
1751                 }
1752         }
1753
1754         if (status & SDMMC_INT_RTO)
1755                 cmd->error = -ETIMEDOUT;
1756         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1757                 cmd->error = -EILSEQ;
1758         else if (status & SDMMC_INT_RESP_ERR)
1759                 cmd->error = -EIO;
1760         else
1761                 cmd->error = 0;
1762
1763         return cmd->error;
1764 }
1765
1766 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1767 {
1768         u32 status = host->data_status;
1769
1770         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1771                 if (status & SDMMC_INT_DRTO) {
1772                         data->error = -ETIMEDOUT;
1773                 } else if (status & SDMMC_INT_DCRC) {
1774                         data->error = -EILSEQ;
1775                 } else if (status & SDMMC_INT_EBE) {
1776                         if (host->dir_status ==
1777                                 DW_MCI_SEND_STATUS) {
1778                                 /*
1779                                  * No data CRC status was returned.
1780                                  * The number of bytes transferred
1781                                  * will be exaggerated in PIO mode.
1782                                  */
1783                                 data->bytes_xfered = 0;
1784                                 data->error = -ETIMEDOUT;
1785                         } else if (host->dir_status ==
1786                                         DW_MCI_RECV_STATUS) {
1787                                 data->error = -EILSEQ;
1788                         }
1789                 } else {
1790                         /* SDMMC_INT_SBE is included */
1791                         data->error = -EILSEQ;
1792                 }
1793
1794                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1795
1796                 /*
1797                  * After an error, there may be data lingering
1798                  * in the FIFO
1799                  */
1800                 dw_mci_reset(host);
1801         } else {
1802                 data->bytes_xfered = data->blocks * data->blksz;
1803                 data->error = 0;
1804         }
1805
1806         return data->error;
1807 }
1808
1809 static void dw_mci_set_drto(struct dw_mci *host)
1810 {
1811         unsigned int drto_clks;
1812         unsigned int drto_ms;
1813
1814         drto_clks = mci_readl(host, TMOUT) >> 8;
1815         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1816
1817         /* add a bit spare time */
1818         drto_ms += 10;
1819
1820         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1821 }
1822
1823 static void dw_mci_tasklet_func(unsigned long priv)
1824 {
1825         struct dw_mci *host = (struct dw_mci *)priv;
1826         struct mmc_data *data;
1827         struct mmc_command *cmd;
1828         struct mmc_request *mrq;
1829         enum dw_mci_state state;
1830         enum dw_mci_state prev_state;
1831         unsigned int err;
1832
1833         spin_lock(&host->lock);
1834
1835         state = host->state;
1836         data = host->data;
1837         mrq = host->mrq;
1838
1839         do {
1840                 prev_state = state;
1841
1842                 switch (state) {
1843                 case STATE_IDLE:
1844                 case STATE_WAITING_CMD11_DONE:
1845                         break;
1846
1847                 case STATE_SENDING_CMD11:
1848                 case STATE_SENDING_CMD:
1849                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1850                                                 &host->pending_events))
1851                                 break;
1852
1853                         cmd = host->cmd;
1854                         host->cmd = NULL;
1855                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1856                         err = dw_mci_command_complete(host, cmd);
1857                         if (cmd == mrq->sbc && !err) {
1858                                 prev_state = state = STATE_SENDING_CMD;
1859                                 __dw_mci_start_request(host, host->cur_slot,
1860                                                        mrq->cmd);
1861                                 goto unlock;
1862                         }
1863
1864                         if (cmd->data && err) {
1865                                 /*
1866                                  * During UHS tuning sequence, sending the stop
1867                                  * command after the response CRC error would
1868                                  * throw the system into a confused state
1869                                  * causing all future tuning phases to report
1870                                  * failure.
1871                                  *
1872                                  * In such case controller will move into a data
1873                                  * transfer state after a response error or
1874                                  * response CRC error. Let's let that finish
1875                                  * before trying to send a stop, so we'll go to
1876                                  * STATE_SENDING_DATA.
1877                                  *
1878                                  * Although letting the data transfer take place
1879                                  * will waste a bit of time (we already know
1880                                  * the command was bad), it can't cause any
1881                                  * errors since it's possible it would have
1882                                  * taken place anyway if this tasklet got
1883                                  * delayed. Allowing the transfer to take place
1884                                  * avoids races and keeps things simple.
1885                                  */
1886                                 if ((err != -ETIMEDOUT) &&
1887                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1888                                         state = STATE_SENDING_DATA;
1889                                         continue;
1890                                 }
1891
1892                                 dw_mci_stop_dma(host);
1893                                 send_stop_abort(host, data);
1894                                 state = STATE_SENDING_STOP;
1895                                 break;
1896                         }
1897
1898                         if (!cmd->data || err) {
1899                                 dw_mci_request_end(host, mrq);
1900                                 goto unlock;
1901                         }
1902
1903                         prev_state = state = STATE_SENDING_DATA;
1904                         /* fall through */
1905
1906                 case STATE_SENDING_DATA:
1907                         /*
1908                          * We could get a data error and never a transfer
1909                          * complete so we'd better check for it here.
1910                          *
1911                          * Note that we don't really care if we also got a
1912                          * transfer complete; stopping the DMA and sending an
1913                          * abort won't hurt.
1914                          */
1915                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1916                                                &host->pending_events)) {
1917                                 dw_mci_stop_dma(host);
1918                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1919                                                            SDMMC_INT_EBE)))
1920                                         send_stop_abort(host, data);
1921                                 state = STATE_DATA_ERROR;
1922                                 break;
1923                         }
1924
1925                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1926                                                 &host->pending_events)) {
1927                                 /*
1928                                  * If all data-related interrupts don't come
1929                                  * within the given time in reading data state.
1930                                  */
1931                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1932                                         dw_mci_set_drto(host);
1933                                 break;
1934                         }
1935
1936                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1937
1938                         /*
1939                          * Handle an EVENT_DATA_ERROR that might have shown up
1940                          * before the transfer completed.  This might not have
1941                          * been caught by the check above because the interrupt
1942                          * could have gone off between the previous check and
1943                          * the check for transfer complete.
1944                          *
1945                          * Technically this ought not be needed assuming we
1946                          * get a DATA_COMPLETE eventually (we'll notice the
1947                          * error and end the request), but it shouldn't hurt.
1948                          *
1949                          * This has the advantage of sending the stop command.
1950                          */
1951                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1952                                                &host->pending_events)) {
1953                                 dw_mci_stop_dma(host);
1954                                 if (!(host->data_status & (SDMMC_INT_DRTO |
1955                                                            SDMMC_INT_EBE)))
1956                                         send_stop_abort(host, data);
1957                                 state = STATE_DATA_ERROR;
1958                                 break;
1959                         }
1960                         prev_state = state = STATE_DATA_BUSY;
1961
1962                         /* fall through */
1963
1964                 case STATE_DATA_BUSY:
1965                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1966                                                 &host->pending_events)) {
1967                                 /*
1968                                  * If data error interrupt comes but data over
1969                                  * interrupt doesn't come within the given time.
1970                                  * in reading data state.
1971                                  */
1972                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1973                                         dw_mci_set_drto(host);
1974                                 break;
1975                         }
1976
1977                         host->data = NULL;
1978                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1979                         err = dw_mci_data_complete(host, data);
1980
1981                         if (!err) {
1982                                 if (!data->stop || mrq->sbc) {
1983                                         if (mrq->sbc && data->stop)
1984                                                 data->stop->error = 0;
1985                                         dw_mci_request_end(host, mrq);
1986                                         goto unlock;
1987                                 }
1988
1989                                 /* stop command for open-ended transfer*/
1990                                 if (data->stop)
1991                                         send_stop_abort(host, data);
1992                         } else {
1993                                 /*
1994                                  * If we don't have a command complete now we'll
1995                                  * never get one since we just reset everything;
1996                                  * better end the request.
1997                                  *
1998                                  * If we do have a command complete we'll fall
1999                                  * through to the SENDING_STOP command and
2000                                  * everything will be peachy keen.
2001                                  */
2002                                 if (!test_bit(EVENT_CMD_COMPLETE,
2003                                               &host->pending_events)) {
2004                                         host->cmd = NULL;
2005                                         dw_mci_request_end(host, mrq);
2006                                         goto unlock;
2007                                 }
2008                         }
2009
2010                         /*
2011                          * If err has non-zero,
2012                          * stop-abort command has been already issued.
2013                          */
2014                         prev_state = state = STATE_SENDING_STOP;
2015
2016                         /* fall through */
2017
2018                 case STATE_SENDING_STOP:
2019                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2020                                                 &host->pending_events))
2021                                 break;
2022
2023                         /* CMD error in data command */
2024                         if (mrq->cmd->error && mrq->data)
2025                                 dw_mci_reset(host);
2026
2027                         host->cmd = NULL;
2028                         host->data = NULL;
2029
2030                         if (!mrq->sbc && mrq->stop)
2031                                 dw_mci_command_complete(host, mrq->stop);
2032                         else
2033                                 host->cmd_status = 0;
2034
2035                         dw_mci_request_end(host, mrq);
2036                         goto unlock;
2037
2038                 case STATE_DATA_ERROR:
2039                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2040                                                 &host->pending_events))
2041                                 break;
2042
2043                         state = STATE_DATA_BUSY;
2044                         break;
2045                 }
2046         } while (state != prev_state);
2047
2048         host->state = state;
2049 unlock:
2050         spin_unlock(&host->lock);
2051
2052 }
2053
2054 /* push final bytes to part_buf, only use during push */
2055 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2056 {
2057         memcpy((void *)&host->part_buf, buf, cnt);
2058         host->part_buf_count = cnt;
2059 }
2060
2061 /* append bytes to part_buf, only use during push */
2062 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2063 {
2064         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2065         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2066         host->part_buf_count += cnt;
2067         return cnt;
2068 }
2069
2070 /* pull first bytes from part_buf, only use during pull */
2071 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2072 {
2073         cnt = min_t(int, cnt, host->part_buf_count);
2074         if (cnt) {
2075                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2076                        cnt);
2077                 host->part_buf_count -= cnt;
2078                 host->part_buf_start += cnt;
2079         }
2080         return cnt;
2081 }
2082
2083 /* pull final bytes from the part_buf, assuming it's just been filled */
2084 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2085 {
2086         memcpy(buf, &host->part_buf, cnt);
2087         host->part_buf_start = cnt;
2088         host->part_buf_count = (1 << host->data_shift) - cnt;
2089 }
2090
2091 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2092 {
2093         struct mmc_data *data = host->data;
2094         int init_cnt = cnt;
2095
2096         /* try and push anything in the part_buf */
2097         if (unlikely(host->part_buf_count)) {
2098                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2099
2100                 buf += len;
2101                 cnt -= len;
2102                 if (host->part_buf_count == 2) {
2103                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2104                         host->part_buf_count = 0;
2105                 }
2106         }
2107 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2108         if (unlikely((unsigned long)buf & 0x1)) {
2109                 while (cnt >= 2) {
2110                         u16 aligned_buf[64];
2111                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2112                         int items = len >> 1;
2113                         int i;
2114                         /* memcpy from input buffer into aligned buffer */
2115                         memcpy(aligned_buf, buf, len);
2116                         buf += len;
2117                         cnt -= len;
2118                         /* push data from aligned buffer into fifo */
2119                         for (i = 0; i < items; ++i)
2120                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2121                 }
2122         } else
2123 #endif
2124         {
2125                 u16 *pdata = buf;
2126
2127                 for (; cnt >= 2; cnt -= 2)
2128                         mci_fifo_writew(host->fifo_reg, *pdata++);
2129                 buf = pdata;
2130         }
2131         /* put anything remaining in the part_buf */
2132         if (cnt) {
2133                 dw_mci_set_part_bytes(host, buf, cnt);
2134                  /* Push data if we have reached the expected data length */
2135                 if ((data->bytes_xfered + init_cnt) ==
2136                     (data->blksz * data->blocks))
2137                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2138         }
2139 }
2140
2141 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2142 {
2143 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2144         if (unlikely((unsigned long)buf & 0x1)) {
2145                 while (cnt >= 2) {
2146                         /* pull data from fifo into aligned buffer */
2147                         u16 aligned_buf[64];
2148                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2149                         int items = len >> 1;
2150                         int i;
2151
2152                         for (i = 0; i < items; ++i)
2153                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2154                         /* memcpy from aligned buffer into output buffer */
2155                         memcpy(buf, aligned_buf, len);
2156                         buf += len;
2157                         cnt -= len;
2158                 }
2159         } else
2160 #endif
2161         {
2162                 u16 *pdata = buf;
2163
2164                 for (; cnt >= 2; cnt -= 2)
2165                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2166                 buf = pdata;
2167         }
2168         if (cnt) {
2169                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2170                 dw_mci_pull_final_bytes(host, buf, cnt);
2171         }
2172 }
2173
2174 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2175 {
2176         struct mmc_data *data = host->data;
2177         int init_cnt = cnt;
2178
2179         /* try and push anything in the part_buf */
2180         if (unlikely(host->part_buf_count)) {
2181                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2182
2183                 buf += len;
2184                 cnt -= len;
2185                 if (host->part_buf_count == 4) {
2186                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2187                         host->part_buf_count = 0;
2188                 }
2189         }
2190 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2191         if (unlikely((unsigned long)buf & 0x3)) {
2192                 while (cnt >= 4) {
2193                         u32 aligned_buf[32];
2194                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2195                         int items = len >> 2;
2196                         int i;
2197                         /* memcpy from input buffer into aligned buffer */
2198                         memcpy(aligned_buf, buf, len);
2199                         buf += len;
2200                         cnt -= len;
2201                         /* push data from aligned buffer into fifo */
2202                         for (i = 0; i < items; ++i)
2203                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2204                 }
2205         } else
2206 #endif
2207         {
2208                 u32 *pdata = buf;
2209
2210                 for (; cnt >= 4; cnt -= 4)
2211                         mci_fifo_writel(host->fifo_reg, *pdata++);
2212                 buf = pdata;
2213         }
2214         /* put anything remaining in the part_buf */
2215         if (cnt) {
2216                 dw_mci_set_part_bytes(host, buf, cnt);
2217                  /* Push data if we have reached the expected data length */
2218                 if ((data->bytes_xfered + init_cnt) ==
2219                     (data->blksz * data->blocks))
2220                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2221         }
2222 }
2223
2224 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2225 {
2226 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2227         if (unlikely((unsigned long)buf & 0x3)) {
2228                 while (cnt >= 4) {
2229                         /* pull data from fifo into aligned buffer */
2230                         u32 aligned_buf[32];
2231                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2232                         int items = len >> 2;
2233                         int i;
2234
2235                         for (i = 0; i < items; ++i)
2236                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2237                         /* memcpy from aligned buffer into output buffer */
2238                         memcpy(buf, aligned_buf, len);
2239                         buf += len;
2240                         cnt -= len;
2241                 }
2242         } else
2243 #endif
2244         {
2245                 u32 *pdata = buf;
2246
2247                 for (; cnt >= 4; cnt -= 4)
2248                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2249                 buf = pdata;
2250         }
2251         if (cnt) {
2252                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2253                 dw_mci_pull_final_bytes(host, buf, cnt);
2254         }
2255 }
2256
2257 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2258 {
2259         struct mmc_data *data = host->data;
2260         int init_cnt = cnt;
2261
2262         /* try and push anything in the part_buf */
2263         if (unlikely(host->part_buf_count)) {
2264                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2265
2266                 buf += len;
2267                 cnt -= len;
2268
2269                 if (host->part_buf_count == 8) {
2270                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2271                         host->part_buf_count = 0;
2272                 }
2273         }
2274 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2275         if (unlikely((unsigned long)buf & 0x7)) {
2276                 while (cnt >= 8) {
2277                         u64 aligned_buf[16];
2278                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2279                         int items = len >> 3;
2280                         int i;
2281                         /* memcpy from input buffer into aligned buffer */
2282                         memcpy(aligned_buf, buf, len);
2283                         buf += len;
2284                         cnt -= len;
2285                         /* push data from aligned buffer into fifo */
2286                         for (i = 0; i < items; ++i)
2287                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2288                 }
2289         } else
2290 #endif
2291         {
2292                 u64 *pdata = buf;
2293
2294                 for (; cnt >= 8; cnt -= 8)
2295                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2296                 buf = pdata;
2297         }
2298         /* put anything remaining in the part_buf */
2299         if (cnt) {
2300                 dw_mci_set_part_bytes(host, buf, cnt);
2301                 /* Push data if we have reached the expected data length */
2302                 if ((data->bytes_xfered + init_cnt) ==
2303                     (data->blksz * data->blocks))
2304                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2305         }
2306 }
2307
2308 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2309 {
2310 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2311         if (unlikely((unsigned long)buf & 0x7)) {
2312                 while (cnt >= 8) {
2313                         /* pull data from fifo into aligned buffer */
2314                         u64 aligned_buf[16];
2315                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2316                         int items = len >> 3;
2317                         int i;
2318
2319                         for (i = 0; i < items; ++i)
2320                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2321
2322                         /* memcpy from aligned buffer into output buffer */
2323                         memcpy(buf, aligned_buf, len);
2324                         buf += len;
2325                         cnt -= len;
2326                 }
2327         } else
2328 #endif
2329         {
2330                 u64 *pdata = buf;
2331
2332                 for (; cnt >= 8; cnt -= 8)
2333                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2334                 buf = pdata;
2335         }
2336         if (cnt) {
2337                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2338                 dw_mci_pull_final_bytes(host, buf, cnt);
2339         }
2340 }
2341
2342 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2343 {
2344         int len;
2345
2346         /* get remaining partial bytes */
2347         len = dw_mci_pull_part_bytes(host, buf, cnt);
2348         if (unlikely(len == cnt))
2349                 return;
2350         buf += len;
2351         cnt -= len;
2352
2353         /* get the rest of the data */
2354         host->pull_data(host, buf, cnt);
2355 }
2356
2357 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2358 {
2359         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2360         void *buf;
2361         unsigned int offset;
2362         struct mmc_data *data = host->data;
2363         int shift = host->data_shift;
2364         u32 status;
2365         unsigned int len;
2366         unsigned int remain, fcnt;
2367
2368         do {
2369                 if (!sg_miter_next(sg_miter))
2370                         goto done;
2371
2372                 host->sg = sg_miter->piter.sg;
2373                 buf = sg_miter->addr;
2374                 remain = sg_miter->length;
2375                 offset = 0;
2376
2377                 do {
2378                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2379                                         << shift) + host->part_buf_count;
2380                         len = min(remain, fcnt);
2381                         if (!len)
2382                                 break;
2383                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2384                         data->bytes_xfered += len;
2385                         offset += len;
2386                         remain -= len;
2387                 } while (remain);
2388
2389                 sg_miter->consumed = offset;
2390                 status = mci_readl(host, MINTSTS);
2391                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2392         /* if the RXDR is ready read again */
2393         } while ((status & SDMMC_INT_RXDR) ||
2394                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2395
2396         if (!remain) {
2397                 if (!sg_miter_next(sg_miter))
2398                         goto done;
2399                 sg_miter->consumed = 0;
2400         }
2401         sg_miter_stop(sg_miter);
2402         return;
2403
2404 done:
2405         sg_miter_stop(sg_miter);
2406         host->sg = NULL;
2407         smp_wmb(); /* drain writebuffer */
2408         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2409 }
2410
2411 static void dw_mci_write_data_pio(struct dw_mci *host)
2412 {
2413         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2414         void *buf;
2415         unsigned int offset;
2416         struct mmc_data *data = host->data;
2417         int shift = host->data_shift;
2418         u32 status;
2419         unsigned int len;
2420         unsigned int fifo_depth = host->fifo_depth;
2421         unsigned int remain, fcnt;
2422
2423         do {
2424                 if (!sg_miter_next(sg_miter))
2425                         goto done;
2426
2427                 host->sg = sg_miter->piter.sg;
2428                 buf = sg_miter->addr;
2429                 remain = sg_miter->length;
2430                 offset = 0;
2431
2432                 do {
2433                         fcnt = ((fifo_depth -
2434                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2435                                         << shift) - host->part_buf_count;
2436                         len = min(remain, fcnt);
2437                         if (!len)
2438                                 break;
2439                         host->push_data(host, (void *)(buf + offset), len);
2440                         data->bytes_xfered += len;
2441                         offset += len;
2442                         remain -= len;
2443                 } while (remain);
2444
2445                 sg_miter->consumed = offset;
2446                 status = mci_readl(host, MINTSTS);
2447                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2448         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2449
2450         if (!remain) {
2451                 if (!sg_miter_next(sg_miter))
2452                         goto done;
2453                 sg_miter->consumed = 0;
2454         }
2455         sg_miter_stop(sg_miter);
2456         return;
2457
2458 done:
2459         sg_miter_stop(sg_miter);
2460         host->sg = NULL;
2461         smp_wmb(); /* drain writebuffer */
2462         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2463 }
2464
2465 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2466 {
2467         if (!host->cmd_status)
2468                 host->cmd_status = status;
2469
2470         smp_wmb(); /* drain writebuffer */
2471
2472         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2473         tasklet_schedule(&host->tasklet);
2474 }
2475
2476 static void dw_mci_handle_cd(struct dw_mci *host)
2477 {
2478         int i;
2479
2480         for (i = 0; i < host->num_slots; i++) {
2481                 struct dw_mci_slot *slot = host->slot[i];
2482
2483                 if (!slot)
2484                         continue;
2485
2486                 if (slot->mmc->ops->card_event)
2487                         slot->mmc->ops->card_event(slot->mmc);
2488                 mmc_detect_change(slot->mmc,
2489                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2490         }
2491 }
2492
2493 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2494 {
2495         struct dw_mci *host = dev_id;
2496         u32 pending;
2497         int i;
2498
2499         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2500
2501         if (pending) {
2502                 /* Check volt switch first, since it can look like an error */
2503                 if ((host->state == STATE_SENDING_CMD11) &&
2504                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2505                         unsigned long irqflags;
2506
2507                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2508                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2509
2510                         /*
2511                          * Hold the lock; we know cmd11_timer can't be kicked
2512                          * off after the lock is released, so safe to delete.
2513                          */
2514                         spin_lock_irqsave(&host->irq_lock, irqflags);
2515                         dw_mci_cmd_interrupt(host, pending);
2516                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2517
2518                         del_timer(&host->cmd11_timer);
2519                 }
2520
2521                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2522                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2523                         host->cmd_status = pending;
2524                         smp_wmb(); /* drain writebuffer */
2525                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2526                 }
2527
2528                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2529                         /* if there is an error report DATA_ERROR */
2530                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2531                         host->data_status = pending;
2532                         smp_wmb(); /* drain writebuffer */
2533                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2534                         tasklet_schedule(&host->tasklet);
2535                 }
2536
2537                 if (pending & SDMMC_INT_DATA_OVER) {
2538                         del_timer(&host->dto_timer);
2539
2540                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2541                         if (!host->data_status)
2542                                 host->data_status = pending;
2543                         smp_wmb(); /* drain writebuffer */
2544                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2545                                 if (host->sg != NULL)
2546                                         dw_mci_read_data_pio(host, true);
2547                         }
2548                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2549                         tasklet_schedule(&host->tasklet);
2550                 }
2551
2552                 if (pending & SDMMC_INT_RXDR) {
2553                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2554                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2555                                 dw_mci_read_data_pio(host, false);
2556                 }
2557
2558                 if (pending & SDMMC_INT_TXDR) {
2559                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2560                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2561                                 dw_mci_write_data_pio(host);
2562                 }
2563
2564                 if (pending & SDMMC_INT_CMD_DONE) {
2565                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2566                         dw_mci_cmd_interrupt(host, pending);
2567                 }
2568
2569                 if (pending & SDMMC_INT_CD) {
2570                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2571                         dw_mci_handle_cd(host);
2572                 }
2573
2574                 /* Handle SDIO Interrupts */
2575                 for (i = 0; i < host->num_slots; i++) {
2576                         struct dw_mci_slot *slot = host->slot[i];
2577
2578                         if (!slot)
2579                                 continue;
2580
2581                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2582                                 mci_writel(host, RINTSTS,
2583                                            SDMMC_INT_SDIO(slot->sdio_id));
2584                                 mmc_signal_sdio_irq(slot->mmc);
2585                         }
2586                 }
2587
2588         }
2589
2590         if (host->use_dma != TRANS_MODE_IDMAC)
2591                 return IRQ_HANDLED;
2592
2593         /* Handle IDMA interrupts */
2594         if (host->dma_64bit_address == 1) {
2595                 pending = mci_readl(host, IDSTS64);
2596                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2597                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2598                                                         SDMMC_IDMAC_INT_RI);
2599                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2600                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2601                                 host->dma_ops->complete((void *)host);
2602                 }
2603         } else {
2604                 pending = mci_readl(host, IDSTS);
2605                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2606                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2607                                                         SDMMC_IDMAC_INT_RI);
2608                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2609                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2610                                 host->dma_ops->complete((void *)host);
2611                 }
2612         }
2613
2614         return IRQ_HANDLED;
2615 }
2616
2617 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2618 {
2619         struct mmc_host *mmc;
2620         struct dw_mci_slot *slot;
2621         const struct dw_mci_drv_data *drv_data = host->drv_data;
2622         int ctrl_id, ret;
2623         u32 freq[2];
2624
2625         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2626         if (!mmc)
2627                 return -ENOMEM;
2628
2629         slot = mmc_priv(mmc);
2630         slot->id = id;
2631         slot->sdio_id = host->sdio_id0 + id;
2632         slot->mmc = mmc;
2633         slot->host = host;
2634         host->slot[id] = slot;
2635
2636         mmc->ops = &dw_mci_ops;
2637         if (of_property_read_u32_array(host->dev->of_node,
2638                                        "clock-freq-min-max", freq, 2)) {
2639                 mmc->f_min = DW_MCI_FREQ_MIN;
2640                 mmc->f_max = DW_MCI_FREQ_MAX;
2641         } else {
2642                 dev_info(host->dev,
2643                         "'clock-freq-min-max' property was deprecated.\n");
2644                 mmc->f_min = freq[0];
2645                 mmc->f_max = freq[1];
2646         }
2647
2648         /*if there are external regulators, get them*/
2649         ret = mmc_regulator_get_supply(mmc);
2650         if (ret == -EPROBE_DEFER)
2651                 goto err_host_allocated;
2652
2653         if (!mmc->ocr_avail)
2654                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2655
2656         if (host->pdata->caps)
2657                 mmc->caps = host->pdata->caps;
2658
2659         /*
2660          * Support MMC_CAP_ERASE by default.
2661          * It needs to use trim/discard/erase commands.
2662          */
2663         mmc->caps |= MMC_CAP_ERASE;
2664
2665         if (host->pdata->pm_caps)
2666                 mmc->pm_caps = host->pdata->pm_caps;
2667
2668         if (host->dev->of_node) {
2669                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2670                 if (ctrl_id < 0)
2671                         ctrl_id = 0;
2672         } else {
2673                 ctrl_id = to_platform_device(host->dev)->id;
2674         }
2675         if (drv_data && drv_data->caps)
2676                 mmc->caps |= drv_data->caps[ctrl_id];
2677
2678         if (host->pdata->caps2)
2679                 mmc->caps2 = host->pdata->caps2;
2680
2681         ret = mmc_of_parse(mmc);
2682         if (ret)
2683                 goto err_host_allocated;
2684
2685         /* Useful defaults if platform data is unset. */
2686         if (host->use_dma == TRANS_MODE_IDMAC) {
2687                 mmc->max_segs = host->ring_size;
2688                 mmc->max_blk_size = 65535;
2689                 mmc->max_seg_size = 0x1000;
2690                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2691                 mmc->max_blk_count = mmc->max_req_size / 512;
2692         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2693                 mmc->max_segs = 64;
2694                 mmc->max_blk_size = 65535;
2695                 mmc->max_blk_count = 65535;
2696                 mmc->max_req_size =
2697                                 mmc->max_blk_size * mmc->max_blk_count;
2698                 mmc->max_seg_size = mmc->max_req_size;
2699         } else {
2700                 /* TRANS_MODE_PIO */
2701                 mmc->max_segs = 64;
2702                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2703                 mmc->max_blk_count = 512;
2704                 mmc->max_req_size = mmc->max_blk_size *
2705                                     mmc->max_blk_count;
2706                 mmc->max_seg_size = mmc->max_req_size;
2707         }
2708
2709         dw_mci_get_cd(mmc);
2710
2711         ret = mmc_add_host(mmc);
2712         if (ret)
2713                 goto err_host_allocated;
2714
2715 #if defined(CONFIG_DEBUG_FS)
2716         dw_mci_init_debugfs(slot);
2717 #endif
2718
2719         return 0;
2720
2721 err_host_allocated:
2722         mmc_free_host(mmc);
2723         return ret;
2724 }
2725
2726 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2727 {
2728         /* Debugfs stuff is cleaned up by mmc core */
2729         mmc_remove_host(slot->mmc);
2730         slot->host->slot[id] = NULL;
2731         mmc_free_host(slot->mmc);
2732 }
2733
2734 static void dw_mci_init_dma(struct dw_mci *host)
2735 {
2736         int addr_config;
2737         struct device *dev = host->dev;
2738         struct device_node *np = dev->of_node;
2739
2740         /*
2741         * Check tansfer mode from HCON[17:16]
2742         * Clear the ambiguous description of dw_mmc databook:
2743         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2744         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2745         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2746         * 2b'11: Non DW DMA Interface -> pio only
2747         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2748         * simpler request/acknowledge handshake mechanism and both of them
2749         * are regarded as external dma master for dw_mmc.
2750         */
2751         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2752         if (host->use_dma == DMA_INTERFACE_IDMA) {
2753                 host->use_dma = TRANS_MODE_IDMAC;
2754         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2755                    host->use_dma == DMA_INTERFACE_GDMA) {
2756                 host->use_dma = TRANS_MODE_EDMAC;
2757         } else {
2758                 goto no_dma;
2759         }
2760
2761         /* Determine which DMA interface to use */
2762         if (host->use_dma == TRANS_MODE_IDMAC) {
2763                 /*
2764                 * Check ADDR_CONFIG bit in HCON to find
2765                 * IDMAC address bus width
2766                 */
2767                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2768
2769                 if (addr_config == 1) {
2770                         /* host supports IDMAC in 64-bit address mode */
2771                         host->dma_64bit_address = 1;
2772                         dev_info(host->dev,
2773                                  "IDMAC supports 64-bit address mode.\n");
2774                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2775                                 dma_set_coherent_mask(host->dev,
2776                                                       DMA_BIT_MASK(64));
2777                 } else {
2778                         /* host supports IDMAC in 32-bit address mode */
2779                         host->dma_64bit_address = 0;
2780                         dev_info(host->dev,
2781                                  "IDMAC supports 32-bit address mode.\n");
2782                 }
2783
2784                 /* Alloc memory for sg translation */
2785                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2786                                                    DESC_RING_BUF_SZ,
2787                                                    &host->sg_dma, GFP_KERNEL);
2788                 if (!host->sg_cpu) {
2789                         dev_err(host->dev,
2790                                 "%s: could not alloc DMA memory\n",
2791                                 __func__);
2792                         goto no_dma;
2793                 }
2794
2795                 host->dma_ops = &dw_mci_idmac_ops;
2796                 dev_info(host->dev, "Using internal DMA controller.\n");
2797         } else {
2798                 /* TRANS_MODE_EDMAC: check dma bindings again */
2799                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2800                     (!of_find_property(np, "dmas", NULL))) {
2801                         goto no_dma;
2802                 }
2803                 host->dma_ops = &dw_mci_edmac_ops;
2804                 dev_info(host->dev, "Using external DMA controller.\n");
2805         }
2806
2807         if (host->dma_ops->init && host->dma_ops->start &&
2808             host->dma_ops->stop && host->dma_ops->cleanup) {
2809                 if (host->dma_ops->init(host)) {
2810                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2811                                 __func__);
2812                         goto no_dma;
2813                 }
2814         } else {
2815                 dev_err(host->dev, "DMA initialization not found.\n");
2816                 goto no_dma;
2817         }
2818
2819         return;
2820
2821 no_dma:
2822         dev_info(host->dev, "Using PIO mode.\n");
2823         host->use_dma = TRANS_MODE_PIO;
2824 }
2825
2826 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2827 {
2828         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2829         u32 ctrl;
2830
2831         ctrl = mci_readl(host, CTRL);
2832         ctrl |= reset;
2833         mci_writel(host, CTRL, ctrl);
2834
2835         /* wait till resets clear */
2836         do {
2837                 ctrl = mci_readl(host, CTRL);
2838                 if (!(ctrl & reset))
2839                         return true;
2840         } while (time_before(jiffies, timeout));
2841
2842         dev_err(host->dev,
2843                 "Timeout resetting block (ctrl reset %#x)\n",
2844                 ctrl & reset);
2845
2846         return false;
2847 }
2848
2849 static bool dw_mci_reset(struct dw_mci *host)
2850 {
2851         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2852         bool ret = false;
2853
2854         /*
2855          * Reseting generates a block interrupt, hence setting
2856          * the scatter-gather pointer to NULL.
2857          */
2858         if (host->sg) {
2859                 sg_miter_stop(&host->sg_miter);
2860                 host->sg = NULL;
2861         }
2862
2863         if (host->use_dma)
2864                 flags |= SDMMC_CTRL_DMA_RESET;
2865
2866         if (dw_mci_ctrl_reset(host, flags)) {
2867                 /*
2868                  * In all cases we clear the RAWINTS register to clear any
2869                  * interrupts.
2870                  */
2871                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2872
2873                 /* if using dma we wait for dma_req to clear */
2874                 if (host->use_dma) {
2875                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2876                         u32 status;
2877
2878                         do {
2879                                 status = mci_readl(host, STATUS);
2880                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2881                                         break;
2882                                 cpu_relax();
2883                         } while (time_before(jiffies, timeout));
2884
2885                         if (status & SDMMC_STATUS_DMA_REQ) {
2886                                 dev_err(host->dev,
2887                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2888                                         __func__);
2889                                 goto ciu_out;
2890                         }
2891
2892                         /* when using DMA next we reset the fifo again */
2893                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2894                                 goto ciu_out;
2895                 }
2896         } else {
2897                 /* if the controller reset bit did clear, then set clock regs */
2898                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2899                         dev_err(host->dev,
2900                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2901                                 __func__);
2902                         goto ciu_out;
2903                 }
2904         }
2905
2906         if (host->use_dma == TRANS_MODE_IDMAC)
2907                 /* It is also recommended that we reset and reprogram idmac */
2908                 dw_mci_idmac_reset(host);
2909
2910         ret = true;
2911
2912 ciu_out:
2913         /* After a CTRL reset we need to have CIU set clock registers  */
2914         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2915
2916         return ret;
2917 }
2918
2919 static void dw_mci_cmd11_timer(unsigned long arg)
2920 {
2921         struct dw_mci *host = (struct dw_mci *)arg;
2922
2923         if (host->state != STATE_SENDING_CMD11) {
2924                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2925                 return;
2926         }
2927
2928         host->cmd_status = SDMMC_INT_RTO;
2929         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2930         tasklet_schedule(&host->tasklet);
2931 }
2932
2933 static void dw_mci_dto_timer(unsigned long arg)
2934 {
2935         struct dw_mci *host = (struct dw_mci *)arg;
2936
2937         switch (host->state) {
2938         case STATE_SENDING_DATA:
2939         case STATE_DATA_BUSY:
2940                 /*
2941                  * If DTO interrupt does NOT come in sending data state,
2942                  * we should notify the driver to terminate current transfer
2943                  * and report a data timeout to the core.
2944                  */
2945                 host->data_status = SDMMC_INT_DRTO;
2946                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2947                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2948                 tasklet_schedule(&host->tasklet);
2949                 break;
2950         default:
2951                 break;
2952         }
2953 }
2954
2955 #ifdef CONFIG_OF
2956 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2957 {
2958         struct dw_mci_board *pdata;
2959         struct device *dev = host->dev;
2960         struct device_node *np = dev->of_node;
2961         const struct dw_mci_drv_data *drv_data = host->drv_data;
2962         int ret;
2963         u32 clock_frequency;
2964
2965         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2966         if (!pdata)
2967                 return ERR_PTR(-ENOMEM);
2968
2969         /* find reset controller when exist */
2970         pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2971         if (IS_ERR(pdata->rstc)) {
2972                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2973                         return ERR_PTR(-EPROBE_DEFER);
2974         }
2975
2976         /* find out number of slots supported */
2977         of_property_read_u32(np, "num-slots", &pdata->num_slots);
2978
2979         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2980                 dev_info(dev,
2981                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2982
2983         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2984
2985         of_property_read_u32(np, "data-addr", &host->data_addr_override);
2986
2987         if (of_get_property(np, "fifo-watermark-aligned", NULL))
2988                 host->wm_aligned = true;
2989
2990         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2991                 pdata->bus_hz = clock_frequency;
2992
2993         if (drv_data && drv_data->parse_dt) {
2994                 ret = drv_data->parse_dt(host);
2995                 if (ret)
2996                         return ERR_PTR(ret);
2997         }
2998
2999         return pdata;
3000 }
3001
3002 #else /* CONFIG_OF */
3003 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3004 {
3005         return ERR_PTR(-EINVAL);
3006 }
3007 #endif /* CONFIG_OF */
3008
3009 static void dw_mci_enable_cd(struct dw_mci *host)
3010 {
3011         unsigned long irqflags;
3012         u32 temp;
3013         int i;
3014         struct dw_mci_slot *slot;
3015
3016         /*
3017          * No need for CD if all slots have a non-error GPIO
3018          * as well as broken card detection is found.
3019          */
3020         for (i = 0; i < host->num_slots; i++) {
3021                 slot = host->slot[i];
3022                 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3023                         return;
3024
3025                 if (mmc_gpio_get_cd(slot->mmc) < 0)
3026                         break;
3027         }
3028         if (i == host->num_slots)
3029                 return;
3030
3031         spin_lock_irqsave(&host->irq_lock, irqflags);
3032         temp = mci_readl(host, INTMASK);
3033         temp  |= SDMMC_INT_CD;
3034         mci_writel(host, INTMASK, temp);
3035         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3036 }
3037
3038 int dw_mci_probe(struct dw_mci *host)
3039 {
3040         const struct dw_mci_drv_data *drv_data = host->drv_data;
3041         int width, i, ret = 0;
3042         u32 fifo_size;
3043         int init_slots = 0;
3044
3045         if (!host->pdata) {
3046                 host->pdata = dw_mci_parse_dt(host);
3047                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3048                         return -EPROBE_DEFER;
3049                 } else if (IS_ERR(host->pdata)) {
3050                         dev_err(host->dev, "platform data not available\n");
3051                         return -EINVAL;
3052                 }
3053         }
3054
3055         host->biu_clk = devm_clk_get(host->dev, "biu");
3056         if (IS_ERR(host->biu_clk)) {
3057                 dev_dbg(host->dev, "biu clock not available\n");
3058         } else {
3059                 ret = clk_prepare_enable(host->biu_clk);
3060                 if (ret) {
3061                         dev_err(host->dev, "failed to enable biu clock\n");
3062                         return ret;
3063                 }
3064         }
3065
3066         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3067         if (IS_ERR(host->ciu_clk)) {
3068                 dev_dbg(host->dev, "ciu clock not available\n");
3069                 host->bus_hz = host->pdata->bus_hz;
3070         } else {
3071                 ret = clk_prepare_enable(host->ciu_clk);
3072                 if (ret) {
3073                         dev_err(host->dev, "failed to enable ciu clock\n");
3074                         goto err_clk_biu;
3075                 }
3076
3077                 if (host->pdata->bus_hz) {
3078                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3079                         if (ret)
3080                                 dev_warn(host->dev,
3081                                          "Unable to set bus rate to %uHz\n",
3082                                          host->pdata->bus_hz);
3083                 }
3084                 host->bus_hz = clk_get_rate(host->ciu_clk);
3085         }
3086
3087         if (!host->bus_hz) {
3088                 dev_err(host->dev,
3089                         "Platform data must supply bus speed\n");
3090                 ret = -ENODEV;
3091                 goto err_clk_ciu;
3092         }
3093
3094         if (drv_data && drv_data->init) {
3095                 ret = drv_data->init(host);
3096                 if (ret) {
3097                         dev_err(host->dev,
3098                                 "implementation specific init failed\n");
3099                         goto err_clk_ciu;
3100                 }
3101         }
3102
3103         if (!IS_ERR(host->pdata->rstc)) {
3104                 reset_control_assert(host->pdata->rstc);
3105                 usleep_range(10, 50);
3106                 reset_control_deassert(host->pdata->rstc);
3107         }
3108
3109         setup_timer(&host->cmd11_timer,
3110                     dw_mci_cmd11_timer, (unsigned long)host);
3111
3112         setup_timer(&host->dto_timer,
3113                     dw_mci_dto_timer, (unsigned long)host);
3114
3115         spin_lock_init(&host->lock);
3116         spin_lock_init(&host->irq_lock);
3117         INIT_LIST_HEAD(&host->queue);
3118
3119         /*
3120          * Get the host data width - this assumes that HCON has been set with
3121          * the correct values.
3122          */
3123         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3124         if (!i) {
3125                 host->push_data = dw_mci_push_data16;
3126                 host->pull_data = dw_mci_pull_data16;
3127                 width = 16;
3128                 host->data_shift = 1;
3129         } else if (i == 2) {
3130                 host->push_data = dw_mci_push_data64;
3131                 host->pull_data = dw_mci_pull_data64;
3132                 width = 64;
3133                 host->data_shift = 3;
3134         } else {
3135                 /* Check for a reserved value, and warn if it is */
3136                 WARN((i != 1),
3137                      "HCON reports a reserved host data width!\n"
3138                      "Defaulting to 32-bit access.\n");
3139                 host->push_data = dw_mci_push_data32;
3140                 host->pull_data = dw_mci_pull_data32;
3141                 width = 32;
3142                 host->data_shift = 2;
3143         }
3144
3145         /* Reset all blocks */
3146         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3147                 ret = -ENODEV;
3148                 goto err_clk_ciu;
3149         }
3150
3151         host->dma_ops = host->pdata->dma_ops;
3152         dw_mci_init_dma(host);
3153
3154         /* Clear the interrupts for the host controller */
3155         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3156         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3157
3158         /* Put in max timeout */
3159         mci_writel(host, TMOUT, 0xFFFFFFFF);
3160
3161         /*
3162          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3163          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3164          */
3165         if (!host->pdata->fifo_depth) {
3166                 /*
3167                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3168                  * have been overwritten by the bootloader, just like we're
3169                  * about to do, so if you know the value for your hardware, you
3170                  * should put it in the platform data.
3171                  */
3172                 fifo_size = mci_readl(host, FIFOTH);
3173                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3174         } else {
3175                 fifo_size = host->pdata->fifo_depth;
3176         }
3177         host->fifo_depth = fifo_size;
3178         host->fifoth_val =
3179                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3180         mci_writel(host, FIFOTH, host->fifoth_val);
3181
3182         /* disable clock to CIU */
3183         mci_writel(host, CLKENA, 0);
3184         mci_writel(host, CLKSRC, 0);
3185
3186         /*
3187          * In 2.40a spec, Data offset is changed.
3188          * Need to check the version-id and set data-offset for DATA register.
3189          */
3190         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3191         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3192
3193         if (host->data_addr_override)
3194                 host->fifo_reg = host->regs + host->data_addr_override;
3195         else if (host->verid < DW_MMC_240A)
3196                 host->fifo_reg = host->regs + DATA_OFFSET;
3197         else
3198                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3199
3200         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3201         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3202                                host->irq_flags, "dw-mci", host);
3203         if (ret)
3204                 goto err_dmaunmap;
3205
3206         if (host->pdata->num_slots)
3207                 host->num_slots = host->pdata->num_slots;
3208         else
3209                 host->num_slots = 1;
3210
3211         if (host->num_slots < 1 ||
3212             host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3213                 dev_err(host->dev,
3214                         "Platform data must supply correct num_slots.\n");
3215                 ret = -ENODEV;
3216                 goto err_clk_ciu;
3217         }
3218
3219         /*
3220          * Enable interrupts for command done, data over, data empty,
3221          * receive ready and error such as transmit, receive timeout, crc error
3222          */
3223         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3224                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3225                    DW_MCI_ERROR_FLAGS);
3226         /* Enable mci interrupt */
3227         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3228
3229         dev_info(host->dev,
3230                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3231                  host->irq, width, fifo_size);
3232
3233         /* We need at least one slot to succeed */
3234         for (i = 0; i < host->num_slots; i++) {
3235                 ret = dw_mci_init_slot(host, i);
3236                 if (ret)
3237                         dev_dbg(host->dev, "slot %d init failed\n", i);
3238                 else
3239                         init_slots++;
3240         }
3241
3242         if (init_slots) {
3243                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3244         } else {
3245                 dev_dbg(host->dev,
3246                         "attempted to initialize %d slots, but failed on all\n",
3247                         host->num_slots);
3248                 goto err_dmaunmap;
3249         }
3250
3251         /* Now that slots are all setup, we can enable card detect */
3252         dw_mci_enable_cd(host);
3253
3254         return 0;
3255
3256 err_dmaunmap:
3257         if (host->use_dma && host->dma_ops->exit)
3258                 host->dma_ops->exit(host);
3259
3260         if (!IS_ERR(host->pdata->rstc))
3261                 reset_control_assert(host->pdata->rstc);
3262
3263 err_clk_ciu:
3264         clk_disable_unprepare(host->ciu_clk);
3265
3266 err_clk_biu:
3267         clk_disable_unprepare(host->biu_clk);
3268
3269         return ret;
3270 }
3271 EXPORT_SYMBOL(dw_mci_probe);
3272
3273 void dw_mci_remove(struct dw_mci *host)
3274 {
3275         int i;
3276
3277         for (i = 0; i < host->num_slots; i++) {
3278                 dev_dbg(host->dev, "remove slot %d\n", i);
3279                 if (host->slot[i])
3280                         dw_mci_cleanup_slot(host->slot[i], i);
3281         }
3282
3283         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3284         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3285
3286         /* disable clock to CIU */
3287         mci_writel(host, CLKENA, 0);
3288         mci_writel(host, CLKSRC, 0);
3289
3290         if (host->use_dma && host->dma_ops->exit)
3291                 host->dma_ops->exit(host);
3292
3293         if (!IS_ERR(host->pdata->rstc))
3294                 reset_control_assert(host->pdata->rstc);
3295
3296         clk_disable_unprepare(host->ciu_clk);
3297         clk_disable_unprepare(host->biu_clk);
3298 }
3299 EXPORT_SYMBOL(dw_mci_remove);
3300
3301
3302
3303 #ifdef CONFIG_PM
3304 int dw_mci_runtime_suspend(struct device *dev)
3305 {
3306         struct dw_mci *host = dev_get_drvdata(dev);
3307
3308         if (host->use_dma && host->dma_ops->exit)
3309                 host->dma_ops->exit(host);
3310
3311         clk_disable_unprepare(host->ciu_clk);
3312
3313         if (host->cur_slot &&
3314             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3315              !mmc_card_is_removable(host->cur_slot->mmc)))
3316                 clk_disable_unprepare(host->biu_clk);
3317
3318         return 0;
3319 }
3320 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3321
3322 int dw_mci_runtime_resume(struct device *dev)
3323 {
3324         int i, ret = 0;
3325         struct dw_mci *host = dev_get_drvdata(dev);
3326
3327         if (host->cur_slot &&
3328             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3329              !mmc_card_is_removable(host->cur_slot->mmc))) {
3330                 ret = clk_prepare_enable(host->biu_clk);
3331                 if (ret)
3332                         return ret;
3333         }
3334
3335         ret = clk_prepare_enable(host->ciu_clk);
3336         if (ret)
3337                 goto err;
3338
3339         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3340                 clk_disable_unprepare(host->ciu_clk);
3341                 ret = -ENODEV;
3342                 goto err;
3343         }
3344
3345         if (host->use_dma && host->dma_ops->init)
3346                 host->dma_ops->init(host);
3347
3348         /*
3349          * Restore the initial value at FIFOTH register
3350          * And Invalidate the prev_blksz with zero
3351          */
3352          mci_writel(host, FIFOTH, host->fifoth_val);
3353          host->prev_blksz = 0;
3354
3355         /* Put in max timeout */
3356         mci_writel(host, TMOUT, 0xFFFFFFFF);
3357
3358         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3359         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3360                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3361                    DW_MCI_ERROR_FLAGS);
3362         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3363
3364         for (i = 0; i < host->num_slots; i++) {
3365                 struct dw_mci_slot *slot = host->slot[i];
3366
3367                 if (!slot)
3368                         continue;
3369                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3370                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3371
3372                 /* Force setup bus to guarantee available clock output */
3373                 dw_mci_setup_bus(slot, true);
3374         }
3375
3376         /* Now that slots are all setup, we can enable card detect */
3377         dw_mci_enable_cd(host);
3378
3379         return 0;
3380
3381 err:
3382         if (host->cur_slot &&
3383             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3384              !mmc_card_is_removable(host->cur_slot->mmc)))
3385                 clk_disable_unprepare(host->biu_clk);
3386
3387         return ret;
3388 }
3389 EXPORT_SYMBOL(dw_mci_runtime_resume);
3390 #endif /* CONFIG_PM */
3391
3392 static int __init dw_mci_init(void)
3393 {
3394         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3395         return 0;
3396 }
3397
3398 static void __exit dw_mci_exit(void)
3399 {
3400 }
3401
3402 module_init(dw_mci_init);
3403 module_exit(dw_mci_exit);
3404
3405 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3406 MODULE_AUTHOR("NXP Semiconductor VietNam");
3407 MODULE_AUTHOR("Imagination Technologies Ltd");
3408 MODULE_LICENSE("GPL v2");