2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
17 #include <linux/scatterlist.h>
18 #include <linux/mmc/core.h>
19 #include <linux/dmaengine.h>
20 #include <linux/reset.h>
21 #include <linux/interrupt.h>
23 #define MAX_MCI_SLOTS 2
33 STATE_WAITING_CMD11_DONE,
37 EVENT_CMD_COMPLETE = 0,
45 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
46 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
57 struct dw_mci_dma_slave {
59 enum dma_transfer_direction direction;
63 * struct dw_mci - MMC controller state shared between all slots
64 * @lock: Spinlock protecting the queue and associated data.
65 * @irq_lock: Spinlock protecting the INTMASK setting.
66 * @regs: Pointer to MMIO registers.
67 * @fifo_reg: Pointer to MMIO registers for data FIFO
68 * @sg: Scatterlist entry currently being processed by PIO code, if any.
69 * @sg_miter: PIO mapping scatterlist iterator.
70 * @cur_slot: The slot which is currently using the controller.
71 * @mrq: The request currently being processed on @cur_slot,
72 * or NULL if the controller is idle.
73 * @cmd: The command currently being sent to the card, or NULL.
74 * @data: The data currently being transferred, or NULL if no data
75 * transfer is in progress.
76 * @stop_abort: The command currently prepared for stoping transfer.
77 * @prev_blksz: The former transfer blksz record.
78 * @timing: Record of current ios timing.
79 * @use_dma: Whether DMA channel is initialized or not.
80 * @using_dma: Whether DMA is in use for the current transfer.
81 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
82 * @sg_dma: Bus address of DMA buffer.
83 * @sg_cpu: Virtual address of DMA buffer.
84 * @dma_ops: Pointer to platform-specific DMA callbacks.
85 * @cmd_status: Snapshot of SR taken upon completion of the current
86 * @ring_size: Buffer size for idma descriptors.
87 * command. Only valid when EVENT_CMD_COMPLETE is pending.
88 * @dms: structure of slave-dma private data.
89 * @phy_regs: physical address of controller's register map
90 * @data_status: Snapshot of SR taken upon completion of the current
91 * data transfer. Only valid when EVENT_DATA_COMPLETE or
92 * EVENT_DATA_ERROR is pending.
93 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
95 * @dir_status: Direction of current transfer.
96 * @tasklet: Tasklet running the request state machine.
97 * @pending_events: Bitmask of events flagged by the interrupt handler
98 * to be processed by the tasklet.
99 * @completed_events: Bitmask of events which the state machine has
101 * @state: Tasklet state.
102 * @queue: List of slots waiting for access to the controller.
103 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
104 * rate and timeout calculations.
105 * @current_speed: Configured rate of the controller.
106 * @num_slots: Number of slots available.
107 * @fifoth_val: The value of FIFOTH register.
108 * @verid: Denote Version ID.
109 * @dev: Device associated with the MMC controller.
110 * @pdata: Platform data associated with the MMC controller.
111 * @drv_data: Driver specific data for identified variant of the controller
112 * @priv: Implementation defined private data.
113 * @biu_clk: Pointer to bus interface unit clock instance.
114 * @ciu_clk: Pointer to card interface unit clock instance.
115 * @slot: Slots sharing this MMC controller.
116 * @fifo_depth: depth of FIFO.
117 * @data_addr_override: override fifo reg offset with this value.
118 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
119 * Set as true if alignment is needed.
120 * @data_shift: log2 of FIFO item size.
121 * @part_buf_start: Start index in part_buf.
122 * @part_buf_count: Bytes of partial data in part_buf.
123 * @part_buf: Simple buffer for partial fifo reads/writes.
124 * @push_data: Pointer to FIFO push function.
125 * @pull_data: Pointer to FIFO pull function.
126 * @vqmmc_enabled: Status of vqmmc, should be true or false.
127 * @irq_flags: The flags to be passed to request_irq.
128 * @irq: The irq value to be passed to request_irq.
129 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
130 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
131 * @dto_timer: Timer for broken data transfer over scheme.
136 * @lock is a softirq-safe spinlock protecting @queue as well as
137 * @cur_slot, @mrq and @state. These must always be updated
138 * at the same time while holding @lock.
140 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
141 * to allow the interrupt handler to modify it directly. Held for only long
142 * enough to read-modify-write INTMASK and no other locks are grabbed when
145 * The @mrq field of struct dw_mci_slot is also protected by @lock,
146 * and must always be written at the same time as the slot is added to
149 * @pending_events and @completed_events are accessed using atomic bit
150 * operations, so they don't need any locking.
152 * None of the fields touched by the interrupt handler need any
153 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
154 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
155 * interrupts must be disabled and @data_status updated with a
156 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
157 * CMDRDY interrupt must be disabled and @cmd_status updated with a
158 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
159 * bytes_xfered field of @data must be written. This is ensured by
166 void __iomem *fifo_reg;
167 u32 data_addr_override;
170 struct scatterlist *sg;
171 struct sg_mapping_iter sg_miter;
173 struct dw_mci_slot *cur_slot;
174 struct mmc_request *mrq;
175 struct mmc_command *cmd;
176 struct mmc_data *data;
177 struct mmc_command stop_abort;
178 unsigned int prev_blksz;
179 unsigned char timing;
181 /* DMA interface members*/
184 int dma_64bit_address;
188 const struct dw_mci_dma_ops *dma_ops;
190 unsigned int ring_size;
193 struct dw_mci_dma_slave *dms;
194 /* Registers's physical base address */
195 resource_size_t phy_regs;
201 struct tasklet_struct tasklet;
202 unsigned long pending_events;
203 unsigned long completed_events;
204 enum dw_mci_state state;
205 struct list_head queue;
213 struct dw_mci_board *pdata;
214 const struct dw_mci_drv_data *drv_data;
218 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
220 /* FIFO push and pull */
230 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
231 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
234 unsigned long irq_flags; /* IRQ flags */
239 struct timer_list cmd11_timer;
240 struct timer_list dto_timer;
243 /* DMA ops for Internal/External DMAC interface */
244 struct dw_mci_dma_ops {
246 int (*init)(struct dw_mci *host);
247 int (*start)(struct dw_mci *host, unsigned int sg_len);
248 void (*complete)(void *host);
249 void (*stop)(struct dw_mci *host);
250 void (*cleanup)(struct dw_mci *host);
251 void (*exit)(struct dw_mci *host);
256 /* Board platform data */
257 struct dw_mci_board {
260 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
262 u32 caps; /* Capabilities */
263 u32 caps2; /* More capabilities */
264 u32 pm_caps; /* PM capabilities */
266 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
267 * but note that this may not be reliable after a bootloader has used
270 unsigned int fifo_depth;
272 /* delay in mS before detecting cards after interrupt */
275 struct reset_control *rstc;
276 struct dw_mci_dma_ops *dma_ops;
277 struct dma_pdata *data;
280 #define DW_MMC_240A 0x240a
281 #define DW_MMC_280A 0x280a
283 #define SDMMC_CTRL 0x000
284 #define SDMMC_PWREN 0x004
285 #define SDMMC_CLKDIV 0x008
286 #define SDMMC_CLKSRC 0x00c
287 #define SDMMC_CLKENA 0x010
288 #define SDMMC_TMOUT 0x014
289 #define SDMMC_CTYPE 0x018
290 #define SDMMC_BLKSIZ 0x01c
291 #define SDMMC_BYTCNT 0x020
292 #define SDMMC_INTMASK 0x024
293 #define SDMMC_CMDARG 0x028
294 #define SDMMC_CMD 0x02c
295 #define SDMMC_RESP0 0x030
296 #define SDMMC_RESP1 0x034
297 #define SDMMC_RESP2 0x038
298 #define SDMMC_RESP3 0x03c
299 #define SDMMC_MINTSTS 0x040
300 #define SDMMC_RINTSTS 0x044
301 #define SDMMC_STATUS 0x048
302 #define SDMMC_FIFOTH 0x04c
303 #define SDMMC_CDETECT 0x050
304 #define SDMMC_WRTPRT 0x054
305 #define SDMMC_GPIO 0x058
306 #define SDMMC_TCBCNT 0x05c
307 #define SDMMC_TBBCNT 0x060
308 #define SDMMC_DEBNCE 0x064
309 #define SDMMC_USRID 0x068
310 #define SDMMC_VERID 0x06c
311 #define SDMMC_HCON 0x070
312 #define SDMMC_UHS_REG 0x074
313 #define SDMMC_RST_N 0x078
314 #define SDMMC_BMOD 0x080
315 #define SDMMC_PLDMND 0x084
316 #define SDMMC_DBADDR 0x088
317 #define SDMMC_IDSTS 0x08c
318 #define SDMMC_IDINTEN 0x090
319 #define SDMMC_DSCADDR 0x094
320 #define SDMMC_BUFADDR 0x098
321 #define SDMMC_CDTHRCTL 0x100
322 #define SDMMC_DATA(x) (x)
324 * Registers to support idmac 64-bit address mode
326 #define SDMMC_DBADDRL 0x088
327 #define SDMMC_DBADDRU 0x08c
328 #define SDMMC_IDSTS64 0x090
329 #define SDMMC_IDINTEN64 0x094
330 #define SDMMC_DSCADDRL 0x098
331 #define SDMMC_DSCADDRU 0x09c
332 #define SDMMC_BUFADDRL 0x0A0
333 #define SDMMC_BUFADDRU 0x0A4
336 * Data offset is difference according to Version
337 * Lower than 2.40a : data register offest is 0x100
339 #define DATA_OFFSET 0x100
340 #define DATA_240A_OFFSET 0x200
342 /* shift bit field */
343 #define _SBF(f, v) ((v) << (f))
345 /* Control register defines */
346 #define SDMMC_CTRL_USE_IDMAC BIT(25)
347 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
348 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
349 #define SDMMC_CTRL_SEND_CCSD BIT(9)
350 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
351 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
352 #define SDMMC_CTRL_READ_WAIT BIT(6)
353 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
354 #define SDMMC_CTRL_INT_ENABLE BIT(4)
355 #define SDMMC_CTRL_DMA_RESET BIT(2)
356 #define SDMMC_CTRL_FIFO_RESET BIT(1)
357 #define SDMMC_CTRL_RESET BIT(0)
358 /* Clock Enable register defines */
359 #define SDMMC_CLKEN_LOW_PWR BIT(16)
360 #define SDMMC_CLKEN_ENABLE BIT(0)
361 /* time-out register defines */
362 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
363 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
364 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
365 #define SDMMC_TMOUT_RESP_MSK 0xFF
366 /* card-type register defines */
367 #define SDMMC_CTYPE_8BIT BIT(16)
368 #define SDMMC_CTYPE_4BIT BIT(0)
369 #define SDMMC_CTYPE_1BIT 0
370 /* Interrupt status & mask register defines */
371 #define SDMMC_INT_SDIO(n) BIT(16 + (n))
372 #define SDMMC_INT_EBE BIT(15)
373 #define SDMMC_INT_ACD BIT(14)
374 #define SDMMC_INT_SBE BIT(13)
375 #define SDMMC_INT_HLE BIT(12)
376 #define SDMMC_INT_FRUN BIT(11)
377 #define SDMMC_INT_HTO BIT(10)
378 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
379 #define SDMMC_INT_DRTO BIT(9)
380 #define SDMMC_INT_RTO BIT(8)
381 #define SDMMC_INT_DCRC BIT(7)
382 #define SDMMC_INT_RCRC BIT(6)
383 #define SDMMC_INT_RXDR BIT(5)
384 #define SDMMC_INT_TXDR BIT(4)
385 #define SDMMC_INT_DATA_OVER BIT(3)
386 #define SDMMC_INT_CMD_DONE BIT(2)
387 #define SDMMC_INT_RESP_ERR BIT(1)
388 #define SDMMC_INT_CD BIT(0)
389 #define SDMMC_INT_ERROR 0xbfc2
390 /* Command register defines */
391 #define SDMMC_CMD_START BIT(31)
392 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
393 #define SDMMC_CMD_VOLT_SWITCH BIT(28)
394 #define SDMMC_CMD_CCS_EXP BIT(23)
395 #define SDMMC_CMD_CEATA_RD BIT(22)
396 #define SDMMC_CMD_UPD_CLK BIT(21)
397 #define SDMMC_CMD_INIT BIT(15)
398 #define SDMMC_CMD_STOP BIT(14)
399 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
400 #define SDMMC_CMD_SEND_STOP BIT(12)
401 #define SDMMC_CMD_STRM_MODE BIT(11)
402 #define SDMMC_CMD_DAT_WR BIT(10)
403 #define SDMMC_CMD_DAT_EXP BIT(9)
404 #define SDMMC_CMD_RESP_CRC BIT(8)
405 #define SDMMC_CMD_RESP_LONG BIT(7)
406 #define SDMMC_CMD_RESP_EXP BIT(6)
407 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
408 /* Status register defines */
409 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
410 #define SDMMC_STATUS_DMA_REQ BIT(31)
411 #define SDMMC_STATUS_BUSY BIT(9)
412 /* FIFOTH register defines */
413 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
414 ((r) & 0xFFF) << 16 | \
416 /* HCON register defines */
417 #define DMA_INTERFACE_IDMA (0x0)
418 #define DMA_INTERFACE_DWDMA (0x1)
419 #define DMA_INTERFACE_GDMA (0x2)
420 #define DMA_INTERFACE_NODMA (0x3)
421 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
422 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
423 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
424 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
425 /* Internal DMAC interrupt defines */
426 #define SDMMC_IDMAC_INT_AI BIT(9)
427 #define SDMMC_IDMAC_INT_NI BIT(8)
428 #define SDMMC_IDMAC_INT_CES BIT(5)
429 #define SDMMC_IDMAC_INT_DU BIT(4)
430 #define SDMMC_IDMAC_INT_FBE BIT(2)
431 #define SDMMC_IDMAC_INT_RI BIT(1)
432 #define SDMMC_IDMAC_INT_TI BIT(0)
433 /* Internal DMAC bus mode bits */
434 #define SDMMC_IDMAC_ENABLE BIT(7)
435 #define SDMMC_IDMAC_FB BIT(1)
436 #define SDMMC_IDMAC_SWRESET BIT(0)
438 #define SDMMC_RST_HWACTIVE 0x1
439 /* Version ID register define */
440 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
441 /* Card read threshold */
442 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
443 #define SDMMC_CARD_WR_THR_EN BIT(2)
444 #define SDMMC_CARD_RD_THR_EN BIT(0)
445 /* UHS-1 register defines */
446 #define SDMMC_UHS_18V BIT(0)
447 /* All ctrl reset bits */
448 #define SDMMC_CTRL_ALL_RESET_FLAGS \
449 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
451 /* FIFO register access macros. These should not change the data endian-ness
452 * as they are written to memory to be dealt with by the upper layers */
453 #define mci_fifo_readw(__reg) __raw_readw(__reg)
454 #define mci_fifo_readl(__reg) __raw_readl(__reg)
455 #define mci_fifo_readq(__reg) __raw_readq(__reg)
457 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
458 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
459 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
461 /* Register access macros */
462 #define mci_readl(dev, reg) \
463 readl_relaxed((dev)->regs + SDMMC_##reg)
464 #define mci_writel(dev, reg, value) \
465 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
467 /* 16-bit FIFO access macros */
468 #define mci_readw(dev, reg) \
469 readw_relaxed((dev)->regs + SDMMC_##reg)
470 #define mci_writew(dev, reg, value) \
471 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
473 /* 64-bit FIFO access macros */
475 #define mci_readq(dev, reg) \
476 readq_relaxed((dev)->regs + SDMMC_##reg)
477 #define mci_writeq(dev, reg, value) \
478 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
481 * Dummy readq implementation for architectures that don't define it.
483 * We would assume that none of these architectures would configure
484 * the IP block with a 64bit FIFO width, so this code will never be
485 * executed on those machines. Defining these macros here keeps the
486 * rest of the code free from ifdefs.
488 #define mci_readq(dev, reg) \
489 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
490 #define mci_writeq(dev, reg, value) \
491 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
493 #define __raw_writeq(__value, __reg) \
494 (*(volatile u64 __force *)(__reg) = (__value))
495 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
498 extern int dw_mci_probe(struct dw_mci *host);
499 extern void dw_mci_remove(struct dw_mci *host);
501 extern int dw_mci_runtime_suspend(struct device *device);
502 extern int dw_mci_runtime_resume(struct device *device);
506 * struct dw_mci_slot - MMC slot state
507 * @mmc: The mmc_host representing this slot.
508 * @host: The MMC controller this slot is using.
509 * @ctype: Card type for this slot.
510 * @mrq: mmc_request currently being processed or waiting to be
511 * processed, or NULL when the slot is idle.
512 * @queue_node: List node for placing this node in the @queue list of
514 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
515 * @__clk_old: The last clock value that was requested from core.
516 * Keeping track of this helps us to avoid spamming the console.
517 * @flags: Random state bits associated with the slot.
518 * @id: Number of this slot.
519 * @sdio_id: Number of this slot in the SDIO interrupt registers.
522 struct mmc_host *mmc;
527 struct mmc_request *mrq;
528 struct list_head queue_node;
531 unsigned int __clk_old;
534 #define DW_MMC_CARD_PRESENT 0
535 #define DW_MMC_CARD_NEED_INIT 1
536 #define DW_MMC_CARD_NO_LOW_PWR 2
537 #define DW_MMC_CARD_NO_USE_HOLD 3
538 #define DW_MMC_CARD_NEEDS_POLL 4
544 * dw_mci driver data - dw-mshc implementation specific driver data.
545 * @caps: mmc subsystem specified capabilities of the controller(s).
546 * @init: early implementation specific initialization.
547 * @set_ios: handle bus specific extensions.
548 * @parse_dt: parse implementation specific device tree properties.
549 * @execute_tuning: implementation specific tuning procedure.
551 * Provide controller implementation specific extensions. The usage of this
552 * data structure is fully optional and usage of each member in this structure
553 * is optional as well.
555 struct dw_mci_drv_data {
557 int (*init)(struct dw_mci *host);
558 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
559 int (*parse_dt)(struct dw_mci *host);
560 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
561 int (*prepare_hs400_tuning)(struct dw_mci *host,
562 struct mmc_ios *ios);
563 int (*switch_voltage)(struct mmc_host *mmc,
564 struct mmc_ios *ios);
566 #endif /* _DW_MMC_H_ */