2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/host.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
24 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/amba/mmci.h>
27 #include <linux/regulator/consumer.h>
29 #include <asm/div64.h>
31 #include <asm/sizes.h>
35 #define DRIVER_NAME "mmci-pl18x"
37 static unsigned int fmax = 515633;
40 * struct variant_data - MMCI variant-specific quirks
41 * @clkreg: default value for MCICLOCK register
42 * @clkreg_enable: enable value for MMCICLOCK register
46 unsigned int clkreg_enable;
49 static struct variant_data variant_arm = {
52 static struct variant_data variant_u300 = {
53 .clkreg_enable = 1 << 13, /* HWFCEN */
56 static struct variant_data variant_ux500 = {
57 .clkreg = MCI_CLK_ENABLE,
58 .clkreg_enable = 1 << 14, /* HWFCEN */
61 * This must be called with host->lock held
63 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
65 struct variant_data *variant = host->variant;
66 u32 clk = variant->clkreg;
69 if (desired >= host->mclk) {
71 host->cclk = host->mclk;
73 clk = host->mclk / (2 * desired) - 1;
76 host->cclk = host->mclk / (2 * (clk + 1));
79 clk |= variant->clkreg_enable;
80 clk |= MCI_CLK_ENABLE;
81 /* This hasn't proven to be worthwhile */
82 /* clk |= MCI_CLK_PWRSAVE; */
85 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
87 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
88 clk |= MCI_ST_8BIT_BUS;
90 writel(clk, host->base + MMCICLOCK);
94 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
96 writel(0, host->base + MMCICOMMAND);
104 mrq->data->bytes_xfered = host->data_xfered;
107 * Need to drop the host lock here; mmc_request_done may call
108 * back into the driver...
110 spin_unlock(&host->lock);
111 mmc_request_done(host->mmc, mrq);
112 spin_lock(&host->lock);
115 static void mmci_stop_data(struct mmci_host *host)
117 writel(0, host->base + MMCIDATACTRL);
118 writel(0, host->base + MMCIMASK1);
122 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
124 unsigned int flags = SG_MITER_ATOMIC;
126 if (data->flags & MMC_DATA_READ)
127 flags |= SG_MITER_TO_SG;
129 flags |= SG_MITER_FROM_SG;
131 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
134 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
136 unsigned int datactrl, timeout, irqmask;
137 unsigned long long clks;
141 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
142 data->blksz, data->blocks, data->flags);
145 host->size = data->blksz * data->blocks;
146 host->data_xfered = 0;
148 mmci_init_sg(host, data);
150 clks = (unsigned long long)data->timeout_ns * host->cclk;
151 do_div(clks, 1000000000UL);
153 timeout = data->timeout_clks + (unsigned int)clks;
156 writel(timeout, base + MMCIDATATIMER);
157 writel(host->size, base + MMCIDATALENGTH);
159 blksz_bits = ffs(data->blksz) - 1;
160 BUG_ON(1 << blksz_bits != data->blksz);
162 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
163 if (data->flags & MMC_DATA_READ) {
164 datactrl |= MCI_DPSM_DIRECTION;
165 irqmask = MCI_RXFIFOHALFFULLMASK;
168 * If we have less than a FIFOSIZE of bytes to transfer,
169 * trigger a PIO interrupt as soon as any data is available.
171 if (host->size < MCI_FIFOSIZE)
172 irqmask |= MCI_RXDATAAVLBLMASK;
175 * We don't actually need to include "FIFO empty" here
176 * since its implicit in "FIFO half empty".
178 irqmask = MCI_TXFIFOHALFEMPTYMASK;
181 writel(datactrl, base + MMCIDATACTRL);
182 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
183 writel(irqmask, base + MMCIMASK1);
187 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
189 void __iomem *base = host->base;
191 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
192 cmd->opcode, cmd->arg, cmd->flags);
194 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
195 writel(0, base + MMCICOMMAND);
199 c |= cmd->opcode | MCI_CPSM_ENABLE;
200 if (cmd->flags & MMC_RSP_PRESENT) {
201 if (cmd->flags & MMC_RSP_136)
202 c |= MCI_CPSM_LONGRSP;
203 c |= MCI_CPSM_RESPONSE;
206 c |= MCI_CPSM_INTERRUPT;
210 writel(cmd->arg, base + MMCIARGUMENT);
211 writel(c, base + MMCICOMMAND);
215 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
218 if (status & MCI_DATABLOCKEND) {
219 host->data_xfered += data->blksz;
220 #ifdef CONFIG_ARCH_U300
222 * On the U300 some signal or other is
223 * badly routed so that a data write does
224 * not properly terminate with a MCI_DATAEND
225 * status flag. This quirk will make writes
228 if (data->flags & MMC_DATA_WRITE)
229 status |= MCI_DATAEND;
232 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
233 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
234 if (status & MCI_DATACRCFAIL)
235 data->error = -EILSEQ;
236 else if (status & MCI_DATATIMEOUT)
237 data->error = -ETIMEDOUT;
238 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
240 status |= MCI_DATAEND;
243 * We hit an error condition. Ensure that any data
244 * partially written to a page is properly coherent.
246 if (data->flags & MMC_DATA_READ) {
247 struct sg_mapping_iter *sg_miter = &host->sg_miter;
250 local_irq_save(flags);
251 if (sg_miter_next(sg_miter)) {
252 flush_dcache_page(sg_miter->page);
253 sg_miter_stop(sg_miter);
255 local_irq_restore(flags);
258 if (status & MCI_DATAEND) {
259 mmci_stop_data(host);
262 mmci_request_end(host, data->mrq);
264 mmci_start_command(host, data->stop, 0);
270 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
273 void __iomem *base = host->base;
277 cmd->resp[0] = readl(base + MMCIRESPONSE0);
278 cmd->resp[1] = readl(base + MMCIRESPONSE1);
279 cmd->resp[2] = readl(base + MMCIRESPONSE2);
280 cmd->resp[3] = readl(base + MMCIRESPONSE3);
282 if (status & MCI_CMDTIMEOUT) {
283 cmd->error = -ETIMEDOUT;
284 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
285 cmd->error = -EILSEQ;
288 if (!cmd->data || cmd->error) {
290 mmci_stop_data(host);
291 mmci_request_end(host, cmd->mrq);
292 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
293 mmci_start_data(host, cmd->data);
297 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
299 void __iomem *base = host->base;
302 int host_remain = host->size;
305 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
313 readsl(base + MMCIFIFO, ptr, count >> 2);
317 host_remain -= count;
322 status = readl(base + MMCISTATUS);
323 } while (status & MCI_RXDATAAVLBL);
328 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
330 void __iomem *base = host->base;
334 unsigned int count, maxcnt;
336 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
337 count = min(remain, maxcnt);
339 writesl(base + MMCIFIFO, ptr, count >> 2);
347 status = readl(base + MMCISTATUS);
348 } while (status & MCI_TXFIFOHALFEMPTY);
354 * PIO data transfer IRQ handler.
356 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
358 struct mmci_host *host = dev_id;
359 struct sg_mapping_iter *sg_miter = &host->sg_miter;
360 void __iomem *base = host->base;
364 status = readl(base + MMCISTATUS);
366 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
368 local_irq_save(flags);
371 unsigned int remain, len;
375 * For write, we only need to test the half-empty flag
376 * here - if the FIFO is completely empty, then by
377 * definition it is more than half empty.
379 * For read, check for data available.
381 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
384 if (!sg_miter_next(sg_miter))
387 buffer = sg_miter->addr;
388 remain = sg_miter->length;
391 if (status & MCI_RXACTIVE)
392 len = mmci_pio_read(host, buffer, remain);
393 if (status & MCI_TXACTIVE)
394 len = mmci_pio_write(host, buffer, remain, status);
396 sg_miter->consumed = len;
404 if (status & MCI_RXACTIVE)
405 flush_dcache_page(sg_miter->page);
407 status = readl(base + MMCISTATUS);
410 sg_miter_stop(sg_miter);
412 local_irq_restore(flags);
415 * If we're nearing the end of the read, switch to
416 * "any data available" mode.
418 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
419 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
422 * If we run out of data, disable the data IRQs; this
423 * prevents a race where the FIFO becomes empty before
424 * the chip itself has disabled the data path, and
425 * stops us racing with our data end IRQ.
427 if (host->size == 0) {
428 writel(0, base + MMCIMASK1);
429 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
436 * Handle completion of command and data transfers.
438 static irqreturn_t mmci_irq(int irq, void *dev_id)
440 struct mmci_host *host = dev_id;
444 spin_lock(&host->lock);
447 struct mmc_command *cmd;
448 struct mmc_data *data;
450 status = readl(host->base + MMCISTATUS);
451 status &= readl(host->base + MMCIMASK0);
452 writel(status, host->base + MMCICLEAR);
454 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
457 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
458 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
459 mmci_data_irq(host, data, status);
462 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
463 mmci_cmd_irq(host, cmd, status);
468 spin_unlock(&host->lock);
470 return IRQ_RETVAL(ret);
473 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
475 struct mmci_host *host = mmc_priv(mmc);
478 WARN_ON(host->mrq != NULL);
480 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
481 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
483 mrq->cmd->error = -EINVAL;
484 mmc_request_done(mmc, mrq);
488 spin_lock_irqsave(&host->lock, flags);
492 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
493 mmci_start_data(host, mrq->data);
495 mmci_start_command(host, mrq->cmd, 0);
497 spin_unlock_irqrestore(&host->lock, flags);
500 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
502 struct mmci_host *host = mmc_priv(mmc);
506 switch (ios->power_mode) {
509 regulator_is_enabled(host->vcc))
510 regulator_disable(host->vcc);
513 #ifdef CONFIG_REGULATOR
515 /* This implicitly enables the regulator */
516 mmc_regulator_set_ocr(host->vcc, ios->vdd);
518 if (host->plat->vdd_handler)
519 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
521 /* The ST version does not have this, fall through to POWER_ON */
522 if (host->hw_designer != AMBA_VENDOR_ST) {
531 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
532 if (host->hw_designer != AMBA_VENDOR_ST)
536 * The ST Micro variant use the ROD bit for something
537 * else and only has OD (Open Drain).
543 spin_lock_irqsave(&host->lock, flags);
545 mmci_set_clkreg(host, ios->clock);
547 if (host->pwr != pwr) {
549 writel(pwr, host->base + MMCIPOWER);
552 spin_unlock_irqrestore(&host->lock, flags);
555 static int mmci_get_ro(struct mmc_host *mmc)
557 struct mmci_host *host = mmc_priv(mmc);
559 if (host->gpio_wp == -ENOSYS)
562 return gpio_get_value(host->gpio_wp);
565 static int mmci_get_cd(struct mmc_host *mmc)
567 struct mmci_host *host = mmc_priv(mmc);
570 if (host->gpio_cd == -ENOSYS)
571 status = host->plat->status(mmc_dev(host->mmc));
573 status = gpio_get_value(host->gpio_cd);
578 static const struct mmc_host_ops mmci_ops = {
579 .request = mmci_request,
580 .set_ios = mmci_set_ios,
581 .get_ro = mmci_get_ro,
582 .get_cd = mmci_get_cd,
585 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
587 struct mmci_platform_data *plat = dev->dev.platform_data;
588 struct variant_data *variant = id->data;
589 struct mmci_host *host;
590 struct mmc_host *mmc;
593 /* must have platform data */
599 ret = amba_request_regions(dev, DRIVER_NAME);
603 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
609 host = mmc_priv(mmc);
612 host->gpio_wp = -ENOSYS;
613 host->gpio_cd = -ENOSYS;
615 host->hw_designer = amba_manf(dev);
616 host->hw_revision = amba_rev(dev);
617 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
618 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
620 host->clk = clk_get(&dev->dev, NULL);
621 if (IS_ERR(host->clk)) {
622 ret = PTR_ERR(host->clk);
627 ret = clk_enable(host->clk);
632 host->variant = variant;
633 host->mclk = clk_get_rate(host->clk);
635 * According to the spec, mclk is max 100 MHz,
636 * so we try to adjust the clock down to this,
639 if (host->mclk > 100000000) {
640 ret = clk_set_rate(host->clk, 100000000);
643 host->mclk = clk_get_rate(host->clk);
644 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
647 host->base = ioremap(dev->res.start, resource_size(&dev->res));
653 mmc->ops = &mmci_ops;
654 mmc->f_min = (host->mclk + 511) / 512;
656 * If the platform data supplies a maximum operating
657 * frequency, this takes precedence. Else, we fall back
658 * to using the module parameter, which has a (low)
659 * default value in case it is not specified. Either
660 * value must not exceed the clock rate into the block,
664 mmc->f_max = min(host->mclk, plat->f_max);
666 mmc->f_max = min(host->mclk, fmax);
667 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
669 #ifdef CONFIG_REGULATOR
670 /* If we're using the regulator framework, try to fetch a regulator */
671 host->vcc = regulator_get(&dev->dev, "vmmc");
672 if (IS_ERR(host->vcc))
675 int mask = mmc_regulator_get_ocrmask(host->vcc);
678 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
681 host->mmc->ocr_avail = (u32) mask;
684 "Provided ocr_mask/setpower will not be used "
685 "(using regulator instead)\n");
689 /* Fall back to platform data if no regulator is found */
690 if (host->vcc == NULL)
691 mmc->ocr_avail = plat->ocr_mask;
692 mmc->caps = plat->capabilities;
693 mmc->caps |= MMC_CAP_NEEDS_POLL;
698 mmc->max_hw_segs = 16;
699 mmc->max_phys_segs = NR_SG;
702 * Since we only have a 16-bit data length register, we must
703 * ensure that we don't exceed 2^16-1 bytes in a single request.
705 mmc->max_req_size = 65535;
708 * Set the maximum segment size. Since we aren't doing DMA
709 * (yet) we are only limited by the data length register.
711 mmc->max_seg_size = mmc->max_req_size;
714 * Block size can be up to 2048 bytes, but must be a power of two.
716 mmc->max_blk_size = 2048;
719 * No limit on the number of blocks transferred.
721 mmc->max_blk_count = mmc->max_req_size;
723 spin_lock_init(&host->lock);
725 writel(0, host->base + MMCIMASK0);
726 writel(0, host->base + MMCIMASK1);
727 writel(0xfff, host->base + MMCICLEAR);
729 if (gpio_is_valid(plat->gpio_cd)) {
730 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
732 ret = gpio_direction_input(plat->gpio_cd);
734 host->gpio_cd = plat->gpio_cd;
735 else if (ret != -ENOSYS)
738 if (gpio_is_valid(plat->gpio_wp)) {
739 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
741 ret = gpio_direction_input(plat->gpio_wp);
743 host->gpio_wp = plat->gpio_wp;
744 else if (ret != -ENOSYS)
748 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
752 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
756 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
758 amba_set_drvdata(dev, mmc);
762 dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
763 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
764 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
769 free_irq(dev->irq[0], host);
771 if (host->gpio_wp != -ENOSYS)
772 gpio_free(host->gpio_wp);
774 if (host->gpio_cd != -ENOSYS)
775 gpio_free(host->gpio_cd);
779 clk_disable(host->clk);
785 amba_release_regions(dev);
790 static int __devexit mmci_remove(struct amba_device *dev)
792 struct mmc_host *mmc = amba_get_drvdata(dev);
794 amba_set_drvdata(dev, NULL);
797 struct mmci_host *host = mmc_priv(mmc);
799 mmc_remove_host(mmc);
801 writel(0, host->base + MMCIMASK0);
802 writel(0, host->base + MMCIMASK1);
804 writel(0, host->base + MMCICOMMAND);
805 writel(0, host->base + MMCIDATACTRL);
807 free_irq(dev->irq[0], host);
808 free_irq(dev->irq[1], host);
810 if (host->gpio_wp != -ENOSYS)
811 gpio_free(host->gpio_wp);
812 if (host->gpio_cd != -ENOSYS)
813 gpio_free(host->gpio_cd);
816 clk_disable(host->clk);
819 if (regulator_is_enabled(host->vcc))
820 regulator_disable(host->vcc);
821 regulator_put(host->vcc);
825 amba_release_regions(dev);
832 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
834 struct mmc_host *mmc = amba_get_drvdata(dev);
838 struct mmci_host *host = mmc_priv(mmc);
840 ret = mmc_suspend_host(mmc);
842 writel(0, host->base + MMCIMASK0);
848 static int mmci_resume(struct amba_device *dev)
850 struct mmc_host *mmc = amba_get_drvdata(dev);
854 struct mmci_host *host = mmc_priv(mmc);
856 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
858 ret = mmc_resume_host(mmc);
864 #define mmci_suspend NULL
865 #define mmci_resume NULL
868 static struct amba_id mmci_ids[] = {
872 .data = &variant_arm,
877 .data = &variant_arm,
879 /* ST Micro variants */
883 .data = &variant_u300,
888 .data = &variant_u300,
893 .data = &variant_ux500,
898 static struct amba_driver mmci_driver = {
903 .remove = __devexit_p(mmci_remove),
904 .suspend = mmci_suspend,
905 .resume = mmci_resume,
906 .id_table = mmci_ids,
909 static int __init mmci_init(void)
911 return amba_driver_register(&mmci_driver);
914 static void __exit mmci_exit(void)
916 amba_driver_unregister(&mmci_driver);
919 module_init(mmci_init);
920 module_exit(mmci_exit);
921 module_param(fmax, uint, 0444);
923 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
924 MODULE_LICENSE("GPL");