2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/card.h>
23 #include <linux/amba/bus.h>
24 #include <linux/clk.h>
25 #include <linux/scatterlist.h>
26 #include <linux/gpio.h>
27 #include <linux/amba/mmci.h>
28 #include <linux/regulator/consumer.h>
30 #include <asm/div64.h>
32 #include <asm/sizes.h>
36 #define DRIVER_NAME "mmci-pl18x"
38 static unsigned int fmax = 515633;
41 * struct variant_data - MMCI variant-specific quirks
42 * @clkreg: default value for MCICLOCK register
43 * @clkreg_enable: enable value for MMCICLOCK register
44 * @datalength_bits: number of bits in the MMCIDATALENGTH register
45 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
46 * is asserted (likewise for RX)
47 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
48 * is asserted (likewise for RX)
49 * @broken_blockend: the MCI_DATABLOCKEND is broken on the hardware
50 * and will not work at all.
51 * @broken_blockend_dma: the MCI_DATABLOCKEND is broken on the hardware when
53 * @sdio: variant supports SDIO
54 * @st_clkdiv: true if using a ST-specific clock divider algorithm
58 unsigned int clkreg_enable;
59 unsigned int datalength_bits;
60 unsigned int fifosize;
61 unsigned int fifohalfsize;
63 bool broken_blockend_dma;
68 static struct variant_data variant_arm = {
70 .fifohalfsize = 8 * 4,
71 .datalength_bits = 16,
74 static struct variant_data variant_u300 = {
76 .fifohalfsize = 8 * 4,
77 .clkreg_enable = 1 << 13, /* HWFCEN */
78 .datalength_bits = 16,
79 .broken_blockend_dma = true,
83 static struct variant_data variant_ux500 = {
85 .fifohalfsize = 8 * 4,
86 .clkreg = MCI_CLK_ENABLE,
87 .clkreg_enable = 1 << 14, /* HWFCEN */
88 .datalength_bits = 24,
89 .broken_blockend = true,
95 * This must be called with host->lock held
97 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
99 struct variant_data *variant = host->variant;
100 u32 clk = variant->clkreg;
103 if (desired >= host->mclk) {
104 clk = MCI_CLK_BYPASS;
105 host->cclk = host->mclk;
106 } else if (variant->st_clkdiv) {
108 * DB8500 TRM says f = mclk / (clkdiv + 2)
109 * => clkdiv = (mclk / f) - 2
110 * Round the divider up so we don't exceed the max
113 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
116 host->cclk = host->mclk / (clk + 2);
119 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
120 * => clkdiv = mclk / (2 * f) - 1
122 clk = host->mclk / (2 * desired) - 1;
125 host->cclk = host->mclk / (2 * (clk + 1));
128 clk |= variant->clkreg_enable;
129 clk |= MCI_CLK_ENABLE;
130 /* This hasn't proven to be worthwhile */
131 /* clk |= MCI_CLK_PWRSAVE; */
134 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
136 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
137 clk |= MCI_ST_8BIT_BUS;
139 writel(clk, host->base + MMCICLOCK);
143 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
145 writel(0, host->base + MMCICOMMAND);
153 mrq->data->bytes_xfered = host->data_xfered;
156 * Need to drop the host lock here; mmc_request_done may call
157 * back into the driver...
159 spin_unlock(&host->lock);
160 mmc_request_done(host->mmc, mrq);
161 spin_lock(&host->lock);
164 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
166 void __iomem *base = host->base;
168 if (host->singleirq) {
169 unsigned int mask0 = readl(base + MMCIMASK0);
171 mask0 &= ~MCI_IRQ1MASK;
174 writel(mask0, base + MMCIMASK0);
177 writel(mask, base + MMCIMASK1);
180 static void mmci_stop_data(struct mmci_host *host)
182 writel(0, host->base + MMCIDATACTRL);
183 mmci_set_mask1(host, 0);
187 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
189 unsigned int flags = SG_MITER_ATOMIC;
191 if (data->flags & MMC_DATA_READ)
192 flags |= SG_MITER_TO_SG;
194 flags |= SG_MITER_FROM_SG;
196 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
199 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
201 struct variant_data *variant = host->variant;
202 unsigned int datactrl, timeout, irqmask;
203 unsigned long long clks;
207 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
208 data->blksz, data->blocks, data->flags);
211 host->size = data->blksz * data->blocks;
212 host->data_xfered = 0;
213 host->blockend = false;
214 host->dataend = false;
216 mmci_init_sg(host, data);
218 clks = (unsigned long long)data->timeout_ns * host->cclk;
219 do_div(clks, 1000000000UL);
221 timeout = data->timeout_clks + (unsigned int)clks;
224 writel(timeout, base + MMCIDATATIMER);
225 writel(host->size, base + MMCIDATALENGTH);
227 blksz_bits = ffs(data->blksz) - 1;
228 BUG_ON(1 << blksz_bits != data->blksz);
230 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
231 if (data->flags & MMC_DATA_READ) {
232 datactrl |= MCI_DPSM_DIRECTION;
233 irqmask = MCI_RXFIFOHALFFULLMASK;
236 * If we have less than a FIFOSIZE of bytes to transfer,
237 * trigger a PIO interrupt as soon as any data is available.
239 if (host->size < variant->fifosize)
240 irqmask |= MCI_RXDATAAVLBLMASK;
243 * We don't actually need to include "FIFO empty" here
244 * since its implicit in "FIFO half empty".
246 irqmask = MCI_TXFIFOHALFEMPTYMASK;
249 /* The ST Micro variants has a special bit to enable SDIO */
250 if (variant->sdio && host->mmc->card)
251 if (mmc_card_sdio(host->mmc->card))
252 datactrl |= MCI_ST_DPSM_SDIOEN;
254 writel(datactrl, base + MMCIDATACTRL);
255 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
256 mmci_set_mask1(host, irqmask);
260 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
262 void __iomem *base = host->base;
264 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
265 cmd->opcode, cmd->arg, cmd->flags);
267 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
268 writel(0, base + MMCICOMMAND);
272 c |= cmd->opcode | MCI_CPSM_ENABLE;
273 if (cmd->flags & MMC_RSP_PRESENT) {
274 if (cmd->flags & MMC_RSP_136)
275 c |= MCI_CPSM_LONGRSP;
276 c |= MCI_CPSM_RESPONSE;
279 c |= MCI_CPSM_INTERRUPT;
283 writel(cmd->arg, base + MMCIARGUMENT);
284 writel(c, base + MMCICOMMAND);
288 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
291 struct variant_data *variant = host->variant;
293 /* First check for errors */
294 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
295 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
296 if (status & MCI_DATACRCFAIL)
297 data->error = -EILSEQ;
298 else if (status & MCI_DATATIMEOUT)
299 data->error = -ETIMEDOUT;
300 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
303 /* Force-complete the transaction */
304 host->blockend = true;
305 host->dataend = true;
308 * We hit an error condition. Ensure that any data
309 * partially written to a page is properly coherent.
311 if (data->flags & MMC_DATA_READ) {
312 struct sg_mapping_iter *sg_miter = &host->sg_miter;
315 local_irq_save(flags);
316 if (sg_miter_next(sg_miter)) {
317 flush_dcache_page(sg_miter->page);
318 sg_miter_stop(sg_miter);
320 local_irq_restore(flags);
325 * On ARM variants in PIO mode, MCI_DATABLOCKEND
326 * is always sent first, and we increase the
327 * transfered number of bytes for that IRQ. Then
328 * MCI_DATAEND follows and we conclude the transaction.
330 * On the Ux500 single-IRQ variant MCI_DATABLOCKEND
331 * doesn't seem to immediately clear from the status,
332 * so we can't use it keep count when only one irq is
333 * used because the irq will hit for other reasons, and
334 * then the flag is still up. So we use the MCI_DATAEND
335 * IRQ at the end of the entire transfer because
336 * MCI_DATABLOCKEND is broken.
338 * In the U300, the IRQs can arrive out-of-order,
339 * e.g. MCI_DATABLOCKEND sometimes arrives after MCI_DATAEND,
340 * so for this case we use the flags "blockend" and
341 * "dataend" to make sure both IRQs have arrived before
342 * concluding the transaction. (This does not apply
343 * to the Ux500 which doesn't fire MCI_DATABLOCKEND
344 * at all.) In DMA mode it suffers from the same problem
347 if (status & MCI_DATABLOCKEND) {
349 * Just being a little over-cautious, we do not
350 * use this progressive update if the hardware blockend
351 * flag is unreliable: since it can stay high between
352 * IRQs it will corrupt the transfer counter.
354 if (!variant->broken_blockend)
355 host->data_xfered += data->blksz;
356 host->blockend = true;
359 if (status & MCI_DATAEND)
360 host->dataend = true;
363 * On variants with broken blockend we shall only wait for dataend,
364 * on others we must sync with the blockend signal since they can
365 * appear out-of-order.
367 if (host->dataend && (host->blockend || variant->broken_blockend)) {
368 mmci_stop_data(host);
370 /* Reset these flags */
371 host->blockend = false;
372 host->dataend = false;
375 * Variants with broken blockend flags need to handle the
376 * end of the entire transfer here.
378 if (variant->broken_blockend && !data->error)
379 host->data_xfered += data->blksz * data->blocks;
382 mmci_request_end(host, data->mrq);
384 mmci_start_command(host, data->stop, 0);
390 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
393 void __iomem *base = host->base;
397 cmd->resp[0] = readl(base + MMCIRESPONSE0);
398 cmd->resp[1] = readl(base + MMCIRESPONSE1);
399 cmd->resp[2] = readl(base + MMCIRESPONSE2);
400 cmd->resp[3] = readl(base + MMCIRESPONSE3);
402 if (status & MCI_CMDTIMEOUT) {
403 cmd->error = -ETIMEDOUT;
404 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
405 cmd->error = -EILSEQ;
408 if (!cmd->data || cmd->error) {
410 mmci_stop_data(host);
411 mmci_request_end(host, cmd->mrq);
412 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
413 mmci_start_data(host, cmd->data);
417 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
419 void __iomem *base = host->base;
422 int host_remain = host->size;
425 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
433 readsl(base + MMCIFIFO, ptr, count >> 2);
437 host_remain -= count;
442 status = readl(base + MMCISTATUS);
443 } while (status & MCI_RXDATAAVLBL);
448 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
450 struct variant_data *variant = host->variant;
451 void __iomem *base = host->base;
455 unsigned int count, maxcnt;
457 maxcnt = status & MCI_TXFIFOEMPTY ?
458 variant->fifosize : variant->fifohalfsize;
459 count = min(remain, maxcnt);
462 * The ST Micro variant for SDIO transfer sizes
463 * less then 8 bytes should have clock H/W flow
467 mmc_card_sdio(host->mmc->card)) {
469 writel(readl(host->base + MMCICLOCK) &
470 ~variant->clkreg_enable,
471 host->base + MMCICLOCK);
473 writel(readl(host->base + MMCICLOCK) |
474 variant->clkreg_enable,
475 host->base + MMCICLOCK);
479 * SDIO especially may want to send something that is
480 * not divisible by 4 (as opposed to card sectors
481 * etc), and the FIFO only accept full 32-bit writes.
482 * So compensate by adding +3 on the count, a single
483 * byte become a 32bit write, 7 bytes will be two
486 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
494 status = readl(base + MMCISTATUS);
495 } while (status & MCI_TXFIFOHALFEMPTY);
501 * PIO data transfer IRQ handler.
503 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
505 struct mmci_host *host = dev_id;
506 struct sg_mapping_iter *sg_miter = &host->sg_miter;
507 struct variant_data *variant = host->variant;
508 void __iomem *base = host->base;
512 status = readl(base + MMCISTATUS);
514 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
516 local_irq_save(flags);
519 unsigned int remain, len;
523 * For write, we only need to test the half-empty flag
524 * here - if the FIFO is completely empty, then by
525 * definition it is more than half empty.
527 * For read, check for data available.
529 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
532 if (!sg_miter_next(sg_miter))
535 buffer = sg_miter->addr;
536 remain = sg_miter->length;
539 if (status & MCI_RXACTIVE)
540 len = mmci_pio_read(host, buffer, remain);
541 if (status & MCI_TXACTIVE)
542 len = mmci_pio_write(host, buffer, remain, status);
544 sg_miter->consumed = len;
552 if (status & MCI_RXACTIVE)
553 flush_dcache_page(sg_miter->page);
555 status = readl(base + MMCISTATUS);
558 sg_miter_stop(sg_miter);
560 local_irq_restore(flags);
563 * If we're nearing the end of the read, switch to
564 * "any data available" mode.
566 if (status & MCI_RXACTIVE && host->size < variant->fifosize)
567 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
570 * If we run out of data, disable the data IRQs; this
571 * prevents a race where the FIFO becomes empty before
572 * the chip itself has disabled the data path, and
573 * stops us racing with our data end IRQ.
575 if (host->size == 0) {
576 mmci_set_mask1(host, 0);
577 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
584 * Handle completion of command and data transfers.
586 static irqreturn_t mmci_irq(int irq, void *dev_id)
588 struct mmci_host *host = dev_id;
592 spin_lock(&host->lock);
595 struct mmc_command *cmd;
596 struct mmc_data *data;
598 status = readl(host->base + MMCISTATUS);
600 if (host->singleirq) {
601 if (status & readl(host->base + MMCIMASK1))
602 mmci_pio_irq(irq, dev_id);
604 status &= ~MCI_IRQ1MASK;
607 status &= readl(host->base + MMCIMASK0);
608 writel(status, host->base + MMCICLEAR);
610 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
613 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
614 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
615 mmci_data_irq(host, data, status);
618 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
619 mmci_cmd_irq(host, cmd, status);
624 spin_unlock(&host->lock);
626 return IRQ_RETVAL(ret);
629 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
631 struct mmci_host *host = mmc_priv(mmc);
634 WARN_ON(host->mrq != NULL);
636 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
637 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
639 mrq->cmd->error = -EINVAL;
640 mmc_request_done(mmc, mrq);
644 spin_lock_irqsave(&host->lock, flags);
648 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
649 mmci_start_data(host, mrq->data);
651 mmci_start_command(host, mrq->cmd, 0);
653 spin_unlock_irqrestore(&host->lock, flags);
656 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
658 struct mmci_host *host = mmc_priv(mmc);
663 switch (ios->power_mode) {
666 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
670 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
672 dev_err(mmc_dev(mmc), "unable to set OCR\n");
674 * The .set_ios() function in the mmc_host_ops
675 * struct return void, and failing to set the
676 * power should be rare so we print an error
682 if (host->plat->vdd_handler)
683 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
685 /* The ST version does not have this, fall through to POWER_ON */
686 if (host->hw_designer != AMBA_VENDOR_ST) {
695 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
696 if (host->hw_designer != AMBA_VENDOR_ST)
700 * The ST Micro variant use the ROD bit for something
701 * else and only has OD (Open Drain).
707 spin_lock_irqsave(&host->lock, flags);
709 mmci_set_clkreg(host, ios->clock);
711 if (host->pwr != pwr) {
713 writel(pwr, host->base + MMCIPOWER);
716 spin_unlock_irqrestore(&host->lock, flags);
719 static int mmci_get_ro(struct mmc_host *mmc)
721 struct mmci_host *host = mmc_priv(mmc);
723 if (host->gpio_wp == -ENOSYS)
726 return gpio_get_value_cansleep(host->gpio_wp);
729 static int mmci_get_cd(struct mmc_host *mmc)
731 struct mmci_host *host = mmc_priv(mmc);
732 struct mmci_platform_data *plat = host->plat;
735 if (host->gpio_cd == -ENOSYS) {
737 return 1; /* Assume always present */
739 status = plat->status(mmc_dev(host->mmc));
741 status = !!gpio_get_value_cansleep(host->gpio_cd)
745 * Use positive logic throughout - status is zero for no card,
746 * non-zero for card inserted.
751 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
753 struct mmci_host *host = dev_id;
755 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
760 static const struct mmc_host_ops mmci_ops = {
761 .request = mmci_request,
762 .set_ios = mmci_set_ios,
763 .get_ro = mmci_get_ro,
764 .get_cd = mmci_get_cd,
767 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
769 struct mmci_platform_data *plat = dev->dev.platform_data;
770 struct variant_data *variant = id->data;
771 struct mmci_host *host;
772 struct mmc_host *mmc;
776 /* must have platform data */
782 ret = amba_request_regions(dev, DRIVER_NAME);
786 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
792 host = mmc_priv(mmc);
795 host->gpio_wp = -ENOSYS;
796 host->gpio_cd = -ENOSYS;
797 host->gpio_cd_irq = -1;
799 host->hw_designer = amba_manf(dev);
800 host->hw_revision = amba_rev(dev);
801 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
802 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
804 host->clk = clk_get(&dev->dev, NULL);
805 if (IS_ERR(host->clk)) {
806 ret = PTR_ERR(host->clk);
811 ret = clk_enable(host->clk);
816 host->variant = variant;
817 host->mclk = clk_get_rate(host->clk);
819 * According to the spec, mclk is max 100 MHz,
820 * so we try to adjust the clock down to this,
823 if (host->mclk > 100000000) {
824 ret = clk_set_rate(host->clk, 100000000);
827 host->mclk = clk_get_rate(host->clk);
828 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
831 host->base = ioremap(dev->res.start, resource_size(&dev->res));
837 mmc->ops = &mmci_ops;
838 mmc->f_min = (host->mclk + 511) / 512;
840 * If the platform data supplies a maximum operating
841 * frequency, this takes precedence. Else, we fall back
842 * to using the module parameter, which has a (low)
843 * default value in case it is not specified. Either
844 * value must not exceed the clock rate into the block,
848 mmc->f_max = min(host->mclk, plat->f_max);
850 mmc->f_max = min(host->mclk, fmax);
851 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
853 #ifdef CONFIG_REGULATOR
854 /* If we're using the regulator framework, try to fetch a regulator */
855 host->vcc = regulator_get(&dev->dev, "vmmc");
856 if (IS_ERR(host->vcc))
859 int mask = mmc_regulator_get_ocrmask(host->vcc);
862 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
865 host->mmc->ocr_avail = (u32) mask;
868 "Provided ocr_mask/setpower will not be used "
869 "(using regulator instead)\n");
873 /* Fall back to platform data if no regulator is found */
874 if (host->vcc == NULL)
875 mmc->ocr_avail = plat->ocr_mask;
876 mmc->caps = plat->capabilities;
881 mmc->max_segs = NR_SG;
884 * Since only a certain number of bits are valid in the data length
885 * register, we must ensure that we don't exceed 2^num-1 bytes in a
888 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
891 * Set the maximum segment size. Since we aren't doing DMA
892 * (yet) we are only limited by the data length register.
894 mmc->max_seg_size = mmc->max_req_size;
897 * Block size can be up to 2048 bytes, but must be a power of two.
899 mmc->max_blk_size = 2048;
902 * No limit on the number of blocks transferred.
904 mmc->max_blk_count = mmc->max_req_size;
906 spin_lock_init(&host->lock);
908 writel(0, host->base + MMCIMASK0);
909 writel(0, host->base + MMCIMASK1);
910 writel(0xfff, host->base + MMCICLEAR);
912 if (gpio_is_valid(plat->gpio_cd)) {
913 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
915 ret = gpio_direction_input(plat->gpio_cd);
917 host->gpio_cd = plat->gpio_cd;
918 else if (ret != -ENOSYS)
921 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
923 DRIVER_NAME " (cd)", host);
925 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
927 if (gpio_is_valid(plat->gpio_wp)) {
928 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
930 ret = gpio_direction_input(plat->gpio_wp);
932 host->gpio_wp = plat->gpio_wp;
933 else if (ret != -ENOSYS)
937 if ((host->plat->status || host->gpio_cd != -ENOSYS)
938 && host->gpio_cd_irq < 0)
939 mmc->caps |= MMC_CAP_NEEDS_POLL;
941 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
945 if (dev->irq[1] == NO_IRQ)
946 host->singleirq = true;
948 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
949 DRIVER_NAME " (pio)", host);
954 mask = MCI_IRQENABLE;
955 /* Don't use the datablockend flag if it's broken */
956 if (variant->broken_blockend)
957 mask &= ~MCI_DATABLOCKEND;
959 writel(mask, host->base + MMCIMASK0);
961 amba_set_drvdata(dev, mmc);
963 dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n",
964 mmc_hostname(mmc), amba_part(dev), amba_rev(dev),
965 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
972 free_irq(dev->irq[0], host);
974 if (host->gpio_wp != -ENOSYS)
975 gpio_free(host->gpio_wp);
977 if (host->gpio_cd_irq >= 0)
978 free_irq(host->gpio_cd_irq, host);
979 if (host->gpio_cd != -ENOSYS)
980 gpio_free(host->gpio_cd);
984 clk_disable(host->clk);
990 amba_release_regions(dev);
995 static int __devexit mmci_remove(struct amba_device *dev)
997 struct mmc_host *mmc = amba_get_drvdata(dev);
999 amba_set_drvdata(dev, NULL);
1002 struct mmci_host *host = mmc_priv(mmc);
1004 mmc_remove_host(mmc);
1006 writel(0, host->base + MMCIMASK0);
1007 writel(0, host->base + MMCIMASK1);
1009 writel(0, host->base + MMCICOMMAND);
1010 writel(0, host->base + MMCIDATACTRL);
1012 free_irq(dev->irq[0], host);
1013 if (!host->singleirq)
1014 free_irq(dev->irq[1], host);
1016 if (host->gpio_wp != -ENOSYS)
1017 gpio_free(host->gpio_wp);
1018 if (host->gpio_cd_irq >= 0)
1019 free_irq(host->gpio_cd_irq, host);
1020 if (host->gpio_cd != -ENOSYS)
1021 gpio_free(host->gpio_cd);
1023 iounmap(host->base);
1024 clk_disable(host->clk);
1028 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1029 regulator_put(host->vcc);
1033 amba_release_regions(dev);
1040 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1042 struct mmc_host *mmc = amba_get_drvdata(dev);
1046 struct mmci_host *host = mmc_priv(mmc);
1048 ret = mmc_suspend_host(mmc);
1050 writel(0, host->base + MMCIMASK0);
1056 static int mmci_resume(struct amba_device *dev)
1058 struct mmc_host *mmc = amba_get_drvdata(dev);
1062 struct mmci_host *host = mmc_priv(mmc);
1064 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1066 ret = mmc_resume_host(mmc);
1072 #define mmci_suspend NULL
1073 #define mmci_resume NULL
1076 static struct amba_id mmci_ids[] = {
1080 .data = &variant_arm,
1085 .data = &variant_arm,
1087 /* ST Micro variants */
1091 .data = &variant_u300,
1096 .data = &variant_u300,
1101 .data = &variant_ux500,
1106 static struct amba_driver mmci_driver = {
1108 .name = DRIVER_NAME,
1110 .probe = mmci_probe,
1111 .remove = __devexit_p(mmci_remove),
1112 .suspend = mmci_suspend,
1113 .resume = mmci_resume,
1114 .id_table = mmci_ids,
1117 static int __init mmci_init(void)
1119 return amba_driver_register(&mmci_driver);
1122 static void __exit mmci_exit(void)
1124 amba_driver_unregister(&mmci_driver);
1127 module_init(mmci_init);
1128 module_exit(mmci_exit);
1129 module_param(fmax, uint, 0444);
1131 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1132 MODULE_LICENSE("GPL");