drivers/mmc/host/msm_sdcc.c

   1 /*
   2  *  linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
   3  *
   4  *  Copyright (C) 2007 Google Inc,
   5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   6  *  Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Based on mmci.c
  13  *
  14  * Author: San Mehat (san@android.com)
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/init.h>
  21 #include <linux/ioport.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/highmem.h>
  27 #include <linux/log2.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/card.h>
  30 #include <linux/mmc/sdio.h>
  31 #include <linux/clk.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/io.h>
  37 #include <linux/memory.h>
  38
  39 #include <asm/cacheflush.h>
  40 #include <asm/div64.h>
  41 #include <asm/sizes.h>
  42
  43 #include <mach/mmc.h>
  44 #include <mach/msm_iomap.h>
  45 #include <mach/dma.h>
  46
  47 #include "msm_sdcc.h"
  48
  49 #define DRIVER_NAME "msm-sdcc"
  50
  51 #define BUSCLK_PWRSAVE 1
  52 #define BUSCLK_TIMEOUT (HZ)
  53 static unsigned int msmsdcc_fmin = 144000;
  54 static unsigned int msmsdcc_fmax = 50000000;
  55 static unsigned int msmsdcc_4bit = 1;
  56 static unsigned int msmsdcc_pwrsave = 1;
  57 static unsigned int msmsdcc_piopoll = 1;
  58 static unsigned int msmsdcc_sdioirq;
  59
  60 #define PIO_SPINMAX 30
  61 #define CMD_SPINMAX 20
  62
  63
  64 static inline void
  65 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
  66 {
  67         WARN_ON(!host->clks_on);
  68
  69         BUG_ON(host->curr.mrq);
  70
  71         if (deferr) {
  72                 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
  73         } else {
  74                 del_timer_sync(&host->busclk_timer);
  75                 /* Need to check clks_on again in case the busclk
  76                  * timer fired
  77                  */
  78                 if (host->clks_on) {
  79                         clk_disable(host->clk);
  80                         clk_disable(host->pclk);
  81                         host->clks_on = 0;
  82                 }
  83         }
  84 }
  85
  86 static inline int
  87 msmsdcc_enable_clocks(struct msmsdcc_host *host)
  88 {
  89         int rc;
  90
  91         del_timer_sync(&host->busclk_timer);
  92
  93         if (!host->clks_on) {
  94                 rc = clk_enable(host->pclk);
  95                 if (rc)
  96                         return rc;
  97                 rc = clk_enable(host->clk);
  98                 if (rc) {
  99                         clk_disable(host->pclk);
 100                         return rc;
 101                 }
 102                 udelay(1 + ((3 * USEC_PER_SEC) /
 103                        (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
 104                 host->clks_on = 1;
 105         }
 106         return 0;
 107 }
 108
 109 static inline unsigned int
 110 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
 111 {
 112         return readl(host->base + reg);
 113 }
 114
 115 static inline void
 116 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
 117 {
 118         writel(data, host->base + reg);
 119         /* 3 clk delay required! */
 120         udelay(1 + ((3 * USEC_PER_SEC) /
 121                (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
 122 }
 123
 124 static void
 125 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
 126                       u32 c);
 127
 128 static void
 129 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
 130 {
 131         BUG_ON(host->curr.data);
 132
 133         host->curr.mrq = NULL;
 134         host->curr.cmd = NULL;
 135
 136         if (mrq->data)
 137                 mrq->data->bytes_xfered = host->curr.data_xfered;
 138         if (mrq->cmd->error == -ETIMEDOUT)
 139                 mdelay(5);
 140
 141 #if BUSCLK_PWRSAVE
 142         msmsdcc_disable_clocks(host, 1);
 143 #endif
 144         /*
 145          * Need to drop the host lock here; mmc_request_done may call
 146          * back into the driver...
 147          */
 148         spin_unlock(&host->lock);
 149         mmc_request_done(host->mmc, mrq);
 150         spin_lock(&host->lock);
 151 }
 152
 153 static void
 154 msmsdcc_stop_data(struct msmsdcc_host *host)
 155 {
 156         host->curr.data = NULL;
 157         host->curr.got_dataend = host->curr.got_datablkend = 0;
 158 }
 159
 160 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
 161 {
 162         switch (host->pdev_id) {
 163         case 1:
 164                 return MSM_SDC1_PHYS + MMCIFIFO;
 165         case 2:
 166                 return MSM_SDC2_PHYS + MMCIFIFO;
 167         case 3:
 168                 return MSM_SDC3_PHYS + MMCIFIFO;
 169         case 4:
 170                 return MSM_SDC4_PHYS + MMCIFIFO;
 171         }
 172         BUG();
 173         return 0;
 174 }
 175
 176 static inline void
 177 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
 178        msmsdcc_writel(host, arg, MMCIARGUMENT);
 179        msmsdcc_writel(host, c, MMCICOMMAND);
 180 }
 181
 182 static void
 183 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
 184 {
 185         struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
 186
 187         msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
 188         msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
 189                        MMCIDATALENGTH);
 190         msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
 191         msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
 192
 193         if (host->cmd_cmd) {
 194                 msmsdcc_start_command_exec(host,
 195                                            (u32) host->cmd_cmd->arg,
 196                                            (u32) host->cmd_c);
 197         }
 198         host->dma.active = 1;
 199 }
 200
 201 static void
 202 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
 203                           unsigned int result,
 204                           struct msm_dmov_errdata *err)
 205 {
 206         struct msmsdcc_dma_data *dma_data =
 207                 container_of(cmd, struct msmsdcc_dma_data, hdr);
 208         struct msmsdcc_host     *host = dma_data->host;
 209         unsigned long           flags;
 210         struct mmc_request      *mrq;
 211
 212         spin_lock_irqsave(&host->lock, flags);
 213         host->dma.active = 0;
 214
 215         mrq = host->curr.mrq;
 216         BUG_ON(!mrq);
 217         WARN_ON(!mrq->data);
 218
 219         if (!(result & DMOV_RSLT_VALID)) {
 220                 pr_err("msmsdcc: Invalid DataMover result\n");
 221                 goto out;
 222         }
 223
 224         if (result & DMOV_RSLT_DONE) {
 225                 host->curr.data_xfered = host->curr.xfer_size;
 226         } else {
 227                 /* Error or flush  */
 228                 if (result & DMOV_RSLT_ERROR)
 229                         pr_err("%s: DMA error (0x%.8x)\n",
 230                                mmc_hostname(host->mmc), result);
 231                 if (result & DMOV_RSLT_FLUSH)
 232                         pr_err("%s: DMA channel flushed (0x%.8x)\n",
 233                                mmc_hostname(host->mmc), result);
 234                 if (err)
 235                         pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
 236                                err->flush[0], err->flush[1], err->flush[2],
 237                                err->flush[3], err->flush[4], err->flush[5]);
 238                 if (!mrq->data->error)
 239                         mrq->data->error = -EIO;
 240         }
 241         dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
 242                      host->dma.dir);
 243
 244         if (host->curr.user_pages) {
 245                 struct scatterlist *sg = host->dma.sg;
 246                 int i;
 247
 248                 for (i = 0; i < host->dma.num_ents; i++)
 249                         flush_dcache_page(sg_page(sg++));
 250         }
 251
 252         host->dma.sg = NULL;
 253         host->dma.busy = 0;
 254
 255         if ((host->curr.got_dataend && host->curr.got_datablkend)
 256              || mrq->data->error) {
 257
 258                 /*
 259                  * If we've already gotten our DATAEND / DATABLKEND
 260                  * for this request, then complete it through here.
 261                  */
 262                 msmsdcc_stop_data(host);
 263
 264                 if (!mrq->data->error)
 265                         host->curr.data_xfered = host->curr.xfer_size;
 266                 if (!mrq->data->stop || mrq->cmd->error) {
 267                         host->curr.mrq = NULL;
 268                         host->curr.cmd = NULL;
 269                         mrq->data->bytes_xfered = host->curr.data_xfered;
 270
 271                         spin_unlock_irqrestore(&host->lock, flags);
 272 #if BUSCLK_PWRSAVE
 273                         msmsdcc_disable_clocks(host, 1);
 274 #endif
 275                         mmc_request_done(host->mmc, mrq);
 276                         return;
 277                 } else
 278                         msmsdcc_start_command(host, mrq->data->stop, 0);
 279         }
 280
 281 out:
 282         spin_unlock_irqrestore(&host->lock, flags);
 283         return;
 284 }
 285
 286 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
 287 {
 288         if (host->dma.channel == -1)
 289                 return -ENOENT;
 290
 291         if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
 292                 return -EINVAL;
 293         if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
 294                 return -EINVAL;
 295         return 0;
 296 }
 297
 298 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
 299 {
 300         struct msmsdcc_nc_dmadata *nc;
 301         dmov_box *box;
 302         uint32_t rows;
 303         uint32_t crci;
 304         unsigned int n;
 305         int i, rc;
 306         struct scatterlist *sg = data->sg;
 307
 308         rc = validate_dma(host, data);
 309         if (rc)
 310                 return rc;
 311
 312         host->dma.sg = data->sg;
 313         host->dma.num_ents = data->sg_len;
 314
 315        BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
 316
 317         nc = host->dma.nc;
 318
 319         switch (host->pdev_id) {
 320         case 1:
 321                 crci = MSMSDCC_CRCI_SDC1;
 322                 break;
 323         case 2:
 324                 crci = MSMSDCC_CRCI_SDC2;
 325                 break;
 326         case 3:
 327                 crci = MSMSDCC_CRCI_SDC3;
 328                 break;
 329         case 4:
 330                 crci = MSMSDCC_CRCI_SDC4;
 331                 break;
 332         default:
 333                 host->dma.sg = NULL;
 334                 host->dma.num_ents = 0;
 335                 return -ENOENT;
 336         }
 337
 338         if (data->flags & MMC_DATA_READ)
 339                 host->dma.dir = DMA_FROM_DEVICE;
 340         else
 341                 host->dma.dir = DMA_TO_DEVICE;
 342
 343         host->curr.user_pages = 0;
 344
 345         box = &nc->cmd[0];
 346         for (i = 0; i < host->dma.num_ents; i++) {
 347                 box->cmd = CMD_MODE_BOX;
 348
 349         /* Initialize sg dma address */
 350         sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg))
 351                                 + sg->offset;
 352
 353         if (i == (host->dma.num_ents - 1))
 354                         box->cmd |= CMD_LC;
 355                 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
 356                         (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
 357                         (sg_dma_len(sg) / MCI_FIFOSIZE) ;
 358
 359                 if (data->flags & MMC_DATA_READ) {
 360                         box->src_row_addr = msmsdcc_fifo_addr(host);
 361                         box->dst_row_addr = sg_dma_address(sg);
 362
 363                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 364                                            (MCI_FIFOSIZE);
 365                         box->row_offset = MCI_FIFOSIZE;
 366
 367                         box->num_rows = rows * ((1 << 16) + 1);
 368                         box->cmd |= CMD_SRC_CRCI(crci);
 369                 } else {
 370                         box->src_row_addr = sg_dma_address(sg);
 371                         box->dst_row_addr = msmsdcc_fifo_addr(host);
 372
 373                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 374                                            (MCI_FIFOSIZE);
 375                         box->row_offset = (MCI_FIFOSIZE << 16);
 376
 377                         box->num_rows = rows * ((1 << 16) + 1);
 378                         box->cmd |= CMD_DST_CRCI(crci);
 379                 }
 380                 box++;
 381                 sg++;
 382         }
 383
 384         /* location of command block must be 64 bit aligned */
 385         BUG_ON(host->dma.cmd_busaddr & 0x07);
 386
 387         nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
 388         host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
 389                                DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
 390         host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
 391
 392         n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
 393                         host->dma.num_ents, host->dma.dir);
 394 /* dsb inside dma_map_sg will write nc out to mem as well */
 395
 396         if (n != host->dma.num_ents) {
 397                 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
 398                         mmc_hostname(host->mmc));
 399                 host->dma.sg = NULL;
 400                 host->dma.num_ents = 0;
 401                 return -ENOMEM;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int
 408 snoop_cccr_abort(struct mmc_command *cmd)
 409 {
 410         if ((cmd->opcode == 52) &&
 411             (cmd->arg & 0x80000000) &&
 412             (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
 413                 return 1;
 414         return 0;
 415 }
 416
 417 static void
 418 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
 419                                 struct mmc_command *cmd, u32 *c)
 420 {
 421         *c |= (cmd->opcode | MCI_CPSM_ENABLE);
 422
 423         if (cmd->flags & MMC_RSP_PRESENT) {
 424                 if (cmd->flags & MMC_RSP_136)
 425                         *c |= MCI_CPSM_LONGRSP;
 426                 *c |= MCI_CPSM_RESPONSE;
 427         }
 428
 429         if (/*interrupt*/0)
 430                 *c |= MCI_CPSM_INTERRUPT;
 431
 432         if ((((cmd->opcode == 17) || (cmd->opcode == 18))  ||
 433              ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
 434               (cmd->opcode == 53))
 435                 *c |= MCI_CSPM_DATCMD;
 436
 437         if (cmd == cmd->mrq->stop)
 438                 *c |= MCI_CSPM_MCIABORT;
 439
 440         if (snoop_cccr_abort(cmd))
 441                 *c |= MCI_CSPM_MCIABORT;
 442
 443         if (host->curr.cmd != NULL) {
 444                 printk(KERN_ERR "%s: Overlapping command requests\n",
 445                         mmc_hostname(host->mmc));
 446         }
 447         host->curr.cmd = cmd;
 448 }
 449
 450 static void
 451 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
 452                         struct mmc_command *cmd, u32 c)
 453 {
 454         unsigned int datactrl, timeout;
 455         unsigned long long clks;
 456         unsigned int pio_irqmask = 0;
 457
 458         host->curr.data = data;
 459         host->curr.xfer_size = data->blksz * data->blocks;
 460         host->curr.xfer_remain = host->curr.xfer_size;
 461         host->curr.data_xfered = 0;
 462         host->curr.got_dataend = 0;
 463         host->curr.got_datablkend = 0;
 464
 465         memset(&host->pio, 0, sizeof(host->pio));
 466
 467         datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
 468
 469         if (!msmsdcc_config_dma(host, data))
 470                 datactrl |= MCI_DPSM_DMAENABLE;
 471         else {
 472                 host->pio.sg = data->sg;
 473                 host->pio.sg_len = data->sg_len;
 474                 host->pio.sg_off = 0;
 475
 476                 if (data->flags & MMC_DATA_READ) {
 477                         pio_irqmask = MCI_RXFIFOHALFFULLMASK;
 478                         if (host->curr.xfer_remain < MCI_FIFOSIZE)
 479                                 pio_irqmask |= MCI_RXDATAAVLBLMASK;
 480                 } else
 481                         pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
 482         }
 483
 484         if (data->flags & MMC_DATA_READ)
 485                 datactrl |= MCI_DPSM_DIRECTION;
 486
 487         clks = (unsigned long long)data->timeout_ns * host->clk_rate;
 488         do_div(clks, NSEC_PER_SEC);
 489         timeout = data->timeout_clks + (unsigned int)clks*2 ;
 490
 491         if (datactrl & MCI_DPSM_DMAENABLE) {
 492                 /* Save parameters for the exec function */
 493                 host->cmd_timeout = timeout;
 494                 host->cmd_pio_irqmask = pio_irqmask;
 495                 host->cmd_datactrl = datactrl;
 496                 host->cmd_cmd = cmd;
 497
 498                 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
 499                 host->dma.hdr.data = (void *)host;
 500                 host->dma.busy = 1;
 501
 502                 if (cmd) {
 503                         msmsdcc_start_command_deferred(host, cmd, &c);
 504                         host->cmd_c = c;
 505                 }
 506                 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
 507         } else {
 508                 msmsdcc_writel(host, timeout, MMCIDATATIMER);
 509
 510                 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
 511
 512                 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
 513                 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
 514
 515                 if (cmd) {
 516                         /* Daisy-chain the command if requested */
 517                         msmsdcc_start_command(host, cmd, c);
 518                 }
 519         }
 520 }
 521
 522 static void
 523 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
 524 {
 525         if (cmd == cmd->mrq->stop)
 526                 c |= MCI_CSPM_MCIABORT;
 527
 528         host->stats.cmds++;
 529
 530         msmsdcc_start_command_deferred(host, cmd, &c);
 531         msmsdcc_start_command_exec(host, cmd->arg, c);
 532 }
 533
 534 static void
 535 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
 536                  unsigned int status)
 537 {
 538         if (status & MCI_DATACRCFAIL) {
 539                 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
 540                 pr_err("%s: opcode 0x%.8x\n", __func__,
 541                        data->mrq->cmd->opcode);
 542                 pr_err("%s: blksz %d, blocks %d\n", __func__,
 543                        data->blksz, data->blocks);
 544                 data->error = -EILSEQ;
 545         } else if (status & MCI_DATATIMEOUT) {
 546                 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
 547                 data->error = -ETIMEDOUT;
 548         } else if (status & MCI_RXOVERRUN) {
 549                 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
 550                 data->error = -EIO;
 551         } else if (status & MCI_TXUNDERRUN) {
 552                 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
 553                 data->error = -EIO;
 554         } else {
 555                 pr_err("%s: Unknown error (0x%.8x)\n",
 556                        mmc_hostname(host->mmc), status);
 557                 data->error = -EIO;
 558         }
 559 }
 560
 561
 562 static int
 563 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
 564 {
 565         uint32_t        *ptr = (uint32_t *) buffer;
 566         int             count = 0;
 567
 568         while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
 569                 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
 570                 ptr++;
 571                 count += sizeof(uint32_t);
 572
 573                 remain -=  sizeof(uint32_t);
 574                 if (remain == 0)
 575                         break;
 576         }
 577         return count;
 578 }
 579
 580 static int
 581 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
 582                   unsigned int remain, u32 status)
 583 {
 584         void __iomem *base = host->base;
 585         char *ptr = buffer;
 586
 587         do {
 588                 unsigned int count, maxcnt;
 589
 590                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
 591                                                     MCI_FIFOHALFSIZE;
 592                 count = min(remain, maxcnt);
 593
 594                 writesl(base + MMCIFIFO, ptr, count >> 2);
 595                 ptr += count;
 596                 remain -= count;
 597
 598                 if (remain == 0)
 599                         break;
 600
 601                 status = msmsdcc_readl(host, MMCISTATUS);
 602         } while (status & MCI_TXFIFOHALFEMPTY);
 603
 604         return ptr - buffer;
 605 }
 606
 607 static int
 608 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
 609 {
 610         while (maxspin) {
 611                 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
 612                         return 0;
 613                 udelay(1);
 614                 --maxspin;
 615         }
 616         return -ETIMEDOUT;
 617 }
 618
 619 static int
 620 msmsdcc_pio_irq(int irq, void *dev_id)
 621 {
 622         struct msmsdcc_host     *host = dev_id;
 623         uint32_t                status;
 624
 625         status = msmsdcc_readl(host, MMCISTATUS);
 626
 627         do {
 628                 unsigned long flags;
 629                 unsigned int remain, len;
 630                 char *buffer;
 631
 632                 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
 633                         if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
 634                                 break;
 635
 636                         if (msmsdcc_spin_on_status(host,
 637                                                    (MCI_TXFIFOHALFEMPTY |
 638                                                    MCI_RXDATAAVLBL),
 639                                                    PIO_SPINMAX)) {
 640                                 break;
 641                         }
 642                 }
 643
 644                 /* Map the current scatter buffer */
 645                 local_irq_save(flags);
 646                 buffer = kmap_atomic(sg_page(host->pio.sg),
 647                                      KM_BIO_SRC_IRQ) + host->pio.sg->offset;
 648                 buffer += host->pio.sg_off;
 649                 remain = host->pio.sg->length - host->pio.sg_off;
 650                 len = 0;
 651                 if (status & MCI_RXACTIVE)
 652                         len = msmsdcc_pio_read(host, buffer, remain);
 653                 if (status & MCI_TXACTIVE)
 654                         len = msmsdcc_pio_write(host, buffer, remain, status);
 655
 656                 /* Unmap the buffer */
 657                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 658                 local_irq_restore(flags);
 659
 660                 host->pio.sg_off += len;
 661                 host->curr.xfer_remain -= len;
 662                 host->curr.data_xfered += len;
 663                 remain -= len;
 664
 665                 if (remain == 0) {
 666                         /* This sg page is full - do some housekeeping */
 667                         if (status & MCI_RXACTIVE && host->curr.user_pages)
 668                                 flush_dcache_page(sg_page(host->pio.sg));
 669
 670                         if (!--host->pio.sg_len) {
 671                                 memset(&host->pio, 0, sizeof(host->pio));
 672                                 break;
 673                         }
 674
 675                         /* Advance to next sg */
 676                         host->pio.sg++;
 677                         host->pio.sg_off = 0;
 678                 }
 679
 680                 status = msmsdcc_readl(host, MMCISTATUS);
 681         } while (1);
 682
 683         if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
 684                 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
 685
 686         if (!host->curr.xfer_remain)
 687                 msmsdcc_writel(host, 0, MMCIMASK1);
 688
 689         return IRQ_HANDLED;
 690 }
 691
 692 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
 693 {
 694         struct mmc_command *cmd = host->curr.cmd;
 695
 696         host->curr.cmd = NULL;
 697         cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
 698         cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
 699         cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
 700         cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
 701
 702         if (status & MCI_CMDTIMEOUT) {
 703                 cmd->error = -ETIMEDOUT;
 704         } else if (status & MCI_CMDCRCFAIL &&
 705                    cmd->flags & MMC_RSP_CRC) {
 706                 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
 707                 cmd->error = -EILSEQ;
 708         }
 709
 710         if (!cmd->data || cmd->error) {
 711                 if (host->curr.data && host->dma.sg)
 712                         msm_dmov_stop_cmd(host->dma.channel,
 713                                           &host->dma.hdr, 0);
 714                 else if (host->curr.data) { /* Non DMA */
 715                         msmsdcc_stop_data(host);
 716                         msmsdcc_request_end(host, cmd->mrq);
 717                 } else /* host->data == NULL */
 718                         msmsdcc_request_end(host, cmd->mrq);
 719         } else if (cmd->data)
 720                 if (!(cmd->data->flags & MMC_DATA_READ))
 721                         msmsdcc_start_data(host, cmd->data,
 722                                                 NULL, 0);
 723 }
 724
 725 static void
 726 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
 727                         void __iomem *base)
 728 {
 729         struct mmc_data *data = host->curr.data;
 730
 731         if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
 732                       MCI_CMDTIMEOUT) && host->curr.cmd) {
 733                 msmsdcc_do_cmdirq(host, status);
 734         }
 735
 736         if (!data)
 737                 return;
 738
 739         /* Check for data errors */
 740         if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
 741                       MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
 742                 msmsdcc_data_err(host, data, status);
 743                 host->curr.data_xfered = 0;
 744                 if (host->dma.sg)
 745                         msm_dmov_stop_cmd(host->dma.channel,
 746                                           &host->dma.hdr, 0);
 747                 else {
 748                         if (host->curr.data)
 749                                 msmsdcc_stop_data(host);
 750                         if (!data->stop)
 751                                 msmsdcc_request_end(host, data->mrq);
 752                         else
 753                                 msmsdcc_start_command(host, data->stop, 0);
 754                 }
 755         }
 756
 757         /* Check for data done */
 758         if (!host->curr.got_dataend && (status & MCI_DATAEND))
 759                 host->curr.got_dataend = 1;
 760
 761         if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
 762                 host->curr.got_datablkend = 1;
 763
 764         /*
 765          * If DMA is still in progress, we complete via the completion handler
 766          */
 767         if (host->curr.got_dataend && host->curr.got_datablkend &&
 768             !host->dma.busy) {
 769                 /*
 770                  * There appears to be an issue in the controller where
 771                  * if you request a small block transfer (< fifo size),
 772                  * you may get your DATAEND/DATABLKEND irq without the
 773                  * PIO data irq.
 774                  *
 775                  * Check to see if there is still data to be read,
 776                  * and simulate a PIO irq.
 777                  */
 778                 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
 779                         msmsdcc_pio_irq(1, host);
 780
 781                 msmsdcc_stop_data(host);
 782                 if (!data->error)
 783                         host->curr.data_xfered = host->curr.xfer_size;
 784
 785                 if (!data->stop)
 786                         msmsdcc_request_end(host, data->mrq);
 787                 else
 788                         msmsdcc_start_command(host, data->stop, 0);
 789         }
 790 }
 791
 792 static irqreturn_t
 793 msmsdcc_irq(int irq, void *dev_id)
 794 {
 795         struct msmsdcc_host     *host = dev_id;
 796         void __iomem            *base = host->base;
 797         u32                     status;
 798         int                     ret = 0;
 799         int                     cardint = 0;
 800
 801         spin_lock(&host->lock);
 802
 803         do {
 804                 struct mmc_data *data;
 805                 status = msmsdcc_readl(host, MMCISTATUS);
 806                 status &= (msmsdcc_readl(host, MMCIMASK0) |
 807                                               MCI_DATABLOCKENDMASK);
 808                 msmsdcc_writel(host, status, MMCICLEAR);
 809
 810                 if (status & MCI_SDIOINTR)
 811                         status &= ~MCI_SDIOINTR;
 812
 813                 if (!status)
 814                         break;
 815
 816                 msmsdcc_handle_irq_data(host, status, base);
 817
 818                 if (status & MCI_SDIOINTOPER) {
 819                         cardint = 1;
 820                         status &= ~MCI_SDIOINTOPER;
 821                 }
 822                 ret = 1;
 823         } while (status);
 824
 825         spin_unlock(&host->lock);
 826
 827         /*
 828          * We have to delay handling the card interrupt as it calls
 829          * back into the driver.
 830          */
 831         if (cardint)
 832                 mmc_signal_sdio_irq(host->mmc);
 833
 834         return IRQ_RETVAL(ret);
 835 }
 836
 837 static void
 838 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 839 {
 840         struct msmsdcc_host *host = mmc_priv(mmc);
 841         unsigned long flags;
 842
 843         WARN_ON(host->curr.mrq != NULL);
 844         WARN_ON(host->pwr == 0);
 845
 846         spin_lock_irqsave(&host->lock, flags);
 847
 848         host->stats.reqs++;
 849
 850         if (host->eject) {
 851                 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
 852                         mrq->cmd->error = 0;
 853                         mrq->data->bytes_xfered = mrq->data->blksz *
 854                                                   mrq->data->blocks;
 855                 } else
 856                         mrq->cmd->error = -ENOMEDIUM;
 857
 858                 spin_unlock_irqrestore(&host->lock, flags);
 859                 mmc_request_done(mmc, mrq);
 860                 return;
 861         }
 862
 863         msmsdcc_enable_clocks(host);
 864
 865         host->curr.mrq = mrq;
 866
 867         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 868                 /* Queue/read data, daisy-chain command when data starts */
 869                 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
 870         else
 871                 msmsdcc_start_command(host, mrq->cmd, 0);
 872
 873         if (host->cmdpoll && !msmsdcc_spin_on_status(host,
 874                                 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
 875                                 CMD_SPINMAX)) {
 876                 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
 877                 msmsdcc_do_cmdirq(host, status);
 878                 msmsdcc_writel(host,
 879                                MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
 880                                MMCICLEAR);
 881                 host->stats.cmdpoll_hits++;
 882         } else {
 883                 host->stats.cmdpoll_misses++;
 884         }
 885         spin_unlock_irqrestore(&host->lock, flags);
 886 }
 887
 888 static void
 889 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 890 {
 891         struct msmsdcc_host *host = mmc_priv(mmc);
 892         u32 clk = 0, pwr = 0;
 893         int rc;
 894         unsigned long flags;
 895
 896         spin_lock_irqsave(&host->lock, flags);
 897
 898         msmsdcc_enable_clocks(host);
 899
 900         if (ios->clock) {
 901                 if (ios->clock != host->clk_rate) {
 902                         rc = clk_set_rate(host->clk, ios->clock);
 903                         if (rc < 0)
 904                                 pr_err("%s: Error setting clock rate (%d)\n",
 905                                        mmc_hostname(host->mmc), rc);
 906                         else
 907                                 host->clk_rate = ios->clock;
 908                 }
 909                 clk |= MCI_CLK_ENABLE;
 910         }
 911
 912         if (ios->bus_width == MMC_BUS_WIDTH_4)
 913                 clk |= (2 << 10); /* Set WIDEBUS */
 914
 915         if (ios->clock > 400000 && msmsdcc_pwrsave)
 916                 clk |= (1 << 9); /* PWRSAVE */
 917
 918         clk |= (1 << 12); /* FLOW_ENA */
 919         clk |= (1 << 15); /* feedback clock */
 920
 921         if (host->plat->translate_vdd)
 922                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 923
 924         switch (ios->power_mode) {
 925         case MMC_POWER_OFF:
 926                 break;
 927         case MMC_POWER_UP:
 928                 pwr |= MCI_PWR_UP;
 929                 break;
 930         case MMC_POWER_ON:
 931                 pwr |= MCI_PWR_ON;
 932                 break;
 933         }
 934
 935         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 936                 pwr |= MCI_OD;
 937
 938         msmsdcc_writel(host, clk, MMCICLOCK);
 939
 940         if (host->pwr != pwr) {
 941                 host->pwr = pwr;
 942                 msmsdcc_writel(host, pwr, MMCIPOWER);
 943         }
 944 #if BUSCLK_PWRSAVE
 945         msmsdcc_disable_clocks(host, 1);
 946 #endif
 947         spin_unlock_irqrestore(&host->lock, flags);
 948 }
 949
 950 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 951 {
 952         struct msmsdcc_host *host = mmc_priv(mmc);
 953         unsigned long flags;
 954         u32 status;
 955
 956         spin_lock_irqsave(&host->lock, flags);
 957         if (msmsdcc_sdioirq == 1) {
 958                 status = msmsdcc_readl(host, MMCIMASK0);
 959                 if (enable)
 960                         status |= MCI_SDIOINTOPERMASK;
 961                 else
 962                         status &= ~MCI_SDIOINTOPERMASK;
 963                 host->saved_irq0mask = status;
 964                 msmsdcc_writel(host, status, MMCIMASK0);
 965         }
 966         spin_unlock_irqrestore(&host->lock, flags);
 967 }
 968
 969 static const struct mmc_host_ops msmsdcc_ops = {
 970         .request        = msmsdcc_request,
 971         .set_ios        = msmsdcc_set_ios,
 972         .enable_sdio_irq = msmsdcc_enable_sdio_irq,
 973 };
 974
 975 static void
 976 msmsdcc_check_status(unsigned long data)
 977 {
 978         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
 979         unsigned int status;
 980
 981         if (!host->plat->status) {
 982                 mmc_detect_change(host->mmc, 0);
 983                 goto out;
 984         }
 985
 986         status = host->plat->status(mmc_dev(host->mmc));
 987         host->eject = !status;
 988         if (status ^ host->oldstat) {
 989                 pr_info("%s: Slot status change detected (%d -> %d)\n",
 990                         mmc_hostname(host->mmc), host->oldstat, status);
 991                 if (status)
 992                         mmc_detect_change(host->mmc, (5 * HZ) / 2);
 993                 else
 994                         mmc_detect_change(host->mmc, 0);
 995         }
 996
 997         host->oldstat = status;
 998
 999 out:
1000         if (host->timer.function)
1001                 mod_timer(&host->timer, jiffies + HZ);
1002 }
1003
1004 static irqreturn_t
1005 msmsdcc_platform_status_irq(int irq, void *dev_id)
1006 {
1007         struct msmsdcc_host *host = dev_id;
1008
1009         printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1010         msmsdcc_check_status((unsigned long) host);
1011         return IRQ_HANDLED;
1012 }
1013
1014 static void
1015 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1016 {
1017         struct msmsdcc_host *host = dev_id;
1018
1019         printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1020                card_present);
1021         msmsdcc_check_status((unsigned long) host);
1022 }
1023
1024 static void
1025 msmsdcc_busclk_expired(unsigned long _data)
1026 {
1027         struct msmsdcc_host     *host = (struct msmsdcc_host *) _data;
1028
1029         if (host->clks_on)
1030                 msmsdcc_disable_clocks(host, 0);
1031 }
1032
1033 static int
1034 msmsdcc_init_dma(struct msmsdcc_host *host)
1035 {
1036         memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1037         host->dma.host = host;
1038         host->dma.channel = -1;
1039
1040         if (!host->dmares)
1041                 return -ENODEV;
1042
1043         host->dma.nc = dma_alloc_coherent(NULL,
1044                                           sizeof(struct msmsdcc_nc_dmadata),
1045                                           &host->dma.nc_busaddr,
1046                                           GFP_KERNEL);
1047         if (host->dma.nc == NULL) {
1048                 pr_err("Unable to allocate DMA buffer\n");
1049                 return -ENOMEM;
1050         }
1051         memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1052         host->dma.cmd_busaddr = host->dma.nc_busaddr;
1053         host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1054                                 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1055         host->dma.channel = host->dmares->start;
1056
1057         return 0;
1058 }
1059
1060 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1061 static void
1062 do_resume_work(struct work_struct *work)
1063 {
1064         struct msmsdcc_host *host =
1065                 container_of(work, struct msmsdcc_host, resume_task);
1066         struct mmc_host *mmc = host->mmc;
1067
1068         if (mmc) {
1069                 mmc_resume_host(mmc);
1070                 if (host->stat_irq)
1071                         enable_irq(host->stat_irq);
1072         }
1073 }
1074 #endif
1075
1076 static int
1077 msmsdcc_probe(struct platform_device *pdev)
1078 {
1079         struct mmc_platform_data *plat = pdev->dev.platform_data;
1080         struct msmsdcc_host *host;
1081         struct mmc_host *mmc;
1082         struct resource *cmd_irqres = NULL;
1083         struct resource *pio_irqres = NULL;
1084         struct resource *stat_irqres = NULL;
1085         struct resource *memres = NULL;
1086         struct resource *dmares = NULL;
1087         int ret;
1088
1089         /* must have platform data */
1090         if (!plat) {
1091                 pr_err("%s: Platform data not available\n", __func__);
1092                 ret = -EINVAL;
1093                 goto out;
1094         }
1095
1096         if (pdev->id < 1 || pdev->id > 4)
1097                 return -EINVAL;
1098
1099         if (pdev->resource == NULL || pdev->num_resources < 2) {
1100                 pr_err("%s: Invalid resource\n", __func__);
1101                 return -ENXIO;
1102         }
1103
1104         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105         dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1106         cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1107                                                   "cmd_irq");
1108         pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1109                                                   "pio_irq");
1110         stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1111                                                    "status_irq");
1112
1113         if (!cmd_irqres || !pio_irqres || !memres) {
1114                 pr_err("%s: Invalid resource\n", __func__);
1115                 return -ENXIO;
1116         }
1117
1118         /*
1119          * Setup our host structure
1120          */
1121
1122         mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1123         if (!mmc) {
1124                 ret = -ENOMEM;
1125                 goto out;
1126         }
1127
1128         host = mmc_priv(mmc);
1129         host->pdev_id = pdev->id;
1130         host->plat = plat;
1131         host->mmc = mmc;
1132         host->curr.cmd = NULL;
1133
1134         host->cmdpoll = 1;
1135
1136         host->base = ioremap(memres->start, PAGE_SIZE);
1137         if (!host->base) {
1138                 ret = -ENOMEM;
1139                 goto out;
1140         }
1141
1142         host->cmd_irqres = cmd_irqres;
1143         host->pio_irqres = pio_irqres;
1144         host->memres = memres;
1145         host->dmares = dmares;
1146         spin_lock_init(&host->lock);
1147
1148         /*
1149          * Setup DMA
1150          */
1151         msmsdcc_init_dma(host);
1152
1153         /* Get our clocks */
1154         host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1155         if (IS_ERR(host->pclk)) {
1156                 ret = PTR_ERR(host->pclk);
1157                 goto host_free;
1158         }
1159
1160         host->clk = clk_get(&pdev->dev, "sdc_clk");
1161         if (IS_ERR(host->clk)) {
1162                 ret = PTR_ERR(host->clk);
1163                 goto pclk_put;
1164         }
1165
1166         /* Enable clocks */
1167         ret = msmsdcc_enable_clocks(host);
1168         if (ret)
1169                 goto clk_put;
1170
1171         ret = clk_set_rate(host->clk, msmsdcc_fmin);
1172         if (ret) {
1173                 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1174                 goto clk_disable;
1175         }
1176
1177         host->pclk_rate = clk_get_rate(host->pclk);
1178         host->clk_rate = clk_get_rate(host->clk);
1179
1180         /*
1181          * Setup MMC host structure
1182          */
1183         mmc->ops = &msmsdcc_ops;
1184         mmc->f_min = msmsdcc_fmin;
1185         mmc->f_max = msmsdcc_fmax;
1186         mmc->ocr_avail = plat->ocr_mask;
1187
1188         if (msmsdcc_4bit)
1189                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1190         if (msmsdcc_sdioirq)
1191                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1192         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1193
1194         mmc->max_phys_segs = NR_SG;
1195         mmc->max_hw_segs = NR_SG;
1196         mmc->max_blk_size = 4096;       /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1197         mmc->max_blk_count = 65536;
1198
1199         mmc->max_req_size = 33554432;   /* MCI_DATA_LENGTH is 25 bits */
1200         mmc->max_seg_size = mmc->max_req_size;
1201
1202         msmsdcc_writel(host, 0, MMCIMASK0);
1203         msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1204
1205         msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1206         host->saved_irq0mask = MCI_IRQENABLE;
1207
1208         /*
1209          * Setup card detect change
1210          */
1211
1212         memset(&host->timer, 0, sizeof(host->timer));
1213
1214         if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1215                 unsigned long irqflags = IRQF_SHARED |
1216                         (stat_irqres->flags & IRQF_TRIGGER_MASK);
1217
1218                 host->stat_irq = stat_irqres->start;
1219                 ret = request_irq(host->stat_irq,
1220                                   msmsdcc_platform_status_irq,
1221                                   irqflags,
1222                                   DRIVER_NAME " (slot)",
1223                                   host);
1224                 if (ret) {
1225                         pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1226                                mmc_hostname(mmc), host->stat_irq, ret);
1227                         goto clk_disable;
1228                 }
1229         } else if (plat->register_status_notify) {
1230                 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1231         } else if (!plat->status)
1232                 pr_err("%s: No card detect facilities available\n",
1233                        mmc_hostname(mmc));
1234         else {
1235                 init_timer(&host->timer);
1236                 host->timer.data = (unsigned long)host;
1237                 host->timer.function = msmsdcc_check_status;
1238                 host->timer.expires = jiffies + HZ;
1239                 add_timer(&host->timer);
1240         }
1241
1242         if (plat->status) {
1243                 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1244                 host->eject = !host->oldstat;
1245         }
1246
1247         init_timer(&host->busclk_timer);
1248         host->busclk_timer.data = (unsigned long) host;
1249         host->busclk_timer.function = msmsdcc_busclk_expired;
1250
1251         ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1252                           DRIVER_NAME " (cmd)", host);
1253         if (ret)
1254                 goto stat_irq_free;
1255
1256         ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1257                           DRIVER_NAME " (pio)", host);
1258         if (ret)
1259                 goto cmd_irq_free;
1260
1261         mmc_set_drvdata(pdev, mmc);
1262         mmc_add_host(mmc);
1263
1264         pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1265                 mmc_hostname(mmc), (unsigned long long)memres->start,
1266                 (unsigned int) cmd_irqres->start,
1267                 (unsigned int) host->stat_irq, host->dma.channel);
1268         pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1269                 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1270         pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1271                 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1272         pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1273         pr_info("%s: Power save feature enable = %d\n",
1274                 mmc_hostname(mmc), msmsdcc_pwrsave);
1275
1276         if (host->dma.channel != -1) {
1277                 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1278                         mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1279                 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1280                         mmc_hostname(mmc), host->dma.cmd_busaddr,
1281                         host->dma.cmdptr_busaddr);
1282         } else
1283                 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1284         if (host->timer.function)
1285                 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1286
1287 #if BUSCLK_PWRSAVE
1288         msmsdcc_disable_clocks(host, 1);
1289 #endif
1290         return 0;
1291  cmd_irq_free:
1292         free_irq(cmd_irqres->start, host);
1293  stat_irq_free:
1294         if (host->stat_irq)
1295                 free_irq(host->stat_irq, host);
1296  clk_disable:
1297         msmsdcc_disable_clocks(host, 0);
1298  clk_put:
1299         clk_put(host->clk);
1300  pclk_put:
1301         clk_put(host->pclk);
1302  host_free:
1303         mmc_free_host(mmc);
1304  out:
1305         return ret;
1306 }
1307
1308 static int
1309 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1310 {
1311         struct mmc_host *mmc = mmc_get_drvdata(dev);
1312         int rc = 0;
1313
1314         if (mmc) {
1315                 struct msmsdcc_host *host = mmc_priv(mmc);
1316
1317                 if (host->stat_irq)
1318                         disable_irq(host->stat_irq);
1319
1320                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1321                         rc = mmc_suspend_host(mmc, state);
1322                 if (!rc)
1323                         msmsdcc_writel(host, 0, MMCIMASK0);
1324                 if (host->clks_on)
1325                         msmsdcc_disable_clocks(host, 0);
1326         }
1327         return rc;
1328 }
1329
1330 static int
1331 msmsdcc_resume(struct platform_device *dev)
1332 {
1333         struct mmc_host *mmc = mmc_get_drvdata(dev);
1334
1335         if (mmc) {
1336                 struct msmsdcc_host *host = mmc_priv(mmc);
1337
1338                 msmsdcc_enable_clocks(host);
1339
1340                 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1341
1342                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1343                         mmc_resume_host(mmc);
1344                 if (host->stat_irq)
1345                         enable_irq(host->stat_irq);
1346 #if BUSCLK_PWRSAVE
1347                 msmsdcc_disable_clocks(host, 1);
1348 #endif
1349         }
1350         return 0;
1351 }
1352
1353 static struct platform_driver msmsdcc_driver = {
1354         .probe          = msmsdcc_probe,
1355         .suspend        = msmsdcc_suspend,
1356         .resume         = msmsdcc_resume,
1357         .driver         = {
1358                 .name   = "msm_sdcc",
1359         },
1360 };
1361
1362 static int __init msmsdcc_init(void)
1363 {
1364         return platform_driver_register(&msmsdcc_driver);
1365 }
1366
1367 static void __exit msmsdcc_exit(void)
1368 {
1369         platform_driver_unregister(&msmsdcc_driver);
1370 }
1371
1372 module_init(msmsdcc_init);
1373 module_exit(msmsdcc_exit);
1374
1375 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1376 MODULE_LICENSE("GPL");