drivers/mmc/host/msm_sdcc.c

   1 /*
   2  *  linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
   3  *
   4  *  Copyright (C) 2007 Google Inc,
   5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Based on mmci.c
  12  *
  13  * Author: San Mehat (san@android.com)
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/moduleparam.h>
  19 #include <linux/init.h>
  20 #include <linux/ioport.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/highmem.h>
  26 #include <linux/log2.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/mmc/card.h>
  29 #include <linux/clk.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/debugfs.h>
  34 #include <linux/io.h>
  35 #include <linux/memory.h>
  36
  37 #include <asm/cacheflush.h>
  38 #include <asm/div64.h>
  39 #include <asm/sizes.h>
  40
  41 #include <mach/mmc.h>
  42 #include <mach/msm_iomap.h>
  43 #include <mach/dma.h>
  44
  45 #include "msm_sdcc.h"
  46
  47 #define DRIVER_NAME "msm-sdcc"
  48
  49 static unsigned int msmsdcc_fmin = 144000;
  50 static unsigned int msmsdcc_fmax = 50000000;
  51 static unsigned int msmsdcc_4bit = 1;
  52 static unsigned int msmsdcc_pwrsave = 1;
  53 static unsigned int msmsdcc_piopoll = 1;
  54 static unsigned int msmsdcc_sdioirq;
  55
  56 #define PIO_SPINMAX 30
  57 #define CMD_SPINMAX 20
  58
  59 static void
  60 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
  61                       u32 c);
  62
  63 static void
  64 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
  65 {
  66         writel(0, host->base + MMCICOMMAND);
  67
  68         BUG_ON(host->curr.data);
  69
  70         host->curr.mrq = NULL;
  71         host->curr.cmd = NULL;
  72
  73         if (mrq->data)
  74                 mrq->data->bytes_xfered = host->curr.data_xfered;
  75         if (mrq->cmd->error == -ETIMEDOUT)
  76                 mdelay(5);
  77
  78         /*
  79          * Need to drop the host lock here; mmc_request_done may call
  80          * back into the driver...
  81          */
  82         spin_unlock(&host->lock);
  83         mmc_request_done(host->mmc, mrq);
  84         spin_lock(&host->lock);
  85 }
  86
  87 static void
  88 msmsdcc_stop_data(struct msmsdcc_host *host)
  89 {
  90         writel(0, host->base + MMCIDATACTRL);
  91         host->curr.data = NULL;
  92         host->curr.got_dataend = host->curr.got_datablkend = 0;
  93 }
  94
  95 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
  96 {
  97         switch (host->pdev_id) {
  98         case 1:
  99                 return MSM_SDC1_PHYS + MMCIFIFO;
 100         case 2:
 101                 return MSM_SDC2_PHYS + MMCIFIFO;
 102         case 3:
 103                 return MSM_SDC3_PHYS + MMCIFIFO;
 104         case 4:
 105                 return MSM_SDC4_PHYS + MMCIFIFO;
 106         }
 107         BUG();
 108         return 0;
 109 }
 110
 111 static void
 112 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
 113                           unsigned int result,
 114                           struct msm_dmov_errdata *err)
 115 {
 116         struct msmsdcc_dma_data *dma_data =
 117                 container_of(cmd, struct msmsdcc_dma_data, hdr);
 118         struct msmsdcc_host     *host = dma_data->host;
 119         unsigned long           flags;
 120         struct mmc_request      *mrq;
 121
 122         spin_lock_irqsave(&host->lock, flags);
 123         mrq = host->curr.mrq;
 124         BUG_ON(!mrq);
 125
 126         if (!(result & DMOV_RSLT_VALID)) {
 127                 pr_err("msmsdcc: Invalid DataMover result\n");
 128                 goto out;
 129         }
 130
 131         if (result & DMOV_RSLT_DONE) {
 132                 host->curr.data_xfered = host->curr.xfer_size;
 133         } else {
 134                 /* Error or flush  */
 135                 if (result & DMOV_RSLT_ERROR)
 136                         pr_err("%s: DMA error (0x%.8x)\n",
 137                                mmc_hostname(host->mmc), result);
 138                 if (result & DMOV_RSLT_FLUSH)
 139                         pr_err("%s: DMA channel flushed (0x%.8x)\n",
 140                                mmc_hostname(host->mmc), result);
 141                 if (err)
 142                         pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
 143                                err->flush[0], err->flush[1], err->flush[2],
 144                                err->flush[3], err->flush[4], err->flush[5]);
 145                 if (!mrq->data->error)
 146                         mrq->data->error = -EIO;
 147         }
 148         host->dma.busy = 0;
 149         dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
 150                      host->dma.dir);
 151
 152         if (host->curr.user_pages) {
 153                 struct scatterlist *sg = host->dma.sg;
 154                 int i;
 155
 156                 for (i = 0; i < host->dma.num_ents; i++)
 157                         flush_dcache_page(sg_page(sg++));
 158         }
 159
 160         host->dma.sg = NULL;
 161
 162         if ((host->curr.got_dataend && host->curr.got_datablkend)
 163              || mrq->data->error) {
 164
 165                 /*
 166                  * If we've already gotten our DATAEND / DATABLKEND
 167                  * for this request, then complete it through here.
 168                  */
 169                 msmsdcc_stop_data(host);
 170
 171                 if (!mrq->data->error)
 172                         host->curr.data_xfered = host->curr.xfer_size;
 173                 if (!mrq->data->stop || mrq->cmd->error) {
 174                         writel(0, host->base + MMCICOMMAND);
 175                         host->curr.mrq = NULL;
 176                         host->curr.cmd = NULL;
 177                         mrq->data->bytes_xfered = host->curr.data_xfered;
 178
 179                         spin_unlock_irqrestore(&host->lock, flags);
 180                         mmc_request_done(host->mmc, mrq);
 181                         return;
 182                 } else
 183                         msmsdcc_start_command(host, mrq->data->stop, 0);
 184         }
 185
 186 out:
 187         spin_unlock_irqrestore(&host->lock, flags);
 188         return;
 189 }
 190
 191 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
 192 {
 193         if (host->dma.channel == -1)
 194                 return -ENOENT;
 195
 196         if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
 197                 return -EINVAL;
 198         if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
 199                 return -EINVAL;
 200         return 0;
 201 }
 202
 203 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
 204 {
 205         struct msmsdcc_nc_dmadata *nc;
 206         dmov_box *box;
 207         uint32_t rows;
 208         uint32_t crci;
 209         unsigned int n;
 210         int i, rc;
 211         struct scatterlist *sg = data->sg;
 212
 213         rc = validate_dma(host, data);
 214         if (rc)
 215                 return rc;
 216
 217         host->dma.sg = data->sg;
 218         host->dma.num_ents = data->sg_len;
 219
 220         nc = host->dma.nc;
 221
 222         switch (host->pdev_id) {
 223         case 1:
 224                 crci = MSMSDCC_CRCI_SDC1;
 225                 break;
 226         case 2:
 227                 crci = MSMSDCC_CRCI_SDC2;
 228                 break;
 229         case 3:
 230                 crci = MSMSDCC_CRCI_SDC3;
 231                 break;
 232         case 4:
 233                 crci = MSMSDCC_CRCI_SDC4;
 234                 break;
 235         default:
 236                 host->dma.sg = NULL;
 237                 host->dma.num_ents = 0;
 238                 return -ENOENT;
 239         }
 240
 241         if (data->flags & MMC_DATA_READ)
 242                 host->dma.dir = DMA_FROM_DEVICE;
 243         else
 244                 host->dma.dir = DMA_TO_DEVICE;
 245
 246         host->curr.user_pages = 0;
 247
 248         n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
 249                        host->dma.num_ents, host->dma.dir);
 250
 251         if (n != host->dma.num_ents) {
 252                 pr_err("%s: Unable to map in all sg elements\n",
 253                        mmc_hostname(host->mmc));
 254                 host->dma.sg = NULL;
 255                 host->dma.num_ents = 0;
 256                 return -ENOMEM;
 257         }
 258
 259         box = &nc->cmd[0];
 260         for (i = 0; i < host->dma.num_ents; i++) {
 261                 box->cmd = CMD_MODE_BOX;
 262
 263                 if (i == (host->dma.num_ents - 1))
 264                         box->cmd |= CMD_LC;
 265                 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
 266                         (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
 267                         (sg_dma_len(sg) / MCI_FIFOSIZE) ;
 268
 269                 if (data->flags & MMC_DATA_READ) {
 270                         box->src_row_addr = msmsdcc_fifo_addr(host);
 271                         box->dst_row_addr = sg_dma_address(sg);
 272
 273                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 274                                            (MCI_FIFOSIZE);
 275                         box->row_offset = MCI_FIFOSIZE;
 276
 277                         box->num_rows = rows * ((1 << 16) + 1);
 278                         box->cmd |= CMD_SRC_CRCI(crci);
 279                 } else {
 280                         box->src_row_addr = sg_dma_address(sg);
 281                         box->dst_row_addr = msmsdcc_fifo_addr(host);
 282
 283                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 284                                            (MCI_FIFOSIZE);
 285                         box->row_offset = (MCI_FIFOSIZE << 16);
 286
 287                         box->num_rows = rows * ((1 << 16) + 1);
 288                         box->cmd |= CMD_DST_CRCI(crci);
 289                 }
 290                 box++;
 291                 sg++;
 292         }
 293
 294         /* location of command block must be 64 bit aligned */
 295         BUG_ON(host->dma.cmd_busaddr & 0x07);
 296
 297         nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
 298         host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
 299                                DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
 300         host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
 301
 302         return 0;
 303 }
 304
 305 static void
 306 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
 307 {
 308         unsigned int datactrl, timeout;
 309         unsigned long long clks;
 310         void __iomem *base = host->base;
 311         unsigned int pio_irqmask = 0;
 312
 313         host->curr.data = data;
 314         host->curr.xfer_size = data->blksz * data->blocks;
 315         host->curr.xfer_remain = host->curr.xfer_size;
 316         host->curr.data_xfered = 0;
 317         host->curr.got_dataend = 0;
 318         host->curr.got_datablkend = 0;
 319
 320         memset(&host->pio, 0, sizeof(host->pio));
 321
 322         clks = (unsigned long long)data->timeout_ns * host->clk_rate;
 323         do_div(clks, NSEC_PER_SEC);
 324         timeout = data->timeout_clks + (unsigned int)clks;
 325         writel(timeout, base + MMCIDATATIMER);
 326
 327         writel(host->curr.xfer_size, base + MMCIDATALENGTH);
 328
 329         datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
 330
 331         if (!msmsdcc_config_dma(host, data))
 332                 datactrl |= MCI_DPSM_DMAENABLE;
 333         else {
 334                 host->pio.sg = data->sg;
 335                 host->pio.sg_len = data->sg_len;
 336                 host->pio.sg_off = 0;
 337
 338                 if (data->flags & MMC_DATA_READ) {
 339                         pio_irqmask = MCI_RXFIFOHALFFULLMASK;
 340                         if (host->curr.xfer_remain < MCI_FIFOSIZE)
 341                                 pio_irqmask |= MCI_RXDATAAVLBLMASK;
 342                 } else
 343                         pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
 344         }
 345
 346         if (data->flags & MMC_DATA_READ)
 347                 datactrl |= MCI_DPSM_DIRECTION;
 348
 349         writel(pio_irqmask, base + MMCIMASK1);
 350         writel(datactrl, base + MMCIDATACTRL);
 351
 352         if (datactrl & MCI_DPSM_DMAENABLE) {
 353                 host->dma.busy = 1;
 354                 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
 355         }
 356 }
 357
 358 static void
 359 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
 360 {
 361         void __iomem *base = host->base;
 362
 363         if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
 364                 writel(0, base + MMCICOMMAND);
 365                 udelay(2 + ((5 * 1000000) / host->clk_rate));
 366         }
 367
 368         c |= cmd->opcode | MCI_CPSM_ENABLE;
 369
 370         if (cmd->flags & MMC_RSP_PRESENT) {
 371                 if (cmd->flags & MMC_RSP_136)
 372                         c |= MCI_CPSM_LONGRSP;
 373                 c |= MCI_CPSM_RESPONSE;
 374         }
 375
 376         if (cmd->opcode == 17 || cmd->opcode == 18 ||
 377             cmd->opcode == 24 || cmd->opcode == 25 ||
 378             cmd->opcode == 53)
 379                 c |= MCI_CSPM_DATCMD;
 380
 381         if (cmd == cmd->mrq->stop)
 382                 c |= MCI_CSPM_MCIABORT;
 383
 384         host->curr.cmd = cmd;
 385
 386         host->stats.cmds++;
 387
 388         writel(cmd->arg, base + MMCIARGUMENT);
 389         writel(c, base + MMCICOMMAND);
 390 }
 391
 392 static void
 393 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
 394                  unsigned int status)
 395 {
 396         if (status & MCI_DATACRCFAIL) {
 397                 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
 398                 pr_err("%s: opcode 0x%.8x\n", __func__,
 399                        data->mrq->cmd->opcode);
 400                 pr_err("%s: blksz %d, blocks %d\n", __func__,
 401                        data->blksz, data->blocks);
 402                 data->error = -EILSEQ;
 403         } else if (status & MCI_DATATIMEOUT) {
 404                 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
 405                 data->error = -ETIMEDOUT;
 406         } else if (status & MCI_RXOVERRUN) {
 407                 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
 408                 data->error = -EIO;
 409         } else if (status & MCI_TXUNDERRUN) {
 410                 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
 411                 data->error = -EIO;
 412         } else {
 413                 pr_err("%s: Unknown error (0x%.8x)\n",
 414                        mmc_hostname(host->mmc), status);
 415                 data->error = -EIO;
 416         }
 417 }
 418
 419
 420 static int
 421 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
 422 {
 423         void __iomem    *base = host->base;
 424         uint32_t        *ptr = (uint32_t *) buffer;
 425         int             count = 0;
 426
 427         while (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) {
 428
 429                 *ptr = readl(base + MMCIFIFO + (count % MCI_FIFOSIZE));
 430                 ptr++;
 431                 count += sizeof(uint32_t);
 432
 433                 remain -=  sizeof(uint32_t);
 434                 if (remain == 0)
 435                         break;
 436         }
 437         return count;
 438 }
 439
 440 static int
 441 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
 442                   unsigned int remain, u32 status)
 443 {
 444         void __iomem *base = host->base;
 445         char *ptr = buffer;
 446
 447         do {
 448                 unsigned int count, maxcnt;
 449
 450                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
 451                                                     MCI_FIFOHALFSIZE;
 452                 count = min(remain, maxcnt);
 453
 454                 writesl(base + MMCIFIFO, ptr, count >> 2);
 455                 ptr += count;
 456                 remain -= count;
 457
 458                 if (remain == 0)
 459                         break;
 460
 461                 status = readl(base + MMCISTATUS);
 462         } while (status & MCI_TXFIFOHALFEMPTY);
 463
 464         return ptr - buffer;
 465 }
 466
 467 static int
 468 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
 469 {
 470         while (maxspin) {
 471                 if ((readl(host->base + MMCISTATUS) & mask))
 472                         return 0;
 473                 udelay(1);
 474                 --maxspin;
 475         }
 476         return -ETIMEDOUT;
 477 }
 478
 479 static int
 480 msmsdcc_pio_irq(int irq, void *dev_id)
 481 {
 482         struct msmsdcc_host     *host = dev_id;
 483         void __iomem            *base = host->base;
 484         uint32_t                status;
 485
 486         status = readl(base + MMCISTATUS);
 487
 488         do {
 489                 unsigned long flags;
 490                 unsigned int remain, len;
 491                 char *buffer;
 492
 493                 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
 494                         if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
 495                                 break;
 496
 497                         if (msmsdcc_spin_on_status(host,
 498                                                    (MCI_TXFIFOHALFEMPTY |
 499                                                    MCI_RXDATAAVLBL),
 500                                                    PIO_SPINMAX)) {
 501                                 break;
 502                         }
 503                 }
 504
 505                 /* Map the current scatter buffer */
 506                 local_irq_save(flags);
 507                 buffer = kmap_atomic(sg_page(host->pio.sg),
 508                                      KM_BIO_SRC_IRQ) + host->pio.sg->offset;
 509                 buffer += host->pio.sg_off;
 510                 remain = host->pio.sg->length - host->pio.sg_off;
 511                 len = 0;
 512                 if (status & MCI_RXACTIVE)
 513                         len = msmsdcc_pio_read(host, buffer, remain);
 514                 if (status & MCI_TXACTIVE)
 515                         len = msmsdcc_pio_write(host, buffer, remain, status);
 516
 517                 /* Unmap the buffer */
 518                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 519                 local_irq_restore(flags);
 520
 521                 host->pio.sg_off += len;
 522                 host->curr.xfer_remain -= len;
 523                 host->curr.data_xfered += len;
 524                 remain -= len;
 525
 526                 if (remain == 0) {
 527                         /* This sg page is full - do some housekeeping */
 528                         if (status & MCI_RXACTIVE && host->curr.user_pages)
 529                                 flush_dcache_page(sg_page(host->pio.sg));
 530
 531                         if (!--host->pio.sg_len) {
 532                                 memset(&host->pio, 0, sizeof(host->pio));
 533                                 break;
 534                         }
 535
 536                         /* Advance to next sg */
 537                         host->pio.sg++;
 538                         host->pio.sg_off = 0;
 539                 }
 540
 541                 status = readl(base + MMCISTATUS);
 542         } while (1);
 543
 544         if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
 545                 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
 546
 547         if (!host->curr.xfer_remain)
 548                 writel(0, base + MMCIMASK1);
 549
 550         return IRQ_HANDLED;
 551 }
 552
 553 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
 554 {
 555         struct mmc_command *cmd = host->curr.cmd;
 556         void __iomem       *base = host->base;
 557
 558         host->curr.cmd = NULL;
 559         cmd->resp[0] = readl(base + MMCIRESPONSE0);
 560         cmd->resp[1] = readl(base + MMCIRESPONSE1);
 561         cmd->resp[2] = readl(base + MMCIRESPONSE2);
 562         cmd->resp[3] = readl(base + MMCIRESPONSE3);
 563
 564         del_timer(&host->command_timer);
 565         if (status & MCI_CMDTIMEOUT) {
 566                 cmd->error = -ETIMEDOUT;
 567         } else if (status & MCI_CMDCRCFAIL &&
 568                    cmd->flags & MMC_RSP_CRC) {
 569                 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
 570                 cmd->error = -EILSEQ;
 571         }
 572
 573         if (!cmd->data || cmd->error) {
 574                 if (host->curr.data && host->dma.sg)
 575                         msm_dmov_stop_cmd(host->dma.channel,
 576                                           &host->dma.hdr, 0);
 577                 else if (host->curr.data) { /* Non DMA */
 578                         msmsdcc_stop_data(host);
 579                         msmsdcc_request_end(host, cmd->mrq);
 580                 } else /* host->data == NULL */
 581                         msmsdcc_request_end(host, cmd->mrq);
 582         } else if (!(cmd->data->flags & MMC_DATA_READ))
 583                 msmsdcc_start_data(host, cmd->data);
 584 }
 585
 586 static void
 587 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
 588                         void __iomem *base)
 589 {
 590         struct mmc_data *data = host->curr.data;
 591
 592         if (!data)
 593                 return;
 594
 595         /* Check for data errors */
 596         if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
 597                       MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
 598                 msmsdcc_data_err(host, data, status);
 599                 host->curr.data_xfered = 0;
 600                 if (host->dma.sg)
 601                         msm_dmov_stop_cmd(host->dma.channel,
 602                                           &host->dma.hdr, 0);
 603                 else {
 604                         msmsdcc_stop_data(host);
 605                         if (!data->stop)
 606                                 msmsdcc_request_end(host, data->mrq);
 607                         else
 608                                 msmsdcc_start_command(host, data->stop, 0);
 609                 }
 610         }
 611
 612         /* Check for data done */
 613         if (!host->curr.got_dataend && (status & MCI_DATAEND))
 614                 host->curr.got_dataend = 1;
 615
 616         if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
 617                 host->curr.got_datablkend = 1;
 618
 619         /*
 620          * If DMA is still in progress, we complete via the completion handler
 621          */
 622         if (host->curr.got_dataend && host->curr.got_datablkend &&
 623             !host->dma.busy) {
 624                 /*
 625                  * There appears to be an issue in the controller where
 626                  * if you request a small block transfer (< fifo size),
 627                  * you may get your DATAEND/DATABLKEND irq without the
 628                  * PIO data irq.
 629                  *
 630                  * Check to see if there is still data to be read,
 631                  * and simulate a PIO irq.
 632                  */
 633                 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
 634                         msmsdcc_pio_irq(1, host);
 635
 636                 msmsdcc_stop_data(host);
 637                 if (!data->error)
 638                         host->curr.data_xfered = host->curr.xfer_size;
 639
 640                 if (!data->stop)
 641                         msmsdcc_request_end(host, data->mrq);
 642                 else
 643                         msmsdcc_start_command(host, data->stop, 0);
 644         }
 645 }
 646
 647 static irqreturn_t
 648 msmsdcc_irq(int irq, void *dev_id)
 649 {
 650         struct msmsdcc_host     *host = dev_id;
 651         void __iomem            *base = host->base;
 652         u32                     status;
 653         int                     ret = 0;
 654         int                     cardint = 0;
 655
 656         spin_lock(&host->lock);
 657
 658         do {
 659                 status = readl(base + MMCISTATUS);
 660
 661                 status &= (readl(base + MMCIMASK0) | MCI_DATABLOCKENDMASK);
 662                 writel(status, base + MMCICLEAR);
 663
 664                 msmsdcc_handle_irq_data(host, status, base);
 665
 666                 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
 667                               MCI_CMDTIMEOUT) && host->curr.cmd) {
 668                         msmsdcc_do_cmdirq(host, status);
 669                 }
 670
 671                 if (status & MCI_SDIOINTOPER) {
 672                         cardint = 1;
 673                         status &= ~MCI_SDIOINTOPER;
 674                 }
 675                 ret = 1;
 676         } while (status);
 677
 678         spin_unlock(&host->lock);
 679
 680         /*
 681          * We have to delay handling the card interrupt as it calls
 682          * back into the driver.
 683          */
 684         if (cardint)
 685                 mmc_signal_sdio_irq(host->mmc);
 686
 687         return IRQ_RETVAL(ret);
 688 }
 689
 690 static void
 691 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 692 {
 693         struct msmsdcc_host *host = mmc_priv(mmc);
 694         unsigned long flags;
 695
 696         WARN_ON(host->curr.mrq != NULL);
 697         WARN_ON(host->pwr == 0);
 698
 699         spin_lock_irqsave(&host->lock, flags);
 700
 701         host->stats.reqs++;
 702
 703         if (host->eject) {
 704                 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
 705                         mrq->cmd->error = 0;
 706                         mrq->data->bytes_xfered = mrq->data->blksz *
 707                                                   mrq->data->blocks;
 708                 } else
 709                         mrq->cmd->error = -ENOMEDIUM;
 710
 711                 spin_unlock_irqrestore(&host->lock, flags);
 712                 mmc_request_done(mmc, mrq);
 713                 return;
 714         }
 715
 716         host->curr.mrq = mrq;
 717
 718         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 719                 msmsdcc_start_data(host, mrq->data);
 720
 721         msmsdcc_start_command(host, mrq->cmd, 0);
 722
 723         if (host->cmdpoll && !msmsdcc_spin_on_status(host,
 724                                 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
 725                                 CMD_SPINMAX)) {
 726                 uint32_t status = readl(host->base + MMCISTATUS);
 727                 msmsdcc_do_cmdirq(host, status);
 728                 writel(MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
 729                        host->base + MMCICLEAR);
 730                 host->stats.cmdpoll_hits++;
 731         } else {
 732                 host->stats.cmdpoll_misses++;
 733                 mod_timer(&host->command_timer, jiffies + HZ);
 734         }
 735         spin_unlock_irqrestore(&host->lock, flags);
 736 }
 737
 738 static int inline
 739 msmsdcc_enable_clocks(struct msmsdcc_host *host, int enable)
 740 {
 741         int rc;
 742         if (enable) {
 743                 rc = clk_enable(host->pclk);
 744                 if (rc)
 745                         return rc;
 746                 rc = clk_enable(host->clk);
 747                 if (rc) {
 748                         clk_disable(host->pclk);
 749                         return rc;
 750                 }
 751                 host->clks_on = 1;
 752                 udelay(10);
 753         } else {
 754                 clk_disable(host->clk);
 755                 clk_disable(host->pclk);
 756                 host->clks_on = 0;
 757         }
 758         return 0;
 759 }
 760
 761 static void
 762 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 763 {
 764         struct msmsdcc_host *host = mmc_priv(mmc);
 765         u32 clk = 0, pwr = 0;
 766         int rc;
 767         unsigned long flags;
 768
 769         spin_lock_irqsave(&host->lock, flags);
 770         if (ios->clock) {
 771
 772                 if (!host->clks_on)
 773                         msmsdcc_enable_clocks(host, 1);
 774                 if (ios->clock != host->clk_rate) {
 775                         rc = clk_set_rate(host->clk, ios->clock);
 776                         if (rc < 0)
 777                                 pr_err("%s: Error setting clock rate (%d)\n",
 778                                        mmc_hostname(host->mmc), rc);
 779                         else
 780                                 host->clk_rate = ios->clock;
 781                 }
 782                 clk |= MCI_CLK_ENABLE;
 783         }
 784
 785         if (ios->bus_width == MMC_BUS_WIDTH_4)
 786                 clk |= (2 << 10); /* Set WIDEBUS */
 787
 788         if (ios->clock > 400000 && msmsdcc_pwrsave)
 789                 clk |= (1 << 9); /* PWRSAVE */
 790
 791         clk |= (1 << 12); /* FLOW_ENA */
 792         clk |= (1 << 15); /* feedback clock */
 793
 794         if (host->plat->translate_vdd)
 795                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 796
 797         switch (ios->power_mode) {
 798         case MMC_POWER_OFF:
 799                 break;
 800         case MMC_POWER_UP:
 801                 pwr |= MCI_PWR_UP;
 802                 break;
 803         case MMC_POWER_ON:
 804                 pwr |= MCI_PWR_ON;
 805                 break;
 806         }
 807
 808         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 809                 pwr |= MCI_OD;
 810
 811         writel(clk, host->base + MMCICLOCK);
 812
 813         if (host->pwr != pwr) {
 814                 host->pwr = pwr;
 815                 writel(pwr, host->base + MMCIPOWER);
 816         }
 817
 818         if (!(clk & MCI_CLK_ENABLE) && host->clks_on)
 819                 msmsdcc_enable_clocks(host, 0);
 820         spin_unlock_irqrestore(&host->lock, flags);
 821 }
 822
 823 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 824 {
 825         struct msmsdcc_host *host = mmc_priv(mmc);
 826         unsigned long flags;
 827         u32 status;
 828
 829         spin_lock_irqsave(&host->lock, flags);
 830         if (msmsdcc_sdioirq == 1) {
 831                 status = readl(host->base + MMCIMASK0);
 832                 if (enable)
 833                         status |= MCI_SDIOINTOPERMASK;
 834                 else
 835                         status &= ~MCI_SDIOINTOPERMASK;
 836                 host->saved_irq0mask = status;
 837                 writel(status, host->base + MMCIMASK0);
 838         }
 839         spin_unlock_irqrestore(&host->lock, flags);
 840 }
 841
 842 static const struct mmc_host_ops msmsdcc_ops = {
 843         .request        = msmsdcc_request,
 844         .set_ios        = msmsdcc_set_ios,
 845         .enable_sdio_irq = msmsdcc_enable_sdio_irq,
 846 };
 847
 848 static void
 849 msmsdcc_check_status(unsigned long data)
 850 {
 851         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
 852         unsigned int status;
 853
 854         if (!host->plat->status) {
 855                 mmc_detect_change(host->mmc, 0);
 856                 goto out;
 857         }
 858
 859         status = host->plat->status(mmc_dev(host->mmc));
 860         host->eject = !status;
 861         if (status ^ host->oldstat) {
 862                 pr_info("%s: Slot status change detected (%d -> %d)\n",
 863                         mmc_hostname(host->mmc), host->oldstat, status);
 864                 if (status)
 865                         mmc_detect_change(host->mmc, (5 * HZ) / 2);
 866                 else
 867                         mmc_detect_change(host->mmc, 0);
 868         }
 869
 870         host->oldstat = status;
 871
 872 out:
 873         if (host->timer.function)
 874                 mod_timer(&host->timer, jiffies + HZ);
 875 }
 876
 877 static irqreturn_t
 878 msmsdcc_platform_status_irq(int irq, void *dev_id)
 879 {
 880         struct msmsdcc_host *host = dev_id;
 881
 882         printk(KERN_DEBUG "%s: %d\n", __func__, irq);
 883         msmsdcc_check_status((unsigned long) host);
 884         return IRQ_HANDLED;
 885 }
 886
 887 static void
 888 msmsdcc_status_notify_cb(int card_present, void *dev_id)
 889 {
 890         struct msmsdcc_host *host = dev_id;
 891
 892         printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
 893                card_present);
 894         msmsdcc_check_status((unsigned long) host);
 895 }
 896
 897 /*
 898  * called when a command expires.
 899  * Dump some debugging, and then error
 900  * out the transaction.
 901  */
 902 static void
 903 msmsdcc_command_expired(unsigned long _data)
 904 {
 905         struct msmsdcc_host     *host = (struct msmsdcc_host *) _data;
 906         struct mmc_request      *mrq;
 907         unsigned long           flags;
 908
 909         spin_lock_irqsave(&host->lock, flags);
 910         mrq = host->curr.mrq;
 911
 912         if (!mrq) {
 913                 pr_info("%s: Command expiry misfire\n",
 914                         mmc_hostname(host->mmc));
 915                 spin_unlock_irqrestore(&host->lock, flags);
 916                 return;
 917         }
 918
 919         pr_err("%s: Command timeout (%p %p %p %p)\n",
 920                mmc_hostname(host->mmc), mrq, mrq->cmd,
 921                mrq->data, host->dma.sg);
 922         mrq->cmd->error = -ETIMEDOUT;
 923         msmsdcc_stop_data(host);
 924
 925         writel(0, host->base + MMCICOMMAND);
 926
 927         host->curr.mrq = NULL;
 928         host->curr.cmd = NULL;
 929
 930         spin_unlock_irqrestore(&host->lock, flags);
 931         mmc_request_done(host->mmc, mrq);
 932 }
 933
 934 static int
 935 msmsdcc_init_dma(struct msmsdcc_host *host)
 936 {
 937         memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
 938         host->dma.host = host;
 939         host->dma.channel = -1;
 940
 941         if (!host->dmares)
 942                 return -ENODEV;
 943
 944         host->dma.nc = dma_alloc_coherent(NULL,
 945                                           sizeof(struct msmsdcc_nc_dmadata),
 946                                           &host->dma.nc_busaddr,
 947                                           GFP_KERNEL);
 948         if (host->dma.nc == NULL) {
 949                 pr_err("Unable to allocate DMA buffer\n");
 950                 return -ENOMEM;
 951         }
 952         memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
 953         host->dma.cmd_busaddr = host->dma.nc_busaddr;
 954         host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
 955                                 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
 956         host->dma.channel = host->dmares->start;
 957
 958         return 0;
 959 }
 960
 961 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
 962 static void
 963 do_resume_work(struct work_struct *work)
 964 {
 965         struct msmsdcc_host *host =
 966                 container_of(work, struct msmsdcc_host, resume_task);
 967         struct mmc_host *mmc = host->mmc;
 968
 969         if (mmc) {
 970                 mmc_resume_host(mmc);
 971                 if (host->stat_irq)
 972                         enable_irq(host->stat_irq);
 973         }
 974 }
 975 #endif
 976
 977 static int
 978 msmsdcc_probe(struct platform_device *pdev)
 979 {
 980         struct mmc_platform_data *plat = pdev->dev.platform_data;
 981         struct msmsdcc_host *host;
 982         struct mmc_host *mmc;
 983         struct resource *cmd_irqres = NULL;
 984         struct resource *pio_irqres = NULL;
 985         struct resource *stat_irqres = NULL;
 986         struct resource *memres = NULL;
 987         struct resource *dmares = NULL;
 988         int ret;
 989
 990         /* must have platform data */
 991         if (!plat) {
 992                 pr_err("%s: Platform data not available\n", __func__);
 993                 ret = -EINVAL;
 994                 goto out;
 995         }
 996
 997         if (pdev->id < 1 || pdev->id > 4)
 998                 return -EINVAL;
 999
1000         if (pdev->resource == NULL || pdev->num_resources < 2) {
1001                 pr_err("%s: Invalid resource\n", __func__);
1002                 return -ENXIO;
1003         }
1004
1005         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1006         dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1007         cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1008                                                   "cmd_irq");
1009         pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1010                                                   "pio_irq");
1011         stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1012                                                    "status_irq");
1013
1014         if (!cmd_irqres || !pio_irqres || !memres) {
1015                 pr_err("%s: Invalid resource\n", __func__);
1016                 return -ENXIO;
1017         }
1018
1019         /*
1020          * Setup our host structure
1021          */
1022
1023         mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1024         if (!mmc) {
1025                 ret = -ENOMEM;
1026                 goto out;
1027         }
1028
1029         host = mmc_priv(mmc);
1030         host->pdev_id = pdev->id;
1031         host->plat = plat;
1032         host->mmc = mmc;
1033
1034         host->cmdpoll = 1;
1035
1036         host->base = ioremap(memres->start, PAGE_SIZE);
1037         if (!host->base) {
1038                 ret = -ENOMEM;
1039                 goto out;
1040         }
1041
1042         host->cmd_irqres = cmd_irqres;
1043         host->pio_irqres = pio_irqres;
1044         host->memres = memres;
1045         host->dmares = dmares;
1046         spin_lock_init(&host->lock);
1047
1048         /*
1049          * Setup DMA
1050          */
1051         msmsdcc_init_dma(host);
1052
1053         /* Get our clocks */
1054         host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1055         if (IS_ERR(host->pclk)) {
1056                 ret = PTR_ERR(host->pclk);
1057                 goto host_free;
1058         }
1059
1060         host->clk = clk_get(&pdev->dev, "sdc_clk");
1061         if (IS_ERR(host->clk)) {
1062                 ret = PTR_ERR(host->clk);
1063                 goto pclk_put;
1064         }
1065
1066         /* Enable clocks */
1067         ret = msmsdcc_enable_clocks(host, 1);
1068         if (ret)
1069                 goto clk_put;
1070
1071         ret = clk_set_rate(host->clk, msmsdcc_fmin);
1072         if (ret) {
1073                 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1074                 goto clk_disable;
1075         }
1076
1077         host->pclk_rate = clk_get_rate(host->pclk);
1078         host->clk_rate = clk_get_rate(host->clk);
1079
1080         /*
1081          * Setup MMC host structure
1082          */
1083         mmc->ops = &msmsdcc_ops;
1084         mmc->f_min = msmsdcc_fmin;
1085         mmc->f_max = msmsdcc_fmax;
1086         mmc->ocr_avail = plat->ocr_mask;
1087
1088         if (msmsdcc_4bit)
1089                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1090         if (msmsdcc_sdioirq)
1091                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1092         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1093
1094         mmc->max_phys_segs = NR_SG;
1095         mmc->max_hw_segs = NR_SG;
1096         mmc->max_blk_size = 4096;       /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1097         mmc->max_blk_count = 65536;
1098
1099         mmc->max_req_size = 33554432;   /* MCI_DATA_LENGTH is 25 bits */
1100         mmc->max_seg_size = mmc->max_req_size;
1101
1102         writel(0, host->base + MMCIMASK0);
1103         writel(0x5e007ff, host->base + MMCICLEAR); /* Add: 1 << 25 */
1104
1105         writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1106         host->saved_irq0mask = MCI_IRQENABLE;
1107
1108         /*
1109          * Setup card detect change
1110          */
1111
1112         memset(&host->timer, 0, sizeof(host->timer));
1113
1114         if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1115                 unsigned long irqflags = IRQF_SHARED |
1116                         (stat_irqres->flags & IRQF_TRIGGER_MASK);
1117
1118                 host->stat_irq = stat_irqres->start;
1119                 ret = request_irq(host->stat_irq,
1120                                   msmsdcc_platform_status_irq,
1121                                   irqflags,
1122                                   DRIVER_NAME " (slot)",
1123                                   host);
1124                 if (ret) {
1125                         pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1126                                mmc_hostname(mmc), host->stat_irq, ret);
1127                         goto clk_disable;
1128                 }
1129         } else if (plat->register_status_notify) {
1130                 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1131         } else if (!plat->status)
1132                 pr_err("%s: No card detect facilities available\n",
1133                        mmc_hostname(mmc));
1134         else {
1135                 init_timer(&host->timer);
1136                 host->timer.data = (unsigned long)host;
1137                 host->timer.function = msmsdcc_check_status;
1138                 host->timer.expires = jiffies + HZ;
1139                 add_timer(&host->timer);
1140         }
1141
1142         if (plat->status) {
1143                 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1144                 host->eject = !host->oldstat;
1145         }
1146
1147         /*
1148          * Setup a command timer. We currently need this due to
1149          * some 'strange' timeout / error handling situations.
1150          */
1151         init_timer(&host->command_timer);
1152         host->command_timer.data = (unsigned long) host;
1153         host->command_timer.function = msmsdcc_command_expired;
1154
1155         ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1156                           DRIVER_NAME " (cmd)", host);
1157         if (ret)
1158                 goto stat_irq_free;
1159
1160         ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1161                           DRIVER_NAME " (pio)", host);
1162         if (ret)
1163                 goto cmd_irq_free;
1164
1165         mmc_set_drvdata(pdev, mmc);
1166         mmc_add_host(mmc);
1167
1168         pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1169                 mmc_hostname(mmc), (unsigned long long)memres->start,
1170                 (unsigned int) cmd_irqres->start,
1171                 (unsigned int) host->stat_irq, host->dma.channel);
1172         pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1173                 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1174         pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1175                 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1176         pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1177         pr_info("%s: Power save feature enable = %d\n",
1178                 mmc_hostname(mmc), msmsdcc_pwrsave);
1179
1180         if (host->dma.channel != -1) {
1181                 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1182                         mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1183                 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1184                         mmc_hostname(mmc), host->dma.cmd_busaddr,
1185                         host->dma.cmdptr_busaddr);
1186         } else
1187                 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1188         if (host->timer.function)
1189                 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1190
1191         return 0;
1192  cmd_irq_free:
1193         free_irq(cmd_irqres->start, host);
1194  stat_irq_free:
1195         if (host->stat_irq)
1196                 free_irq(host->stat_irq, host);
1197  clk_disable:
1198         msmsdcc_enable_clocks(host, 0);
1199  clk_put:
1200         clk_put(host->clk);
1201  pclk_put:
1202         clk_put(host->pclk);
1203  host_free:
1204         mmc_free_host(mmc);
1205  out:
1206         return ret;
1207 }
1208
1209 static int
1210 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1211 {
1212         struct mmc_host *mmc = mmc_get_drvdata(dev);
1213         int rc = 0;
1214
1215         if (mmc) {
1216                 struct msmsdcc_host *host = mmc_priv(mmc);
1217
1218                 if (host->stat_irq)
1219                         disable_irq(host->stat_irq);
1220
1221                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1222                         rc = mmc_suspend_host(mmc, state);
1223                 if (!rc) {
1224                         writel(0, host->base + MMCIMASK0);
1225
1226                         if (host->clks_on)
1227                                 msmsdcc_enable_clocks(host, 0);
1228                 }
1229         }
1230         return rc;
1231 }
1232
1233 static int
1234 msmsdcc_resume(struct platform_device *dev)
1235 {
1236         struct mmc_host *mmc = mmc_get_drvdata(dev);
1237         unsigned long flags;
1238
1239         if (mmc) {
1240                 struct msmsdcc_host *host = mmc_priv(mmc);
1241
1242                 spin_lock_irqsave(&host->lock, flags);
1243
1244                 if (!host->clks_on)
1245                         msmsdcc_enable_clocks(host, 1);
1246
1247                 writel(host->saved_irq0mask, host->base + MMCIMASK0);
1248
1249                 spin_unlock_irqrestore(&host->lock, flags);
1250
1251                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1252                         mmc_resume_host(mmc);
1253                 if (host->stat_irq)
1254                         enable_irq(host->stat_irq);
1255         }
1256         return 0;
1257 }
1258
1259 static struct platform_driver msmsdcc_driver = {
1260         .probe          = msmsdcc_probe,
1261         .suspend        = msmsdcc_suspend,
1262         .resume         = msmsdcc_resume,
1263         .driver         = {
1264                 .name   = "msm_sdcc",
1265         },
1266 };
1267
1268 static int __init msmsdcc_init(void)
1269 {
1270         return platform_driver_register(&msmsdcc_driver);
1271 }
1272
1273 static void __exit msmsdcc_exit(void)
1274 {
1275         platform_driver_unregister(&msmsdcc_driver);
1276 }
1277
1278 module_init(msmsdcc_init);
1279 module_exit(msmsdcc_exit);
1280
1281 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1282 MODULE_LICENSE("GPL");