2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Author: San Mehat (san@android.com)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
39 #include <linux/gpio.h>
41 #include <asm/cacheflush.h>
42 #include <asm/div64.h>
43 #include <asm/sizes.h>
46 #include <mach/msm_iomap.h>
52 #define DRIVER_NAME "msm-sdcc"
54 #define BUSCLK_PWRSAVE 1
55 #define BUSCLK_TIMEOUT (HZ)
56 static unsigned int msmsdcc_fmin = 144000;
57 static unsigned int msmsdcc_fmax = 50000000;
58 static unsigned int msmsdcc_4bit = 1;
59 static unsigned int msmsdcc_pwrsave = 1;
60 static unsigned int msmsdcc_piopoll = 1;
61 static unsigned int msmsdcc_sdioirq;
63 #define PIO_SPINMAX 30
64 #define CMD_SPINMAX 20
68 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
70 WARN_ON(!host->clks_on);
72 BUG_ON(host->curr.mrq);
75 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
77 del_timer_sync(&host->busclk_timer);
78 /* Need to check clks_on again in case the busclk
82 clk_disable(host->clk);
83 clk_disable(host->pclk);
90 msmsdcc_enable_clocks(struct msmsdcc_host *host)
94 del_timer_sync(&host->busclk_timer);
97 rc = clk_enable(host->pclk);
100 rc = clk_enable(host->clk);
102 clk_disable(host->pclk);
105 udelay(1 + ((3 * USEC_PER_SEC) /
106 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
112 static inline unsigned int
113 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
115 return readl(host->base + reg);
119 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
121 writel(data, host->base + reg);
122 /* 3 clk delay required! */
123 udelay(1 + ((3 * USEC_PER_SEC) /
124 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
128 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
131 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
137 /* Save the controller state */
138 mci_clk = readl(host->base + MMCICLOCK);
139 mci_mask0 = readl(host->base + MMCIMASK0);
141 /* Reset the controller */
142 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
144 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
145 mmc_hostname(host->mmc), host->clk_rate, ret);
147 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
149 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
150 mmc_hostname(host->mmc), host->clk_rate, ret);
152 pr_info("%s: Controller has been re-initialiazed\n",
153 mmc_hostname(host->mmc));
155 /* Restore the contoller state */
156 writel(host->pwr, host->base + MMCIPOWER);
157 writel(mci_clk, host->base + MMCICLOCK);
158 writel(mci_mask0, host->base + MMCIMASK0);
159 ret = clk_set_rate(host->clk, host->clk_rate);
161 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
162 mmc_hostname(host->mmc), host->clk_rate, ret);
166 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
168 BUG_ON(host->curr.data);
170 host->curr.mrq = NULL;
171 host->curr.cmd = NULL;
174 mrq->data->bytes_xfered = host->curr.data_xfered;
175 if (mrq->cmd->error == -ETIMEDOUT)
179 msmsdcc_disable_clocks(host, 1);
182 * Need to drop the host lock here; mmc_request_done may call
183 * back into the driver...
185 spin_unlock(&host->lock);
186 mmc_request_done(host->mmc, mrq);
187 spin_lock(&host->lock);
191 msmsdcc_stop_data(struct msmsdcc_host *host)
193 host->curr.data = NULL;
194 host->curr.got_dataend = 0;
197 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
199 return host->memres->start + MMCIFIFO;
203 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
204 msmsdcc_writel(host, arg, MMCIARGUMENT);
205 msmsdcc_writel(host, c, MMCICOMMAND);
209 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
211 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
213 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
214 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
216 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
217 (~MCI_IRQ_PIO)) | host->cmd_pio_irqmask, MMCIMASK0);
218 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
221 msmsdcc_start_command_exec(host,
222 (u32) host->cmd_cmd->arg,
225 host->dma.active = 1;
229 msmsdcc_dma_complete_tlet(unsigned long data)
231 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
233 struct mmc_request *mrq;
234 struct msm_dmov_errdata err;
236 spin_lock_irqsave(&host->lock, flags);
237 host->dma.active = 0;
240 mrq = host->curr.mrq;
244 if (!(host->dma.result & DMOV_RSLT_VALID)) {
245 pr_err("msmsdcc: Invalid DataMover result\n");
249 if (host->dma.result & DMOV_RSLT_DONE) {
250 host->curr.data_xfered = host->curr.xfer_size;
253 if (host->dma.result & DMOV_RSLT_ERROR)
254 pr_err("%s: DMA error (0x%.8x)\n",
255 mmc_hostname(host->mmc), host->dma.result);
256 if (host->dma.result & DMOV_RSLT_FLUSH)
257 pr_err("%s: DMA channel flushed (0x%.8x)\n",
258 mmc_hostname(host->mmc), host->dma.result);
260 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
261 err.flush[0], err.flush[1], err.flush[2],
262 err.flush[3], err.flush[4], err.flush[5]);
264 msmsdcc_reset_and_restore(host);
265 if (!mrq->data->error)
266 mrq->data->error = -EIO;
268 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
274 if (host->curr.got_dataend || mrq->data->error) {
277 * If we've already gotten our DATAEND / DATABLKEND
278 * for this request, then complete it through here.
280 msmsdcc_stop_data(host);
282 if (!mrq->data->error)
283 host->curr.data_xfered = host->curr.xfer_size;
284 if (!mrq->data->stop || mrq->cmd->error) {
285 host->curr.mrq = NULL;
286 host->curr.cmd = NULL;
287 mrq->data->bytes_xfered = host->curr.data_xfered;
289 spin_unlock_irqrestore(&host->lock, flags);
291 msmsdcc_disable_clocks(host, 1);
293 mmc_request_done(host->mmc, mrq);
296 msmsdcc_start_command(host, mrq->data->stop, 0);
300 spin_unlock_irqrestore(&host->lock, flags);
305 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
307 struct msm_dmov_errdata *err)
309 struct msmsdcc_dma_data *dma_data =
310 container_of(cmd, struct msmsdcc_dma_data, hdr);
311 struct msmsdcc_host *host = dma_data->host;
313 dma_data->result = result;
315 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
317 tasklet_schedule(&host->dma_tlet);
320 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
322 if (host->dma.channel == -1)
325 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
327 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
332 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
334 struct msmsdcc_nc_dmadata *nc;
340 struct scatterlist *sg = data->sg;
342 rc = validate_dma(host, data);
346 host->dma.sg = data->sg;
347 host->dma.num_ents = data->sg_len;
349 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
353 switch (host->pdev_id) {
355 crci = MSMSDCC_CRCI_SDC1;
358 crci = MSMSDCC_CRCI_SDC2;
361 crci = MSMSDCC_CRCI_SDC3;
364 crci = MSMSDCC_CRCI_SDC4;
368 host->dma.num_ents = 0;
372 if (data->flags & MMC_DATA_READ)
373 host->dma.dir = DMA_FROM_DEVICE;
375 host->dma.dir = DMA_TO_DEVICE;
377 host->curr.user_pages = 0;
381 /* location of command block must be 64 bit aligned */
382 BUG_ON(host->dma.cmd_busaddr & 0x07);
384 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
385 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
386 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
387 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
389 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
390 host->dma.num_ents, host->dma.dir);
392 pr_err("%s: Unable to map in all sg elements\n",
393 mmc_hostname(host->mmc));
395 host->dma.num_ents = 0;
399 for_each_sg(host->dma.sg, sg, n, i) {
401 box->cmd = CMD_MODE_BOX;
405 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
406 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
407 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
409 if (data->flags & MMC_DATA_READ) {
410 box->src_row_addr = msmsdcc_fifo_addr(host);
411 box->dst_row_addr = sg_dma_address(sg);
413 box->src_dst_len = (MCI_FIFOSIZE << 16) |
415 box->row_offset = MCI_FIFOSIZE;
417 box->num_rows = rows * ((1 << 16) + 1);
418 box->cmd |= CMD_SRC_CRCI(crci);
420 box->src_row_addr = sg_dma_address(sg);
421 box->dst_row_addr = msmsdcc_fifo_addr(host);
423 box->src_dst_len = (MCI_FIFOSIZE << 16) |
425 box->row_offset = (MCI_FIFOSIZE << 16);
427 box->num_rows = rows * ((1 << 16) + 1);
428 box->cmd |= CMD_DST_CRCI(crci);
437 snoop_cccr_abort(struct mmc_command *cmd)
439 if ((cmd->opcode == 52) &&
440 (cmd->arg & 0x80000000) &&
441 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
447 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
448 struct mmc_command *cmd, u32 *c)
450 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
452 if (cmd->flags & MMC_RSP_PRESENT) {
453 if (cmd->flags & MMC_RSP_136)
454 *c |= MCI_CPSM_LONGRSP;
455 *c |= MCI_CPSM_RESPONSE;
459 *c |= MCI_CPSM_INTERRUPT;
461 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
462 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
464 *c |= MCI_CSPM_DATCMD;
466 if (host->prog_scan && (cmd->opcode == 12)) {
467 *c |= MCI_CPSM_PROGENA;
468 host->prog_enable = true;
471 if (cmd == cmd->mrq->stop)
472 *c |= MCI_CSPM_MCIABORT;
474 if (snoop_cccr_abort(cmd))
475 *c |= MCI_CSPM_MCIABORT;
477 if (host->curr.cmd != NULL) {
478 pr_err("%s: Overlapping command requests\n",
479 mmc_hostname(host->mmc));
481 host->curr.cmd = cmd;
485 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
486 struct mmc_command *cmd, u32 c)
488 unsigned int datactrl, timeout;
489 unsigned long long clks;
490 unsigned int pio_irqmask = 0;
492 host->curr.data = data;
493 host->curr.xfer_size = data->blksz * data->blocks;
494 host->curr.xfer_remain = host->curr.xfer_size;
495 host->curr.data_xfered = 0;
496 host->curr.got_dataend = 0;
498 memset(&host->pio, 0, sizeof(host->pio));
500 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
502 if (!msmsdcc_config_dma(host, data))
503 datactrl |= MCI_DPSM_DMAENABLE;
505 host->pio.sg = data->sg;
506 host->pio.sg_len = data->sg_len;
507 host->pio.sg_off = 0;
509 if (data->flags & MMC_DATA_READ) {
510 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
511 if (host->curr.xfer_remain < MCI_FIFOSIZE)
512 pio_irqmask |= MCI_RXDATAAVLBLMASK;
514 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
517 if (data->flags & MMC_DATA_READ)
518 datactrl |= MCI_DPSM_DIRECTION;
520 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
521 do_div(clks, NSEC_PER_SEC);
522 timeout = data->timeout_clks + (unsigned int)clks*2 ;
524 if (datactrl & MCI_DPSM_DMAENABLE) {
525 /* Save parameters for the exec function */
526 host->cmd_timeout = timeout;
527 host->cmd_pio_irqmask = pio_irqmask;
528 host->cmd_datactrl = datactrl;
531 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
532 host->dma.hdr.data = (void *)host;
536 msmsdcc_start_command_deferred(host, cmd, &c);
539 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
540 if (data->flags & MMC_DATA_WRITE)
541 host->prog_scan = true;
543 msmsdcc_writel(host, timeout, MMCIDATATIMER);
545 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
547 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) &
548 (~MCI_IRQ_PIO)) | pio_irqmask, MMCIMASK0);
550 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
553 /* Daisy-chain the command if requested */
554 msmsdcc_start_command(host, cmd, c);
560 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
562 if (cmd == cmd->mrq->stop)
563 c |= MCI_CSPM_MCIABORT;
567 msmsdcc_start_command_deferred(host, cmd, &c);
568 msmsdcc_start_command_exec(host, cmd->arg, c);
572 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
575 if (status & MCI_DATACRCFAIL) {
576 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
577 pr_err("%s: opcode 0x%.8x\n", __func__,
578 data->mrq->cmd->opcode);
579 pr_err("%s: blksz %d, blocks %d\n", __func__,
580 data->blksz, data->blocks);
581 data->error = -EILSEQ;
582 } else if (status & MCI_DATATIMEOUT) {
583 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
584 data->error = -ETIMEDOUT;
585 } else if (status & MCI_RXOVERRUN) {
586 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
588 } else if (status & MCI_TXUNDERRUN) {
589 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
592 pr_err("%s: Unknown error (0x%.8x)\n",
593 mmc_hostname(host->mmc), status);
600 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
602 uint32_t *ptr = (uint32_t *) buffer;
606 remain = ((remain >> 2) + 1) << 2;
608 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
609 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
611 count += sizeof(uint32_t);
613 remain -= sizeof(uint32_t);
621 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
622 unsigned int remain, u32 status)
624 void __iomem *base = host->base;
628 unsigned int count, maxcnt, sz;
630 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
632 count = min(remain, maxcnt);
634 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
635 writesl(base + MMCIFIFO, ptr, sz);
642 status = msmsdcc_readl(host, MMCISTATUS);
643 } while (status & MCI_TXFIFOHALFEMPTY);
649 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
652 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
661 msmsdcc_pio_irq(int irq, void *dev_id)
663 struct msmsdcc_host *host = dev_id;
667 status = msmsdcc_readl(host, MMCISTATUS);
668 mci_mask0 = msmsdcc_readl(host, MMCIMASK0);
670 if (((mci_mask0 & status) & MCI_IRQ_PIO) == 0)
675 unsigned int remain, len;
678 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
679 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
682 if (msmsdcc_spin_on_status(host,
683 (MCI_TXFIFOHALFEMPTY |
690 /* Map the current scatter buffer */
691 local_irq_save(flags);
692 buffer = kmap_atomic(sg_page(host->pio.sg))
693 + host->pio.sg->offset;
694 buffer += host->pio.sg_off;
695 remain = host->pio.sg->length - host->pio.sg_off;
697 if (status & MCI_RXACTIVE)
698 len = msmsdcc_pio_read(host, buffer, remain);
699 if (status & MCI_TXACTIVE)
700 len = msmsdcc_pio_write(host, buffer, remain, status);
702 /* Unmap the buffer */
703 kunmap_atomic(buffer);
704 local_irq_restore(flags);
706 host->pio.sg_off += len;
707 host->curr.xfer_remain -= len;
708 host->curr.data_xfered += len;
712 /* This sg page is full - do some housekeeping */
713 if (status & MCI_RXACTIVE && host->curr.user_pages)
714 flush_dcache_page(sg_page(host->pio.sg));
716 if (!--host->pio.sg_len) {
717 memset(&host->pio, 0, sizeof(host->pio));
721 /* Advance to next sg */
723 host->pio.sg_off = 0;
726 status = msmsdcc_readl(host, MMCISTATUS);
729 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
730 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) |
731 MCI_RXDATAAVLBLMASK, MMCIMASK0);
733 if (!host->curr.xfer_remain)
734 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) | 0,
740 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
742 struct mmc_command *cmd = host->curr.cmd;
744 host->curr.cmd = NULL;
745 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
746 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
747 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
748 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
750 if (status & MCI_CMDTIMEOUT) {
751 cmd->error = -ETIMEDOUT;
752 } else if (status & MCI_CMDCRCFAIL &&
753 cmd->flags & MMC_RSP_CRC) {
754 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
755 cmd->error = -EILSEQ;
758 if (!cmd->data || cmd->error) {
759 if (host->curr.data && host->dma.sg)
760 msm_dmov_stop_cmd(host->dma.channel,
762 else if (host->curr.data) { /* Non DMA */
763 msmsdcc_reset_and_restore(host);
764 msmsdcc_stop_data(host);
765 msmsdcc_request_end(host, cmd->mrq);
766 } else { /* host->data == NULL */
767 if (!cmd->error && host->prog_enable) {
768 if (status & MCI_PROGDONE) {
769 host->prog_scan = false;
770 host->prog_enable = false;
771 msmsdcc_request_end(host, cmd->mrq);
773 host->curr.cmd = cmd;
776 if (host->prog_enable) {
777 host->prog_scan = false;
778 host->prog_enable = false;
780 msmsdcc_request_end(host, cmd->mrq);
783 } else if (cmd->data)
784 if (!(cmd->data->flags & MMC_DATA_READ))
785 msmsdcc_start_data(host, cmd->data,
790 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
793 struct mmc_data *data = host->curr.data;
795 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
796 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
797 msmsdcc_do_cmdirq(host, status);
803 /* Check for data errors */
804 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
805 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
806 msmsdcc_data_err(host, data, status);
807 host->curr.data_xfered = 0;
809 msm_dmov_stop_cmd(host->dma.channel,
812 msmsdcc_reset_and_restore(host);
814 msmsdcc_stop_data(host);
816 msmsdcc_request_end(host, data->mrq);
818 msmsdcc_start_command(host, data->stop, 0);
822 /* Check for data done */
823 if (!host->curr.got_dataend && (status & MCI_DATAEND))
824 host->curr.got_dataend = 1;
827 * If DMA is still in progress, we complete via the completion handler
829 if (host->curr.got_dataend && !host->dma.busy) {
831 * There appears to be an issue in the controller where
832 * if you request a small block transfer (< fifo size),
833 * you may get your DATAEND/DATABLKEND irq without the
836 * Check to see if there is still data to be read,
837 * and simulate a PIO irq.
839 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
840 msmsdcc_pio_irq(1, host);
842 msmsdcc_stop_data(host);
844 host->curr.data_xfered = host->curr.xfer_size;
847 msmsdcc_request_end(host, data->mrq);
849 msmsdcc_start_command(host, data->stop, 0);
854 msmsdcc_irq(int irq, void *dev_id)
856 struct msmsdcc_host *host = dev_id;
857 void __iomem *base = host->base;
862 spin_lock(&host->lock);
865 status = msmsdcc_readl(host, MMCISTATUS);
866 status &= msmsdcc_readl(host, MMCIMASK0);
867 if ((status & (~MCI_IRQ_PIO)) == 0)
869 msmsdcc_writel(host, status, MMCICLEAR);
871 if (status & MCI_SDIOINTR)
872 status &= ~MCI_SDIOINTR;
877 msmsdcc_handle_irq_data(host, status, base);
879 if (status & MCI_SDIOINTOPER) {
881 status &= ~MCI_SDIOINTOPER;
886 spin_unlock(&host->lock);
889 * We have to delay handling the card interrupt as it calls
890 * back into the driver.
893 mmc_signal_sdio_irq(host->mmc);
895 return IRQ_RETVAL(ret);
899 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
901 struct msmsdcc_host *host = mmc_priv(mmc);
904 WARN_ON(host->curr.mrq != NULL);
905 WARN_ON(host->pwr == 0);
907 spin_lock_irqsave(&host->lock, flags);
912 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
914 mrq->data->bytes_xfered = mrq->data->blksz *
917 mrq->cmd->error = -ENOMEDIUM;
919 spin_unlock_irqrestore(&host->lock, flags);
920 mmc_request_done(mmc, mrq);
924 msmsdcc_enable_clocks(host);
926 host->curr.mrq = mrq;
928 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
929 /* Queue/read data, daisy-chain command when data starts */
930 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
932 msmsdcc_start_command(host, mrq->cmd, 0);
934 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
935 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
937 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
938 msmsdcc_do_cmdirq(host, status);
940 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
942 host->stats.cmdpoll_hits++;
944 host->stats.cmdpoll_misses++;
946 spin_unlock_irqrestore(&host->lock, flags);
949 static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable)
951 struct msm_mmc_gpio_data *curr;
954 if (!host->plat->gpio_data || host->gpio_config_status == enable)
957 curr = host->plat->gpio_data;
958 for (i = 0; i < curr->size; i++) {
960 rc = gpio_request(curr->gpio[i].no,
963 pr_err("%s: gpio_request(%d, %s) failed %d\n",
964 mmc_hostname(host->mmc),
966 curr->gpio[i].name, rc);
970 gpio_free(curr->gpio[i].no);
973 host->gpio_config_status = enable;
978 gpio_free(curr->gpio[i].no);
982 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
984 struct msmsdcc_host *host = mmc_priv(mmc);
985 u32 clk = 0, pwr = 0;
989 spin_lock_irqsave(&host->lock, flags);
991 msmsdcc_enable_clocks(host);
993 spin_unlock_irqrestore(&host->lock, flags);
996 if (ios->clock != host->clk_rate) {
997 rc = clk_set_rate(host->clk, ios->clock);
999 pr_err("%s: Error setting clock rate (%d)\n",
1000 mmc_hostname(host->mmc), rc);
1002 host->clk_rate = ios->clock;
1004 clk |= MCI_CLK_ENABLE;
1007 if (ios->bus_width == MMC_BUS_WIDTH_4)
1008 clk |= (2 << 10); /* Set WIDEBUS */
1010 if (ios->clock > 400000 && msmsdcc_pwrsave)
1011 clk |= (1 << 9); /* PWRSAVE */
1013 clk |= (1 << 12); /* FLOW_ENA */
1014 clk |= (1 << 15); /* feedback clock */
1016 if (host->plat->translate_vdd)
1017 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
1019 switch (ios->power_mode) {
1021 msmsdcc_setup_gpio(host, false);
1025 msmsdcc_setup_gpio(host, true);
1032 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1035 msmsdcc_writel(host, clk, MMCICLOCK);
1037 if (host->pwr != pwr) {
1039 msmsdcc_writel(host, pwr, MMCIPOWER);
1042 spin_lock_irqsave(&host->lock, flags);
1043 msmsdcc_disable_clocks(host, 1);
1044 spin_unlock_irqrestore(&host->lock, flags);
1048 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1050 struct msmsdcc_host *host = mmc_priv(mmc);
1051 unsigned long flags;
1054 spin_lock_irqsave(&host->lock, flags);
1055 if (msmsdcc_sdioirq == 1) {
1056 status = msmsdcc_readl(host, MMCIMASK0);
1058 status |= MCI_SDIOINTOPERMASK;
1060 status &= ~MCI_SDIOINTOPERMASK;
1061 host->saved_irq0mask = status;
1062 msmsdcc_writel(host, status, MMCIMASK0);
1064 spin_unlock_irqrestore(&host->lock, flags);
1067 static void msmsdcc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1069 struct msmsdcc_host *host = mmc_priv(mmc);
1071 if (host->plat->init_card)
1072 host->plat->init_card(card);
1075 static const struct mmc_host_ops msmsdcc_ops = {
1076 .request = msmsdcc_request,
1077 .set_ios = msmsdcc_set_ios,
1078 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1079 .init_card = msmsdcc_init_card,
1083 msmsdcc_check_status(unsigned long data)
1085 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1086 unsigned int status;
1088 if (!host->plat->status) {
1089 mmc_detect_change(host->mmc, 0);
1093 status = host->plat->status(mmc_dev(host->mmc));
1094 host->eject = !status;
1095 if (status ^ host->oldstat) {
1096 pr_info("%s: Slot status change detected (%d -> %d)\n",
1097 mmc_hostname(host->mmc), host->oldstat, status);
1099 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1101 mmc_detect_change(host->mmc, 0);
1104 host->oldstat = status;
1107 if (host->timer.function)
1108 mod_timer(&host->timer, jiffies + HZ);
1112 msmsdcc_platform_status_irq(int irq, void *dev_id)
1114 struct msmsdcc_host *host = dev_id;
1116 pr_debug("%s: %d\n", __func__, irq);
1117 msmsdcc_check_status((unsigned long) host);
1122 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1124 struct msmsdcc_host *host = dev_id;
1126 pr_debug("%s: card_present %d\n", mmc_hostname(host->mmc),
1128 msmsdcc_check_status((unsigned long) host);
1132 msmsdcc_busclk_expired(unsigned long _data)
1134 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
1137 msmsdcc_disable_clocks(host, 0);
1141 msmsdcc_init_dma(struct msmsdcc_host *host)
1143 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1144 host->dma.host = host;
1145 host->dma.channel = -1;
1150 host->dma.nc = dma_alloc_coherent(NULL,
1151 sizeof(struct msmsdcc_nc_dmadata),
1152 &host->dma.nc_busaddr,
1154 if (host->dma.nc == NULL) {
1155 pr_err("Unable to allocate DMA buffer\n");
1158 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1159 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1160 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1161 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1162 host->dma.channel = host->dmares->start;
1168 msmsdcc_probe(struct platform_device *pdev)
1170 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1171 struct msmsdcc_host *host;
1172 struct mmc_host *mmc;
1173 struct resource *cmd_irqres = NULL;
1174 struct resource *stat_irqres = NULL;
1175 struct resource *memres = NULL;
1176 struct resource *dmares = NULL;
1179 /* must have platform data */
1181 pr_err("%s: Platform data not available\n", __func__);
1186 if (pdev->id < 1 || pdev->id > 4)
1189 if (pdev->resource == NULL || pdev->num_resources < 2) {
1190 pr_err("%s: Invalid resource\n", __func__);
1194 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1195 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1196 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1198 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1201 if (!cmd_irqres || !memres) {
1202 pr_err("%s: Invalid resource\n", __func__);
1207 * Setup our host structure
1210 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1216 host = mmc_priv(mmc);
1217 host->pdev_id = pdev->id;
1220 host->curr.cmd = NULL;
1221 init_timer(&host->busclk_timer);
1222 host->busclk_timer.data = (unsigned long) host;
1223 host->busclk_timer.function = msmsdcc_busclk_expired;
1228 host->base = ioremap(memres->start, PAGE_SIZE);
1234 host->cmd_irqres = cmd_irqres;
1235 host->memres = memres;
1236 host->dmares = dmares;
1237 spin_lock_init(&host->lock);
1239 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1240 (unsigned long)host);
1246 ret = msmsdcc_init_dma(host);
1250 host->dma.channel = -1;
1253 /* Get our clocks */
1254 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1255 if (IS_ERR(host->pclk)) {
1256 ret = PTR_ERR(host->pclk);
1260 host->clk = clk_get(&pdev->dev, "sdc_clk");
1261 if (IS_ERR(host->clk)) {
1262 ret = PTR_ERR(host->clk);
1266 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1268 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1273 ret = msmsdcc_enable_clocks(host);
1277 host->pclk_rate = clk_get_rate(host->pclk);
1278 host->clk_rate = clk_get_rate(host->clk);
1281 * Setup MMC host structure
1283 mmc->ops = &msmsdcc_ops;
1284 mmc->f_min = msmsdcc_fmin;
1285 mmc->f_max = msmsdcc_fmax;
1286 mmc->ocr_avail = plat->ocr_mask;
1289 mmc->caps |= MMC_CAP_4_BIT_DATA;
1290 if (msmsdcc_sdioirq)
1291 mmc->caps |= MMC_CAP_SDIO_IRQ;
1292 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1294 mmc->max_segs = NR_SG;
1295 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1296 mmc->max_blk_count = 65536;
1298 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1299 mmc->max_seg_size = mmc->max_req_size;
1301 msmsdcc_writel(host, 0, MMCIMASK0);
1302 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1304 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1305 host->saved_irq0mask = MCI_IRQENABLE;
1308 * Setup card detect change
1311 memset(&host->timer, 0, sizeof(host->timer));
1313 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1314 unsigned long irqflags = IRQF_SHARED |
1315 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1317 host->stat_irq = stat_irqres->start;
1318 ret = request_irq(host->stat_irq,
1319 msmsdcc_platform_status_irq,
1321 DRIVER_NAME " (slot)",
1324 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1325 mmc_hostname(mmc), host->stat_irq, ret);
1328 } else if (plat->register_status_notify) {
1329 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1330 } else if (!plat->status)
1331 pr_err("%s: No card detect facilities available\n",
1334 init_timer(&host->timer);
1335 host->timer.data = (unsigned long)host;
1336 host->timer.function = msmsdcc_check_status;
1337 host->timer.expires = jiffies + HZ;
1338 add_timer(&host->timer);
1342 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1343 host->eject = !host->oldstat;
1346 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1347 DRIVER_NAME " (cmd)", host);
1351 ret = request_irq(cmd_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1352 DRIVER_NAME " (pio)", host);
1356 mmc_set_drvdata(pdev, mmc);
1359 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1360 mmc_hostname(mmc), (unsigned long long)memres->start,
1361 (unsigned int) cmd_irqres->start,
1362 (unsigned int) host->stat_irq, host->dma.channel);
1363 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1364 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1365 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1366 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1367 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1368 pr_info("%s: Power save feature enable = %d\n",
1369 mmc_hostname(mmc), msmsdcc_pwrsave);
1371 if (host->dma.channel != -1) {
1372 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1373 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1374 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1375 mmc_hostname(mmc), host->dma.cmd_busaddr,
1376 host->dma.cmdptr_busaddr);
1378 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1379 if (host->timer.function)
1380 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1384 free_irq(cmd_irqres->start, host);
1387 free_irq(host->stat_irq, host);
1389 msmsdcc_disable_clocks(host, 0);
1393 clk_put(host->pclk);
1396 dma_free_coherent(NULL, sizeof(struct msmsdcc_nc_dmadata),
1397 host->dma.nc, host->dma.nc_busaddr);
1399 tasklet_kill(&host->dma_tlet);
1400 iounmap(host->base);
1408 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1410 do_resume_work(struct work_struct *work)
1412 struct msmsdcc_host *host =
1413 container_of(work, struct msmsdcc_host, resume_task);
1414 struct mmc_host *mmc = host->mmc;
1417 mmc_resume_host(mmc);
1419 enable_irq(host->stat_irq);
1426 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1428 struct mmc_host *mmc = mmc_get_drvdata(dev);
1432 struct msmsdcc_host *host = mmc_priv(mmc);
1435 disable_irq(host->stat_irq);
1437 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1438 rc = mmc_suspend_host(mmc);
1440 msmsdcc_writel(host, 0, MMCIMASK0);
1442 msmsdcc_disable_clocks(host, 0);
1448 msmsdcc_resume(struct platform_device *dev)
1450 struct mmc_host *mmc = mmc_get_drvdata(dev);
1453 struct msmsdcc_host *host = mmc_priv(mmc);
1455 msmsdcc_enable_clocks(host);
1457 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1459 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1460 mmc_resume_host(mmc);
1462 enable_irq(host->stat_irq);
1464 msmsdcc_disable_clocks(host, 1);
1470 #define msmsdcc_suspend 0
1471 #define msmsdcc_resume 0
1474 static struct platform_driver msmsdcc_driver = {
1475 .probe = msmsdcc_probe,
1476 .suspend = msmsdcc_suspend,
1477 .resume = msmsdcc_resume,
1483 module_platform_driver(msmsdcc_driver);
1485 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1486 MODULE_LICENSE("GPL");