2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/omap-dma.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29 #include <linux/scatterlist.h>
30 #include <linux/i2c/tps65010.h>
31 #include <linux/slab.h>
36 #include <plat/board.h>
41 #include <plat/fpga.h>
43 #define OMAP_MMC_REG_CMD 0x00
44 #define OMAP_MMC_REG_ARGL 0x01
45 #define OMAP_MMC_REG_ARGH 0x02
46 #define OMAP_MMC_REG_CON 0x03
47 #define OMAP_MMC_REG_STAT 0x04
48 #define OMAP_MMC_REG_IE 0x05
49 #define OMAP_MMC_REG_CTO 0x06
50 #define OMAP_MMC_REG_DTO 0x07
51 #define OMAP_MMC_REG_DATA 0x08
52 #define OMAP_MMC_REG_BLEN 0x09
53 #define OMAP_MMC_REG_NBLK 0x0a
54 #define OMAP_MMC_REG_BUF 0x0b
55 #define OMAP_MMC_REG_SDIO 0x0d
56 #define OMAP_MMC_REG_REV 0x0f
57 #define OMAP_MMC_REG_RSP0 0x10
58 #define OMAP_MMC_REG_RSP1 0x11
59 #define OMAP_MMC_REG_RSP2 0x12
60 #define OMAP_MMC_REG_RSP3 0x13
61 #define OMAP_MMC_REG_RSP4 0x14
62 #define OMAP_MMC_REG_RSP5 0x15
63 #define OMAP_MMC_REG_RSP6 0x16
64 #define OMAP_MMC_REG_RSP7 0x17
65 #define OMAP_MMC_REG_IOSR 0x18
66 #define OMAP_MMC_REG_SYSC 0x19
67 #define OMAP_MMC_REG_SYSS 0x1a
69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
73 #define OMAP_MMC_STAT_A_FULL (1 << 10)
74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
78 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
83 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
84 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
85 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
90 #define OMAP_MMC_CMDTYPE_BC 0
91 #define OMAP_MMC_CMDTYPE_BCR 1
92 #define OMAP_MMC_CMDTYPE_AC 2
93 #define OMAP_MMC_CMDTYPE_ADTC 3
96 #define DRIVER_NAME "mmci-omap"
98 /* Specifies how often in millisecs to poll for card status changes
99 * when the cover switch is open */
100 #define OMAP_MMC_COVER_POLL_DELAY 500
102 struct mmc_omap_host;
104 struct mmc_omap_slot {
109 unsigned int fclk_freq;
112 struct tasklet_struct cover_tasklet;
113 struct timer_list cover_timer;
116 struct mmc_request *mrq;
117 struct mmc_omap_host *host;
118 struct mmc_host *mmc;
119 struct omap_mmc_slot_data *pdata;
122 struct mmc_omap_host {
125 struct mmc_request * mrq;
126 struct mmc_command * cmd;
127 struct mmc_data * data;
128 struct mmc_host * mmc;
130 unsigned char id; /* 16xx chips have 2 MMC blocks */
133 struct dma_chan *dma_rx;
135 struct dma_chan *dma_tx;
137 struct resource *mem_res;
138 void __iomem *virt_base;
139 unsigned int phys_base;
141 unsigned char bus_mode;
142 unsigned char hw_bus_mode;
143 unsigned int reg_shift;
145 struct work_struct cmd_abort_work;
147 struct timer_list cmd_abort_timer;
149 struct work_struct slot_release_work;
150 struct mmc_omap_slot *next_slot;
151 struct work_struct send_stop_work;
152 struct mmc_data *stop_data;
157 u32 buffer_bytes_left;
158 u32 total_bytes_left;
161 unsigned brs_received:1, dma_done:1;
162 unsigned dma_in_use:1;
165 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
166 struct mmc_omap_slot *current_slot;
167 spinlock_t slot_lock;
168 wait_queue_head_t slot_wq;
171 struct timer_list clk_timer;
172 spinlock_t clk_lock; /* for changing enabled state */
173 unsigned int fclk_enabled:1;
174 struct workqueue_struct *mmc_omap_wq;
176 struct omap_mmc_platform_data *pdata;
180 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
182 unsigned long tick_ns;
184 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
185 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
190 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
194 spin_lock_irqsave(&host->clk_lock, flags);
195 if (host->fclk_enabled != enable) {
196 host->fclk_enabled = enable;
198 clk_enable(host->fclk);
200 clk_disable(host->fclk);
202 spin_unlock_irqrestore(&host->clk_lock, flags);
205 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
207 struct mmc_omap_host *host = slot->host;
212 spin_lock_irqsave(&host->slot_lock, flags);
213 while (host->mmc != NULL) {
214 spin_unlock_irqrestore(&host->slot_lock, flags);
215 wait_event(host->slot_wq, host->mmc == NULL);
216 spin_lock_irqsave(&host->slot_lock, flags);
218 host->mmc = slot->mmc;
219 spin_unlock_irqrestore(&host->slot_lock, flags);
221 del_timer(&host->clk_timer);
222 if (host->current_slot != slot || !claimed)
223 mmc_omap_fclk_offdelay(host->current_slot);
225 if (host->current_slot != slot) {
226 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
227 if (host->pdata->switch_slot != NULL)
228 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
229 host->current_slot = slot;
233 mmc_omap_fclk_enable(host, 1);
235 /* Doing the dummy read here seems to work around some bug
236 * at least in OMAP24xx silicon where the command would not
237 * start after writing the CMD register. Sigh. */
238 OMAP_MMC_READ(host, CON);
240 OMAP_MMC_WRITE(host, CON, slot->saved_con);
242 mmc_omap_fclk_enable(host, 0);
245 static void mmc_omap_start_request(struct mmc_omap_host *host,
246 struct mmc_request *req);
248 static void mmc_omap_slot_release_work(struct work_struct *work)
250 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
252 struct mmc_omap_slot *next_slot = host->next_slot;
253 struct mmc_request *rq;
255 host->next_slot = NULL;
256 mmc_omap_select_slot(next_slot, 1);
259 next_slot->mrq = NULL;
260 mmc_omap_start_request(host, rq);
263 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
265 struct mmc_omap_host *host = slot->host;
269 BUG_ON(slot == NULL || host->mmc == NULL);
272 /* Keeps clock running for at least 8 cycles on valid freq */
273 mod_timer(&host->clk_timer, jiffies + HZ/10);
275 del_timer(&host->clk_timer);
276 mmc_omap_fclk_offdelay(slot);
277 mmc_omap_fclk_enable(host, 0);
280 spin_lock_irqsave(&host->slot_lock, flags);
281 /* Check for any pending requests */
282 for (i = 0; i < host->nr_slots; i++) {
283 struct mmc_omap_slot *new_slot;
285 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
288 BUG_ON(host->next_slot != NULL);
289 new_slot = host->slots[i];
290 /* The current slot should not have a request in queue */
291 BUG_ON(new_slot == host->current_slot);
293 host->next_slot = new_slot;
294 host->mmc = new_slot->mmc;
295 spin_unlock_irqrestore(&host->slot_lock, flags);
296 queue_work(host->mmc_omap_wq, &host->slot_release_work);
301 wake_up(&host->slot_wq);
302 spin_unlock_irqrestore(&host->slot_lock, flags);
306 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
308 if (slot->pdata->get_cover_state)
309 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
315 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
318 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
319 struct mmc_omap_slot *slot = mmc_priv(mmc);
321 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
325 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
328 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
331 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
332 struct mmc_omap_slot *slot = mmc_priv(mmc);
334 return sprintf(buf, "%s\n", slot->pdata->name);
337 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
340 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
351 /* Our hardware needs to know exact type */
352 switch (mmc_resp_type(cmd)) {
357 /* resp 1, 1b, 6, 7 */
367 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
371 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
372 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
373 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
374 cmdtype = OMAP_MMC_CMDTYPE_BC;
375 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
376 cmdtype = OMAP_MMC_CMDTYPE_BCR;
378 cmdtype = OMAP_MMC_CMDTYPE_AC;
381 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
383 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
386 if (cmd->flags & MMC_RSP_BUSY)
389 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
392 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
394 OMAP_MMC_WRITE(host, CTO, 200);
395 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
396 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
397 OMAP_MMC_WRITE(host, IE,
398 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
399 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
400 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
401 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
402 OMAP_MMC_STAT_END_OF_DATA);
403 OMAP_MMC_WRITE(host, CMD, cmdreg);
407 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
410 enum dma_data_direction dma_data_dir;
411 struct device *dev = mmc_dev(host->mmc);
414 if (data->flags & MMC_DATA_WRITE) {
415 dma_data_dir = DMA_TO_DEVICE;
418 dma_data_dir = DMA_FROM_DEVICE;
423 dmaengine_terminate_all(c);
424 /* Claim nothing transferred on error... */
425 data->bytes_xfered = 0;
427 dev = c->device->dev;
429 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
432 static void mmc_omap_send_stop_work(struct work_struct *work)
434 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
436 struct mmc_omap_slot *slot = host->current_slot;
437 struct mmc_data *data = host->stop_data;
438 unsigned long tick_ns;
440 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
443 mmc_omap_start_command(host, data->stop);
447 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
449 if (host->dma_in_use)
450 mmc_omap_release_dma(host, data, data->error);
455 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
456 * dozens of requests until the card finishes writing data.
457 * It'd be cheaper to just wait till an EOFB interrupt arrives...
461 struct mmc_host *mmc;
465 mmc_omap_release_slot(host->current_slot, 1);
466 mmc_request_done(mmc, data->mrq);
470 host->stop_data = data;
471 queue_work(host->mmc_omap_wq, &host->send_stop_work);
475 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
477 struct mmc_omap_slot *slot = host->current_slot;
478 unsigned int restarts, passes, timeout;
481 /* Sending abort takes 80 clocks. Have some extra and round up */
482 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
484 while (restarts < maxloops) {
485 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
486 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
489 while (passes < timeout) {
490 stat = OMAP_MMC_READ(host, STAT);
491 if (stat & OMAP_MMC_STAT_END_OF_CMD)
500 OMAP_MMC_WRITE(host, STAT, stat);
504 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
506 if (host->dma_in_use)
507 mmc_omap_release_dma(host, data, 1);
512 mmc_omap_send_abort(host, 10000);
516 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
521 if (!host->dma_in_use) {
522 mmc_omap_xfer_done(host, data);
526 spin_lock_irqsave(&host->dma_lock, flags);
530 host->brs_received = 1;
531 spin_unlock_irqrestore(&host->dma_lock, flags);
533 mmc_omap_xfer_done(host, data);
537 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
543 spin_lock_irqsave(&host->dma_lock, flags);
544 if (host->brs_received)
548 spin_unlock_irqrestore(&host->dma_lock, flags);
550 mmc_omap_xfer_done(host, data);
554 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
558 del_timer(&host->cmd_abort_timer);
560 if (cmd->flags & MMC_RSP_PRESENT) {
561 if (cmd->flags & MMC_RSP_136) {
562 /* response type 2 */
564 OMAP_MMC_READ(host, RSP0) |
565 (OMAP_MMC_READ(host, RSP1) << 16);
567 OMAP_MMC_READ(host, RSP2) |
568 (OMAP_MMC_READ(host, RSP3) << 16);
570 OMAP_MMC_READ(host, RSP4) |
571 (OMAP_MMC_READ(host, RSP5) << 16);
573 OMAP_MMC_READ(host, RSP6) |
574 (OMAP_MMC_READ(host, RSP7) << 16);
576 /* response types 1, 1b, 3, 4, 5, 6 */
578 OMAP_MMC_READ(host, RSP6) |
579 (OMAP_MMC_READ(host, RSP7) << 16);
583 if (host->data == NULL || cmd->error) {
584 struct mmc_host *mmc;
586 if (host->data != NULL)
587 mmc_omap_abort_xfer(host, host->data);
590 mmc_omap_release_slot(host->current_slot, 1);
591 mmc_request_done(mmc, cmd->mrq);
596 * Abort stuck command. Can occur when card is removed while it is being
599 static void mmc_omap_abort_command(struct work_struct *work)
601 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
605 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
608 if (host->cmd->error == 0)
609 host->cmd->error = -ETIMEDOUT;
611 if (host->data == NULL) {
612 struct mmc_command *cmd;
613 struct mmc_host *mmc;
617 mmc_omap_send_abort(host, 10000);
621 mmc_omap_release_slot(host->current_slot, 1);
622 mmc_request_done(mmc, cmd->mrq);
624 mmc_omap_cmd_done(host, host->cmd);
627 enable_irq(host->irq);
631 mmc_omap_cmd_timer(unsigned long data)
633 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
636 spin_lock_irqsave(&host->slot_lock, flags);
637 if (host->cmd != NULL && !host->abort) {
638 OMAP_MMC_WRITE(host, IE, 0);
639 disable_irq(host->irq);
641 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
643 spin_unlock_irqrestore(&host->slot_lock, flags);
648 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
650 struct scatterlist *sg;
652 sg = host->data->sg + host->sg_idx;
653 host->buffer_bytes_left = sg->length;
654 host->buffer = sg_virt(sg);
655 if (host->buffer_bytes_left > host->total_bytes_left)
656 host->buffer_bytes_left = host->total_bytes_left;
660 mmc_omap_clk_timer(unsigned long data)
662 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
664 mmc_omap_fclk_enable(host, 0);
669 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
673 if (host->buffer_bytes_left == 0) {
675 BUG_ON(host->sg_idx == host->sg_len);
676 mmc_omap_sg_to_buf(host);
679 if (n > host->buffer_bytes_left)
680 n = host->buffer_bytes_left;
681 host->buffer_bytes_left -= n;
682 host->total_bytes_left -= n;
683 host->data->bytes_xfered += n;
686 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
688 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n);
692 static inline void mmc_omap_report_irq(u16 status)
694 static const char *mmc_omap_status_bits[] = {
695 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
696 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
700 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
701 if (status & (1 << i)) {
704 printk("%s", mmc_omap_status_bits[i]);
709 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
711 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
715 int transfer_error, cmd_error;
717 if (host->cmd == NULL && host->data == NULL) {
718 status = OMAP_MMC_READ(host, STAT);
719 dev_info(mmc_dev(host->slots[0]->mmc),
720 "Spurious IRQ 0x%04x\n", status);
722 OMAP_MMC_WRITE(host, STAT, status);
723 OMAP_MMC_WRITE(host, IE, 0);
733 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
736 OMAP_MMC_WRITE(host, STAT, status);
737 if (host->cmd != NULL)
738 cmd = host->cmd->opcode;
741 #ifdef CONFIG_MMC_DEBUG
742 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
744 mmc_omap_report_irq(status);
747 if (host->total_bytes_left) {
748 if ((status & OMAP_MMC_STAT_A_FULL) ||
749 (status & OMAP_MMC_STAT_END_OF_DATA))
750 mmc_omap_xfer_data(host, 0);
751 if (status & OMAP_MMC_STAT_A_EMPTY)
752 mmc_omap_xfer_data(host, 1);
755 if (status & OMAP_MMC_STAT_END_OF_DATA)
758 if (status & OMAP_MMC_STAT_DATA_TOUT) {
759 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
762 host->data->error = -ETIMEDOUT;
767 if (status & OMAP_MMC_STAT_DATA_CRC) {
769 host->data->error = -EILSEQ;
770 dev_dbg(mmc_dev(host->mmc),
771 "data CRC error, bytes left %d\n",
772 host->total_bytes_left);
775 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
779 if (status & OMAP_MMC_STAT_CMD_TOUT) {
780 /* Timeouts are routine with some commands */
782 struct mmc_omap_slot *slot =
785 !mmc_omap_cover_is_open(slot))
786 dev_err(mmc_dev(host->mmc),
787 "command timeout (CMD%d)\n",
789 host->cmd->error = -ETIMEDOUT;
795 if (status & OMAP_MMC_STAT_CMD_CRC) {
797 dev_err(mmc_dev(host->mmc),
798 "command CRC error (CMD%d, arg 0x%08x)\n",
799 cmd, host->cmd->arg);
800 host->cmd->error = -EILSEQ;
804 dev_err(mmc_dev(host->mmc),
805 "command CRC error without cmd?\n");
808 if (status & OMAP_MMC_STAT_CARD_ERR) {
809 dev_dbg(mmc_dev(host->mmc),
810 "ignoring card status error (CMD%d)\n",
816 * NOTE: On 1610 the END_OF_CMD may come too early when
819 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
820 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
825 if (cmd_error && host->data) {
826 del_timer(&host->cmd_abort_timer);
828 OMAP_MMC_WRITE(host, IE, 0);
829 disable_irq_nosync(host->irq);
830 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
834 if (end_command && host->cmd)
835 mmc_omap_cmd_done(host, host->cmd);
836 if (host->data != NULL) {
838 mmc_omap_xfer_done(host, host->data);
839 else if (end_transfer)
840 mmc_omap_end_of_data(host, host->data);
846 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
849 struct mmc_omap_host *host = dev_get_drvdata(dev);
850 struct mmc_omap_slot *slot = host->slots[num];
852 BUG_ON(num >= host->nr_slots);
854 /* Other subsystems can call in here before we're initialised. */
855 if (host->nr_slots == 0 || !host->slots[num])
858 cover_open = mmc_omap_cover_is_open(slot);
859 if (cover_open != slot->cover_open) {
860 slot->cover_open = cover_open;
861 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
864 tasklet_hi_schedule(&slot->cover_tasklet);
867 static void mmc_omap_cover_timer(unsigned long arg)
869 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
870 tasklet_schedule(&slot->cover_tasklet);
873 static void mmc_omap_cover_handler(unsigned long param)
875 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
876 int cover_open = mmc_omap_cover_is_open(slot);
878 mmc_detect_change(slot->mmc, 0);
883 * If no card is inserted, we postpone polling until
884 * the cover has been closed.
886 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
889 mod_timer(&slot->cover_timer,
890 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
893 static void mmc_omap_dma_callback(void *priv)
895 struct mmc_omap_host *host = priv;
896 struct mmc_data *data = host->data;
898 /* If we got to the end of DMA, assume everything went well */
899 data->bytes_xfered += data->blocks * data->blksz;
901 mmc_omap_dma_done(host, data);
904 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
908 reg = OMAP_MMC_READ(host, SDIO);
910 OMAP_MMC_WRITE(host, SDIO, reg);
911 /* Set maximum timeout */
912 OMAP_MMC_WRITE(host, CTO, 0xff);
915 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
917 unsigned int timeout, cycle_ns;
920 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
921 timeout = req->data->timeout_ns / cycle_ns;
922 timeout += req->data->timeout_clks;
924 /* Check if we need to use timeout multiplier register */
925 reg = OMAP_MMC_READ(host, SDIO);
926 if (timeout > 0xffff) {
931 OMAP_MMC_WRITE(host, SDIO, reg);
932 OMAP_MMC_WRITE(host, DTO, timeout);
936 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
938 struct mmc_data *data = req->data;
939 int i, use_dma, block_size;
944 OMAP_MMC_WRITE(host, BLEN, 0);
945 OMAP_MMC_WRITE(host, NBLK, 0);
946 OMAP_MMC_WRITE(host, BUF, 0);
947 host->dma_in_use = 0;
948 set_cmd_timeout(host, req);
952 block_size = data->blksz;
954 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
955 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
956 set_data_timeout(host, req);
958 /* cope with calling layer confusion; it issues "single
959 * block" writes using multi-block scatterlists.
961 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
963 /* Only do DMA for entire blocks */
964 use_dma = host->use_dma;
966 for (i = 0; i < sg_len; i++) {
967 if ((data->sg[i].length % block_size) != 0) {
976 enum dma_data_direction dma_data_dir;
977 struct dma_async_tx_descriptor *tx;
983 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
984 * and 24xx. Use 16 or 32 word frames when the
985 * blocksize is at least that large. Blocksize is
986 * usually 512 bytes; but not for some SD reads.
988 burst = cpu_is_omap15xx() ? 32 : 64;
989 if (burst > data->blksz)
994 if (data->flags & MMC_DATA_WRITE) {
996 bp = &host->dma_tx_burst;
997 buf = 0x0f80 | (burst - 1) << 0;
998 dma_data_dir = DMA_TO_DEVICE;
1001 bp = &host->dma_rx_burst;
1002 buf = 0x800f | (burst - 1) << 8;
1003 dma_data_dir = DMA_FROM_DEVICE;
1009 /* Only reconfigure if we have a different burst size */
1011 struct dma_slave_config cfg;
1013 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1014 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1015 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1016 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1017 cfg.src_maxburst = burst;
1018 cfg.dst_maxburst = burst;
1020 if (dmaengine_slave_config(c, &cfg))
1026 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1028 if (host->sg_len == 0)
1031 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1032 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1033 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1037 OMAP_MMC_WRITE(host, BUF, buf);
1039 tx->callback = mmc_omap_dma_callback;
1040 tx->callback_param = host;
1041 dmaengine_submit(tx);
1042 host->brs_received = 0;
1044 host->dma_in_use = 1;
1049 /* Revert to PIO? */
1050 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1051 host->total_bytes_left = data->blocks * block_size;
1052 host->sg_len = sg_len;
1053 mmc_omap_sg_to_buf(host);
1054 host->dma_in_use = 0;
1057 static void mmc_omap_start_request(struct mmc_omap_host *host,
1058 struct mmc_request *req)
1060 BUG_ON(host->mrq != NULL);
1064 /* only touch fifo AFTER the controller readies it */
1065 mmc_omap_prepare_data(host, req);
1066 mmc_omap_start_command(host, req->cmd);
1067 if (host->dma_in_use) {
1068 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1069 host->dma_tx : host->dma_rx;
1071 dma_async_issue_pending(c);
1075 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1077 struct mmc_omap_slot *slot = mmc_priv(mmc);
1078 struct mmc_omap_host *host = slot->host;
1079 unsigned long flags;
1081 spin_lock_irqsave(&host->slot_lock, flags);
1082 if (host->mmc != NULL) {
1083 BUG_ON(slot->mrq != NULL);
1085 spin_unlock_irqrestore(&host->slot_lock, flags);
1089 spin_unlock_irqrestore(&host->slot_lock, flags);
1090 mmc_omap_select_slot(slot, 1);
1091 mmc_omap_start_request(host, req);
1094 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1097 struct mmc_omap_host *host;
1101 if (slot->pdata->set_power != NULL)
1102 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1105 if (cpu_is_omap24xx()) {
1109 w = OMAP_MMC_READ(host, CON);
1110 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1112 w = OMAP_MMC_READ(host, CON);
1113 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1118 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1120 struct mmc_omap_slot *slot = mmc_priv(mmc);
1121 struct mmc_omap_host *host = slot->host;
1122 int func_clk_rate = clk_get_rate(host->fclk);
1125 if (ios->clock == 0)
1128 dsor = func_clk_rate / ios->clock;
1132 if (func_clk_rate / dsor > ios->clock)
1138 slot->fclk_freq = func_clk_rate / dsor;
1140 if (ios->bus_width == MMC_BUS_WIDTH_4)
1146 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1148 struct mmc_omap_slot *slot = mmc_priv(mmc);
1149 struct mmc_omap_host *host = slot->host;
1153 mmc_omap_select_slot(slot, 0);
1155 dsor = mmc_omap_calc_divisor(mmc, ios);
1157 if (ios->vdd != slot->vdd)
1158 slot->vdd = ios->vdd;
1161 switch (ios->power_mode) {
1163 mmc_omap_set_power(slot, 0, ios->vdd);
1166 /* Cannot touch dsor yet, just power up MMC */
1167 mmc_omap_set_power(slot, 1, ios->vdd);
1170 mmc_omap_fclk_enable(host, 1);
1176 if (slot->bus_mode != ios->bus_mode) {
1177 if (slot->pdata->set_bus_mode != NULL)
1178 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1180 slot->bus_mode = ios->bus_mode;
1183 /* On insanely high arm_per frequencies something sometimes
1184 * goes somehow out of sync, and the POW bit is not being set,
1185 * which results in the while loop below getting stuck.
1186 * Writing to the CON register twice seems to do the trick. */
1187 for (i = 0; i < 2; i++)
1188 OMAP_MMC_WRITE(host, CON, dsor);
1189 slot->saved_con = dsor;
1190 if (ios->power_mode == MMC_POWER_ON) {
1191 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1194 /* Send clock cycles, poll completion */
1195 OMAP_MMC_WRITE(host, IE, 0);
1196 OMAP_MMC_WRITE(host, STAT, 0xffff);
1197 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1198 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1202 OMAP_MMC_WRITE(host, STAT, 1);
1206 mmc_omap_release_slot(slot, clk_enabled);
1209 static const struct mmc_host_ops mmc_omap_ops = {
1210 .request = mmc_omap_request,
1211 .set_ios = mmc_omap_set_ios,
1214 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1216 struct mmc_omap_slot *slot = NULL;
1217 struct mmc_host *mmc;
1220 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1224 slot = mmc_priv(mmc);
1228 slot->pdata = &host->pdata->slots[id];
1230 host->slots[id] = slot;
1233 if (host->pdata->slots[id].wires >= 4)
1234 mmc->caps |= MMC_CAP_4_BIT_DATA;
1236 mmc->ops = &mmc_omap_ops;
1237 mmc->f_min = 400000;
1239 if (cpu_class_is_omap2())
1240 mmc->f_max = 48000000;
1242 mmc->f_max = 24000000;
1243 if (host->pdata->max_freq)
1244 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1245 mmc->ocr_avail = slot->pdata->ocr_mask;
1247 /* Use scatterlist DMA to reduce per-transfer costs.
1248 * NOTE max_seg_size assumption that small blocks aren't
1249 * normally used (except e.g. for reading SD registers).
1252 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1253 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1254 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1255 mmc->max_seg_size = mmc->max_req_size;
1257 r = mmc_add_host(mmc);
1259 goto err_remove_host;
1261 if (slot->pdata->name != NULL) {
1262 r = device_create_file(&mmc->class_dev,
1263 &dev_attr_slot_name);
1265 goto err_remove_host;
1268 if (slot->pdata->get_cover_state != NULL) {
1269 r = device_create_file(&mmc->class_dev,
1270 &dev_attr_cover_switch);
1272 goto err_remove_slot_name;
1274 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1275 (unsigned long)slot);
1276 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1277 (unsigned long)slot);
1278 tasklet_schedule(&slot->cover_tasklet);
1283 err_remove_slot_name:
1284 if (slot->pdata->name != NULL)
1285 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1287 mmc_remove_host(mmc);
1292 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1294 struct mmc_host *mmc = slot->mmc;
1296 if (slot->pdata->name != NULL)
1297 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1298 if (slot->pdata->get_cover_state != NULL)
1299 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1301 tasklet_kill(&slot->cover_tasklet);
1302 del_timer_sync(&slot->cover_timer);
1303 flush_workqueue(slot->host->mmc_omap_wq);
1305 mmc_remove_host(mmc);
1309 static int __devinit mmc_omap_probe(struct platform_device *pdev)
1311 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1312 struct mmc_omap_host *host = NULL;
1313 struct resource *res;
1314 dma_cap_mask_t mask;
1319 if (pdata == NULL) {
1320 dev_err(&pdev->dev, "platform data missing\n");
1323 if (pdata->nr_slots == 0) {
1324 dev_err(&pdev->dev, "no slots\n");
1328 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329 irq = platform_get_irq(pdev, 0);
1330 if (res == NULL || irq < 0)
1333 res = request_mem_region(res->start, resource_size(res),
1338 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1341 goto err_free_mem_region;
1344 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1345 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1347 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1348 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1349 (unsigned long) host);
1351 spin_lock_init(&host->clk_lock);
1352 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1354 spin_lock_init(&host->dma_lock);
1355 spin_lock_init(&host->slot_lock);
1356 init_waitqueue_head(&host->slot_wq);
1358 host->pdata = pdata;
1359 host->dev = &pdev->dev;
1360 platform_set_drvdata(pdev, host);
1362 host->id = pdev->id;
1363 host->mem_res = res;
1367 host->phys_base = host->mem_res->start;
1368 host->virt_base = ioremap(res->start, resource_size(res));
1369 if (!host->virt_base)
1372 host->iclk = clk_get(&pdev->dev, "ick");
1373 if (IS_ERR(host->iclk)) {
1374 ret = PTR_ERR(host->iclk);
1375 goto err_free_mmc_host;
1377 clk_enable(host->iclk);
1379 host->fclk = clk_get(&pdev->dev, "fck");
1380 if (IS_ERR(host->fclk)) {
1381 ret = PTR_ERR(host->fclk);
1386 dma_cap_set(DMA_SLAVE, mask);
1388 host->dma_tx_burst = -1;
1389 host->dma_rx_burst = -1;
1391 if (cpu_is_omap24xx())
1392 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1394 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1395 host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1397 if (!host->dma_tx) {
1398 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1404 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1407 if (cpu_is_omap24xx())
1408 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1410 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1411 host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1413 if (!host->dma_rx) {
1414 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1420 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1424 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1428 if (pdata->init != NULL) {
1429 ret = pdata->init(&pdev->dev);
1434 host->nr_slots = pdata->nr_slots;
1435 host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1437 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1438 if (!host->mmc_omap_wq)
1439 goto err_plat_cleanup;
1441 for (i = 0; i < pdata->nr_slots; i++) {
1442 ret = mmc_omap_new_slot(host, i);
1445 mmc_omap_remove_slot(host->slots[i]);
1447 goto err_destroy_wq;
1454 destroy_workqueue(host->mmc_omap_wq);
1457 pdata->cleanup(&pdev->dev);
1459 free_irq(host->irq, host);
1462 dma_release_channel(host->dma_tx);
1464 dma_release_channel(host->dma_rx);
1465 clk_put(host->fclk);
1467 clk_disable(host->iclk);
1468 clk_put(host->iclk);
1470 iounmap(host->virt_base);
1473 err_free_mem_region:
1474 release_mem_region(res->start, resource_size(res));
1478 static int __devexit mmc_omap_remove(struct platform_device *pdev)
1480 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1483 platform_set_drvdata(pdev, NULL);
1485 BUG_ON(host == NULL);
1487 for (i = 0; i < host->nr_slots; i++)
1488 mmc_omap_remove_slot(host->slots[i]);
1490 if (host->pdata->cleanup)
1491 host->pdata->cleanup(&pdev->dev);
1493 mmc_omap_fclk_enable(host, 0);
1494 free_irq(host->irq, host);
1495 clk_put(host->fclk);
1496 clk_disable(host->iclk);
1497 clk_put(host->iclk);
1500 dma_release_channel(host->dma_tx);
1502 dma_release_channel(host->dma_rx);
1504 iounmap(host->virt_base);
1505 release_mem_region(pdev->resource[0].start,
1506 pdev->resource[0].end - pdev->resource[0].start + 1);
1507 destroy_workqueue(host->mmc_omap_wq);
1515 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1518 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1520 if (host == NULL || host->suspended)
1523 for (i = 0; i < host->nr_slots; i++) {
1524 struct mmc_omap_slot *slot;
1526 slot = host->slots[i];
1527 ret = mmc_suspend_host(slot->mmc);
1530 slot = host->slots[i];
1531 mmc_resume_host(slot->mmc);
1536 host->suspended = 1;
1540 static int mmc_omap_resume(struct platform_device *pdev)
1543 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1545 if (host == NULL || !host->suspended)
1548 for (i = 0; i < host->nr_slots; i++) {
1549 struct mmc_omap_slot *slot;
1550 slot = host->slots[i];
1551 ret = mmc_resume_host(slot->mmc);
1555 host->suspended = 0;
1560 #define mmc_omap_suspend NULL
1561 #define mmc_omap_resume NULL
1564 static struct platform_driver mmc_omap_driver = {
1565 .probe = mmc_omap_probe,
1566 .remove = __devexit_p(mmc_omap_remove),
1567 .suspend = mmc_omap_suspend,
1568 .resume = mmc_omap_resume,
1570 .name = DRIVER_NAME,
1571 .owner = THIS_MODULE,
1575 module_platform_driver(mmc_omap_driver);
1576 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1577 MODULE_LICENSE("GPL");
1578 MODULE_ALIAS("platform:" DRIVER_NAME);
1579 MODULE_AUTHOR("Juha Yrjölä");