2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/i2c/tps65010.h>
29 #include <linux/slab.h>
34 #include <plat/board.h>
36 #include <mach/gpio.h>
39 #include <plat/fpga.h>
41 #define OMAP_MMC_REG_CMD 0x00
42 #define OMAP_MMC_REG_ARGL 0x04
43 #define OMAP_MMC_REG_ARGH 0x08
44 #define OMAP_MMC_REG_CON 0x0c
45 #define OMAP_MMC_REG_STAT 0x10
46 #define OMAP_MMC_REG_IE 0x14
47 #define OMAP_MMC_REG_CTO 0x18
48 #define OMAP_MMC_REG_DTO 0x1c
49 #define OMAP_MMC_REG_DATA 0x20
50 #define OMAP_MMC_REG_BLEN 0x24
51 #define OMAP_MMC_REG_NBLK 0x28
52 #define OMAP_MMC_REG_BUF 0x2c
53 #define OMAP_MMC_REG_SDIO 0x34
54 #define OMAP_MMC_REG_REV 0x3c
55 #define OMAP_MMC_REG_RSP0 0x40
56 #define OMAP_MMC_REG_RSP1 0x44
57 #define OMAP_MMC_REG_RSP2 0x48
58 #define OMAP_MMC_REG_RSP3 0x4c
59 #define OMAP_MMC_REG_RSP4 0x50
60 #define OMAP_MMC_REG_RSP5 0x54
61 #define OMAP_MMC_REG_RSP6 0x58
62 #define OMAP_MMC_REG_RSP7 0x5c
63 #define OMAP_MMC_REG_IOSR 0x60
64 #define OMAP_MMC_REG_SYSC 0x64
65 #define OMAP_MMC_REG_SYSS 0x68
67 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71 #define OMAP_MMC_STAT_A_FULL (1 << 10)
72 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
77 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
81 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
87 #define OMAP_MMC_CMDTYPE_BC 0
88 #define OMAP_MMC_CMDTYPE_BCR 1
89 #define OMAP_MMC_CMDTYPE_AC 2
90 #define OMAP_MMC_CMDTYPE_ADTC 3
93 #define DRIVER_NAME "mmci-omap"
95 /* Specifies how often in millisecs to poll for card status changes
96 * when the cover switch is open */
97 #define OMAP_MMC_COVER_POLL_DELAY 500
101 struct mmc_omap_slot {
106 unsigned int fclk_freq;
109 struct tasklet_struct cover_tasklet;
110 struct timer_list cover_timer;
113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
119 struct mmc_omap_host {
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
130 struct resource *mem_res;
131 void __iomem *virt_base;
132 unsigned int phys_base;
134 unsigned char bus_mode;
135 unsigned char hw_bus_mode;
137 struct work_struct cmd_abort_work;
139 struct timer_list cmd_abort_timer;
141 struct work_struct slot_release_work;
142 struct mmc_omap_slot *next_slot;
143 struct work_struct send_stop_work;
144 struct mmc_data *stop_data;
149 u32 buffer_bytes_left;
150 u32 total_bytes_left;
153 unsigned brs_received:1, dma_done:1;
154 unsigned dma_is_read:1;
155 unsigned dma_in_use:1;
158 struct timer_list dma_timer;
161 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
162 struct mmc_omap_slot *current_slot;
163 spinlock_t slot_lock;
164 wait_queue_head_t slot_wq;
167 struct timer_list clk_timer;
168 spinlock_t clk_lock; /* for changing enabled state */
169 unsigned int fclk_enabled:1;
171 struct omap_mmc_platform_data *pdata;
174 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
176 unsigned long tick_ns;
178 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
179 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
184 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
188 spin_lock_irqsave(&host->clk_lock, flags);
189 if (host->fclk_enabled != enable) {
190 host->fclk_enabled = enable;
192 clk_enable(host->fclk);
194 clk_disable(host->fclk);
196 spin_unlock_irqrestore(&host->clk_lock, flags);
199 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
201 struct mmc_omap_host *host = slot->host;
206 spin_lock_irqsave(&host->slot_lock, flags);
207 while (host->mmc != NULL) {
208 spin_unlock_irqrestore(&host->slot_lock, flags);
209 wait_event(host->slot_wq, host->mmc == NULL);
210 spin_lock_irqsave(&host->slot_lock, flags);
212 host->mmc = slot->mmc;
213 spin_unlock_irqrestore(&host->slot_lock, flags);
215 del_timer(&host->clk_timer);
216 if (host->current_slot != slot || !claimed)
217 mmc_omap_fclk_offdelay(host->current_slot);
219 if (host->current_slot != slot) {
220 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
221 if (host->pdata->switch_slot != NULL)
222 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
223 host->current_slot = slot;
227 mmc_omap_fclk_enable(host, 1);
229 /* Doing the dummy read here seems to work around some bug
230 * at least in OMAP24xx silicon where the command would not
231 * start after writing the CMD register. Sigh. */
232 OMAP_MMC_READ(host, CON);
234 OMAP_MMC_WRITE(host, CON, slot->saved_con);
236 mmc_omap_fclk_enable(host, 0);
239 static void mmc_omap_start_request(struct mmc_omap_host *host,
240 struct mmc_request *req);
242 static void mmc_omap_slot_release_work(struct work_struct *work)
244 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
246 struct mmc_omap_slot *next_slot = host->next_slot;
247 struct mmc_request *rq;
249 host->next_slot = NULL;
250 mmc_omap_select_slot(next_slot, 1);
253 next_slot->mrq = NULL;
254 mmc_omap_start_request(host, rq);
257 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
259 struct mmc_omap_host *host = slot->host;
263 BUG_ON(slot == NULL || host->mmc == NULL);
266 /* Keeps clock running for at least 8 cycles on valid freq */
267 mod_timer(&host->clk_timer, jiffies + HZ/10);
269 del_timer(&host->clk_timer);
270 mmc_omap_fclk_offdelay(slot);
271 mmc_omap_fclk_enable(host, 0);
274 spin_lock_irqsave(&host->slot_lock, flags);
275 /* Check for any pending requests */
276 for (i = 0; i < host->nr_slots; i++) {
277 struct mmc_omap_slot *new_slot;
279 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
282 BUG_ON(host->next_slot != NULL);
283 new_slot = host->slots[i];
284 /* The current slot should not have a request in queue */
285 BUG_ON(new_slot == host->current_slot);
287 host->next_slot = new_slot;
288 host->mmc = new_slot->mmc;
289 spin_unlock_irqrestore(&host->slot_lock, flags);
290 schedule_work(&host->slot_release_work);
295 wake_up(&host->slot_wq);
296 spin_unlock_irqrestore(&host->slot_lock, flags);
300 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
302 if (slot->pdata->get_cover_state)
303 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
309 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
312 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
313 struct mmc_omap_slot *slot = mmc_priv(mmc);
315 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
319 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
322 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
325 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
326 struct mmc_omap_slot *slot = mmc_priv(mmc);
328 return sprintf(buf, "%s\n", slot->pdata->name);
331 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
334 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
345 /* Our hardware needs to know exact type */
346 switch (mmc_resp_type(cmd)) {
351 /* resp 1, 1b, 6, 7 */
361 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
365 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
366 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
367 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
368 cmdtype = OMAP_MMC_CMDTYPE_BC;
369 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
370 cmdtype = OMAP_MMC_CMDTYPE_BCR;
372 cmdtype = OMAP_MMC_CMDTYPE_AC;
375 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
377 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
380 if (cmd->flags & MMC_RSP_BUSY)
383 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
386 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
388 OMAP_MMC_WRITE(host, CTO, 200);
389 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
390 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
391 OMAP_MMC_WRITE(host, IE,
392 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
393 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
394 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
395 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
396 OMAP_MMC_STAT_END_OF_DATA);
397 OMAP_MMC_WRITE(host, CMD, cmdreg);
401 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
404 enum dma_data_direction dma_data_dir;
406 BUG_ON(host->dma_ch < 0);
408 omap_stop_dma(host->dma_ch);
409 /* Release DMA channel lazily */
410 mod_timer(&host->dma_timer, jiffies + HZ);
411 if (data->flags & MMC_DATA_WRITE)
412 dma_data_dir = DMA_TO_DEVICE;
414 dma_data_dir = DMA_FROM_DEVICE;
415 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
419 static void mmc_omap_send_stop_work(struct work_struct *work)
421 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
423 struct mmc_omap_slot *slot = host->current_slot;
424 struct mmc_data *data = host->stop_data;
425 unsigned long tick_ns;
427 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
430 mmc_omap_start_command(host, data->stop);
434 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
436 if (host->dma_in_use)
437 mmc_omap_release_dma(host, data, data->error);
442 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
443 * dozens of requests until the card finishes writing data.
444 * It'd be cheaper to just wait till an EOFB interrupt arrives...
448 struct mmc_host *mmc;
452 mmc_omap_release_slot(host->current_slot, 1);
453 mmc_request_done(mmc, data->mrq);
457 host->stop_data = data;
458 schedule_work(&host->send_stop_work);
462 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
464 struct mmc_omap_slot *slot = host->current_slot;
465 unsigned int restarts, passes, timeout;
468 /* Sending abort takes 80 clocks. Have some extra and round up */
469 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
471 while (restarts < maxloops) {
472 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
473 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
476 while (passes < timeout) {
477 stat = OMAP_MMC_READ(host, STAT);
478 if (stat & OMAP_MMC_STAT_END_OF_CMD)
487 OMAP_MMC_WRITE(host, STAT, stat);
491 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
493 if (host->dma_in_use)
494 mmc_omap_release_dma(host, data, 1);
499 mmc_omap_send_abort(host, 10000);
503 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
508 if (!host->dma_in_use) {
509 mmc_omap_xfer_done(host, data);
513 spin_lock_irqsave(&host->dma_lock, flags);
517 host->brs_received = 1;
518 spin_unlock_irqrestore(&host->dma_lock, flags);
520 mmc_omap_xfer_done(host, data);
524 mmc_omap_dma_timer(unsigned long data)
526 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
528 BUG_ON(host->dma_ch < 0);
529 omap_free_dma(host->dma_ch);
534 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
540 spin_lock_irqsave(&host->dma_lock, flags);
541 if (host->brs_received)
545 spin_unlock_irqrestore(&host->dma_lock, flags);
547 mmc_omap_xfer_done(host, data);
551 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
555 del_timer(&host->cmd_abort_timer);
557 if (cmd->flags & MMC_RSP_PRESENT) {
558 if (cmd->flags & MMC_RSP_136) {
559 /* response type 2 */
561 OMAP_MMC_READ(host, RSP0) |
562 (OMAP_MMC_READ(host, RSP1) << 16);
564 OMAP_MMC_READ(host, RSP2) |
565 (OMAP_MMC_READ(host, RSP3) << 16);
567 OMAP_MMC_READ(host, RSP4) |
568 (OMAP_MMC_READ(host, RSP5) << 16);
570 OMAP_MMC_READ(host, RSP6) |
571 (OMAP_MMC_READ(host, RSP7) << 16);
573 /* response types 1, 1b, 3, 4, 5, 6 */
575 OMAP_MMC_READ(host, RSP6) |
576 (OMAP_MMC_READ(host, RSP7) << 16);
580 if (host->data == NULL || cmd->error) {
581 struct mmc_host *mmc;
583 if (host->data != NULL)
584 mmc_omap_abort_xfer(host, host->data);
587 mmc_omap_release_slot(host->current_slot, 1);
588 mmc_request_done(mmc, cmd->mrq);
593 * Abort stuck command. Can occur when card is removed while it is being
596 static void mmc_omap_abort_command(struct work_struct *work)
598 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
602 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
605 if (host->cmd->error == 0)
606 host->cmd->error = -ETIMEDOUT;
608 if (host->data == NULL) {
609 struct mmc_command *cmd;
610 struct mmc_host *mmc;
614 mmc_omap_send_abort(host, 10000);
618 mmc_omap_release_slot(host->current_slot, 1);
619 mmc_request_done(mmc, cmd->mrq);
621 mmc_omap_cmd_done(host, host->cmd);
624 enable_irq(host->irq);
628 mmc_omap_cmd_timer(unsigned long data)
630 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
633 spin_lock_irqsave(&host->slot_lock, flags);
634 if (host->cmd != NULL && !host->abort) {
635 OMAP_MMC_WRITE(host, IE, 0);
636 disable_irq(host->irq);
638 schedule_work(&host->cmd_abort_work);
640 spin_unlock_irqrestore(&host->slot_lock, flags);
645 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
647 struct scatterlist *sg;
649 sg = host->data->sg + host->sg_idx;
650 host->buffer_bytes_left = sg->length;
651 host->buffer = sg_virt(sg);
652 if (host->buffer_bytes_left > host->total_bytes_left)
653 host->buffer_bytes_left = host->total_bytes_left;
657 mmc_omap_clk_timer(unsigned long data)
659 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
661 mmc_omap_fclk_enable(host, 0);
666 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
670 if (host->buffer_bytes_left == 0) {
672 BUG_ON(host->sg_idx == host->sg_len);
673 mmc_omap_sg_to_buf(host);
676 if (n > host->buffer_bytes_left)
677 n = host->buffer_bytes_left;
678 host->buffer_bytes_left -= n;
679 host->total_bytes_left -= n;
680 host->data->bytes_xfered += n;
683 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
685 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
689 static inline void mmc_omap_report_irq(u16 status)
691 static const char *mmc_omap_status_bits[] = {
692 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
693 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
697 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
698 if (status & (1 << i)) {
701 printk("%s", mmc_omap_status_bits[i]);
706 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
708 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
712 int transfer_error, cmd_error;
714 if (host->cmd == NULL && host->data == NULL) {
715 status = OMAP_MMC_READ(host, STAT);
716 dev_info(mmc_dev(host->slots[0]->mmc),
717 "Spurious IRQ 0x%04x\n", status);
719 OMAP_MMC_WRITE(host, STAT, status);
720 OMAP_MMC_WRITE(host, IE, 0);
730 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
733 OMAP_MMC_WRITE(host, STAT, status);
734 if (host->cmd != NULL)
735 cmd = host->cmd->opcode;
738 #ifdef CONFIG_MMC_DEBUG
739 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
741 mmc_omap_report_irq(status);
744 if (host->total_bytes_left) {
745 if ((status & OMAP_MMC_STAT_A_FULL) ||
746 (status & OMAP_MMC_STAT_END_OF_DATA))
747 mmc_omap_xfer_data(host, 0);
748 if (status & OMAP_MMC_STAT_A_EMPTY)
749 mmc_omap_xfer_data(host, 1);
752 if (status & OMAP_MMC_STAT_END_OF_DATA)
755 if (status & OMAP_MMC_STAT_DATA_TOUT) {
756 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
759 host->data->error = -ETIMEDOUT;
764 if (status & OMAP_MMC_STAT_DATA_CRC) {
766 host->data->error = -EILSEQ;
767 dev_dbg(mmc_dev(host->mmc),
768 "data CRC error, bytes left %d\n",
769 host->total_bytes_left);
772 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
776 if (status & OMAP_MMC_STAT_CMD_TOUT) {
777 /* Timeouts are routine with some commands */
779 struct mmc_omap_slot *slot =
782 !mmc_omap_cover_is_open(slot))
783 dev_err(mmc_dev(host->mmc),
784 "command timeout (CMD%d)\n",
786 host->cmd->error = -ETIMEDOUT;
792 if (status & OMAP_MMC_STAT_CMD_CRC) {
794 dev_err(mmc_dev(host->mmc),
795 "command CRC error (CMD%d, arg 0x%08x)\n",
796 cmd, host->cmd->arg);
797 host->cmd->error = -EILSEQ;
801 dev_err(mmc_dev(host->mmc),
802 "command CRC error without cmd?\n");
805 if (status & OMAP_MMC_STAT_CARD_ERR) {
806 dev_dbg(mmc_dev(host->mmc),
807 "ignoring card status error (CMD%d)\n",
813 * NOTE: On 1610 the END_OF_CMD may come too early when
816 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
817 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
822 if (cmd_error && host->data) {
823 del_timer(&host->cmd_abort_timer);
825 OMAP_MMC_WRITE(host, IE, 0);
826 disable_irq_nosync(host->irq);
827 schedule_work(&host->cmd_abort_work);
832 mmc_omap_cmd_done(host, host->cmd);
833 if (host->data != NULL) {
835 mmc_omap_xfer_done(host, host->data);
836 else if (end_transfer)
837 mmc_omap_end_of_data(host, host->data);
843 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
846 struct mmc_omap_host *host = dev_get_drvdata(dev);
847 struct mmc_omap_slot *slot = host->slots[num];
849 BUG_ON(num >= host->nr_slots);
851 /* Other subsystems can call in here before we're initialised. */
852 if (host->nr_slots == 0 || !host->slots[num])
855 cover_open = mmc_omap_cover_is_open(slot);
856 if (cover_open != slot->cover_open) {
857 slot->cover_open = cover_open;
858 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
861 tasklet_hi_schedule(&slot->cover_tasklet);
864 static void mmc_omap_cover_timer(unsigned long arg)
866 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
867 tasklet_schedule(&slot->cover_tasklet);
870 static void mmc_omap_cover_handler(unsigned long param)
872 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
873 int cover_open = mmc_omap_cover_is_open(slot);
875 mmc_detect_change(slot->mmc, 0);
880 * If no card is inserted, we postpone polling until
881 * the cover has been closed.
883 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
886 mod_timer(&slot->cover_timer,
887 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
890 /* Prepare to transfer the next segment of a scatterlist */
892 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
894 int dma_ch = host->dma_ch;
895 unsigned long data_addr;
898 struct scatterlist *sg = &data->sg[host->sg_idx];
903 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
905 count = sg_dma_len(sg);
907 if ((data->blocks == 1) && (count > data->blksz))
910 host->dma_len = count;
912 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
913 * Use 16 or 32 word frames when the blocksize is at least that large.
914 * Blocksize is usually 512 bytes; but not for some SD reads.
916 if (cpu_is_omap15xx() && frame > 32)
923 if (!(data->flags & MMC_DATA_WRITE)) {
924 buf = 0x800f | ((frame - 1) << 8);
926 if (cpu_class_is_omap1()) {
927 src_port = OMAP_DMA_PORT_TIPB;
928 dst_port = OMAP_DMA_PORT_EMIFF;
930 if (cpu_is_omap24xx())
931 sync_dev = OMAP24XX_DMA_MMC1_RX;
933 omap_set_dma_src_params(dma_ch, src_port,
934 OMAP_DMA_AMODE_CONSTANT,
936 omap_set_dma_dest_params(dma_ch, dst_port,
937 OMAP_DMA_AMODE_POST_INC,
938 sg_dma_address(sg), 0, 0);
939 omap_set_dma_dest_data_pack(dma_ch, 1);
940 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
942 buf = 0x0f80 | ((frame - 1) << 0);
944 if (cpu_class_is_omap1()) {
945 src_port = OMAP_DMA_PORT_EMIFF;
946 dst_port = OMAP_DMA_PORT_TIPB;
948 if (cpu_is_omap24xx())
949 sync_dev = OMAP24XX_DMA_MMC1_TX;
951 omap_set_dma_dest_params(dma_ch, dst_port,
952 OMAP_DMA_AMODE_CONSTANT,
954 omap_set_dma_src_params(dma_ch, src_port,
955 OMAP_DMA_AMODE_POST_INC,
956 sg_dma_address(sg), 0, 0);
957 omap_set_dma_src_data_pack(dma_ch, 1);
958 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
961 /* Max limit for DMA frame count is 0xffff */
962 BUG_ON(count > 0xffff);
964 OMAP_MMC_WRITE(host, BUF, buf);
965 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
966 frame, count, OMAP_DMA_SYNC_FRAME,
970 /* A scatterlist segment completed */
971 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
973 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
974 struct mmc_data *mmcdat = host->data;
976 if (unlikely(host->dma_ch < 0)) {
977 dev_err(mmc_dev(host->mmc),
978 "DMA callback while DMA not enabled\n");
981 /* FIXME: We really should do something to _handle_ the errors */
982 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
983 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
986 if (ch_status & OMAP_DMA_DROP_IRQ) {
987 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
990 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
993 mmcdat->bytes_xfered += host->dma_len;
995 if (host->sg_idx < host->sg_len) {
996 mmc_omap_prepare_dma(host, host->data);
997 omap_start_dma(host->dma_ch);
999 mmc_omap_dma_done(host, host->data);
1002 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
1004 const char *dma_dev_name;
1005 int sync_dev, dma_ch, is_read, r;
1007 is_read = !(data->flags & MMC_DATA_WRITE);
1008 del_timer_sync(&host->dma_timer);
1009 if (host->dma_ch >= 0) {
1010 if (is_read == host->dma_is_read)
1012 omap_free_dma(host->dma_ch);
1017 if (host->id == 0) {
1018 sync_dev = OMAP_DMA_MMC_RX;
1019 dma_dev_name = "MMC1 read";
1021 sync_dev = OMAP_DMA_MMC2_RX;
1022 dma_dev_name = "MMC2 read";
1025 if (host->id == 0) {
1026 sync_dev = OMAP_DMA_MMC_TX;
1027 dma_dev_name = "MMC1 write";
1029 sync_dev = OMAP_DMA_MMC2_TX;
1030 dma_dev_name = "MMC2 write";
1033 r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb,
1036 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
1039 host->dma_ch = dma_ch;
1040 host->dma_is_read = is_read;
1045 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1049 reg = OMAP_MMC_READ(host, SDIO);
1051 OMAP_MMC_WRITE(host, SDIO, reg);
1052 /* Set maximum timeout */
1053 OMAP_MMC_WRITE(host, CTO, 0xff);
1056 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
1058 unsigned int timeout, cycle_ns;
1061 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
1062 timeout = req->data->timeout_ns / cycle_ns;
1063 timeout += req->data->timeout_clks;
1065 /* Check if we need to use timeout multiplier register */
1066 reg = OMAP_MMC_READ(host, SDIO);
1067 if (timeout > 0xffff) {
1072 OMAP_MMC_WRITE(host, SDIO, reg);
1073 OMAP_MMC_WRITE(host, DTO, timeout);
1077 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1079 struct mmc_data *data = req->data;
1080 int i, use_dma, block_size;
1085 OMAP_MMC_WRITE(host, BLEN, 0);
1086 OMAP_MMC_WRITE(host, NBLK, 0);
1087 OMAP_MMC_WRITE(host, BUF, 0);
1088 host->dma_in_use = 0;
1089 set_cmd_timeout(host, req);
1093 block_size = data->blksz;
1095 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
1096 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
1097 set_data_timeout(host, req);
1099 /* cope with calling layer confusion; it issues "single
1100 * block" writes using multi-block scatterlists.
1102 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1104 /* Only do DMA for entire blocks */
1105 use_dma = host->use_dma;
1107 for (i = 0; i < sg_len; i++) {
1108 if ((data->sg[i].length % block_size) != 0) {
1117 if (mmc_omap_get_dma_channel(host, data) == 0) {
1118 enum dma_data_direction dma_data_dir;
1120 if (data->flags & MMC_DATA_WRITE)
1121 dma_data_dir = DMA_TO_DEVICE;
1123 dma_data_dir = DMA_FROM_DEVICE;
1125 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1126 sg_len, dma_data_dir);
1127 host->total_bytes_left = 0;
1128 mmc_omap_prepare_dma(host, req->data);
1129 host->brs_received = 0;
1131 host->dma_in_use = 1;
1136 /* Revert to PIO? */
1138 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1139 host->total_bytes_left = data->blocks * block_size;
1140 host->sg_len = sg_len;
1141 mmc_omap_sg_to_buf(host);
1142 host->dma_in_use = 0;
1146 static void mmc_omap_start_request(struct mmc_omap_host *host,
1147 struct mmc_request *req)
1149 BUG_ON(host->mrq != NULL);
1153 /* only touch fifo AFTER the controller readies it */
1154 mmc_omap_prepare_data(host, req);
1155 mmc_omap_start_command(host, req->cmd);
1156 if (host->dma_in_use)
1157 omap_start_dma(host->dma_ch);
1158 BUG_ON(irqs_disabled());
1161 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1163 struct mmc_omap_slot *slot = mmc_priv(mmc);
1164 struct mmc_omap_host *host = slot->host;
1165 unsigned long flags;
1167 spin_lock_irqsave(&host->slot_lock, flags);
1168 if (host->mmc != NULL) {
1169 BUG_ON(slot->mrq != NULL);
1171 spin_unlock_irqrestore(&host->slot_lock, flags);
1175 spin_unlock_irqrestore(&host->slot_lock, flags);
1176 mmc_omap_select_slot(slot, 1);
1177 mmc_omap_start_request(host, req);
1180 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1183 struct mmc_omap_host *host;
1187 if (slot->pdata->set_power != NULL)
1188 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1191 if (cpu_is_omap24xx()) {
1195 w = OMAP_MMC_READ(host, CON);
1196 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1198 w = OMAP_MMC_READ(host, CON);
1199 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1204 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1206 struct mmc_omap_slot *slot = mmc_priv(mmc);
1207 struct mmc_omap_host *host = slot->host;
1208 int func_clk_rate = clk_get_rate(host->fclk);
1211 if (ios->clock == 0)
1214 dsor = func_clk_rate / ios->clock;
1218 if (func_clk_rate / dsor > ios->clock)
1224 slot->fclk_freq = func_clk_rate / dsor;
1226 if (ios->bus_width == MMC_BUS_WIDTH_4)
1232 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1234 struct mmc_omap_slot *slot = mmc_priv(mmc);
1235 struct mmc_omap_host *host = slot->host;
1239 mmc_omap_select_slot(slot, 0);
1241 dsor = mmc_omap_calc_divisor(mmc, ios);
1243 if (ios->vdd != slot->vdd)
1244 slot->vdd = ios->vdd;
1247 switch (ios->power_mode) {
1249 mmc_omap_set_power(slot, 0, ios->vdd);
1252 /* Cannot touch dsor yet, just power up MMC */
1253 mmc_omap_set_power(slot, 1, ios->vdd);
1256 mmc_omap_fclk_enable(host, 1);
1262 if (slot->bus_mode != ios->bus_mode) {
1263 if (slot->pdata->set_bus_mode != NULL)
1264 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1266 slot->bus_mode = ios->bus_mode;
1269 /* On insanely high arm_per frequencies something sometimes
1270 * goes somehow out of sync, and the POW bit is not being set,
1271 * which results in the while loop below getting stuck.
1272 * Writing to the CON register twice seems to do the trick. */
1273 for (i = 0; i < 2; i++)
1274 OMAP_MMC_WRITE(host, CON, dsor);
1275 slot->saved_con = dsor;
1276 if (ios->power_mode == MMC_POWER_ON) {
1277 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1280 /* Send clock cycles, poll completion */
1281 OMAP_MMC_WRITE(host, IE, 0);
1282 OMAP_MMC_WRITE(host, STAT, 0xffff);
1283 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1284 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1288 OMAP_MMC_WRITE(host, STAT, 1);
1292 mmc_omap_release_slot(slot, clk_enabled);
1295 static const struct mmc_host_ops mmc_omap_ops = {
1296 .request = mmc_omap_request,
1297 .set_ios = mmc_omap_set_ios,
1300 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1302 struct mmc_omap_slot *slot = NULL;
1303 struct mmc_host *mmc;
1306 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1310 slot = mmc_priv(mmc);
1314 slot->pdata = &host->pdata->slots[id];
1316 host->slots[id] = slot;
1319 if (host->pdata->slots[id].wires >= 4)
1320 mmc->caps |= MMC_CAP_4_BIT_DATA;
1322 mmc->ops = &mmc_omap_ops;
1323 mmc->f_min = 400000;
1325 if (cpu_class_is_omap2())
1326 mmc->f_max = 48000000;
1328 mmc->f_max = 24000000;
1329 if (host->pdata->max_freq)
1330 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1331 mmc->ocr_avail = slot->pdata->ocr_mask;
1333 /* Use scatterlist DMA to reduce per-transfer costs.
1334 * NOTE max_seg_size assumption that small blocks aren't
1335 * normally used (except e.g. for reading SD registers).
1337 mmc->max_phys_segs = 32;
1338 mmc->max_hw_segs = 32;
1339 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1340 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1341 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1342 mmc->max_seg_size = mmc->max_req_size;
1344 r = mmc_add_host(mmc);
1346 goto err_remove_host;
1348 if (slot->pdata->name != NULL) {
1349 r = device_create_file(&mmc->class_dev,
1350 &dev_attr_slot_name);
1352 goto err_remove_host;
1355 if (slot->pdata->get_cover_state != NULL) {
1356 r = device_create_file(&mmc->class_dev,
1357 &dev_attr_cover_switch);
1359 goto err_remove_slot_name;
1361 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1362 (unsigned long)slot);
1363 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1364 (unsigned long)slot);
1365 tasklet_schedule(&slot->cover_tasklet);
1370 err_remove_slot_name:
1371 if (slot->pdata->name != NULL)
1372 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1374 mmc_remove_host(mmc);
1379 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1381 struct mmc_host *mmc = slot->mmc;
1383 if (slot->pdata->name != NULL)
1384 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1385 if (slot->pdata->get_cover_state != NULL)
1386 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1388 tasklet_kill(&slot->cover_tasklet);
1389 del_timer_sync(&slot->cover_timer);
1390 flush_scheduled_work();
1392 mmc_remove_host(mmc);
1396 static int __init mmc_omap_probe(struct platform_device *pdev)
1398 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1399 struct mmc_omap_host *host = NULL;
1400 struct resource *res;
1404 if (pdata == NULL) {
1405 dev_err(&pdev->dev, "platform data missing\n");
1408 if (pdata->nr_slots == 0) {
1409 dev_err(&pdev->dev, "no slots\n");
1413 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1414 irq = platform_get_irq(pdev, 0);
1415 if (res == NULL || irq < 0)
1418 res = request_mem_region(res->start, res->end - res->start + 1,
1423 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1426 goto err_free_mem_region;
1429 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1430 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1432 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1433 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1434 (unsigned long) host);
1436 spin_lock_init(&host->clk_lock);
1437 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1439 spin_lock_init(&host->dma_lock);
1440 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1441 spin_lock_init(&host->slot_lock);
1442 init_waitqueue_head(&host->slot_wq);
1444 host->pdata = pdata;
1445 host->dev = &pdev->dev;
1446 platform_set_drvdata(pdev, host);
1448 host->id = pdev->id;
1449 host->mem_res = res;
1453 host->dev->dma_mask = &pdata->dma_mask;
1457 host->phys_base = host->mem_res->start;
1458 host->virt_base = ioremap(res->start, res->end - res->start + 1);
1459 if (!host->virt_base)
1462 host->iclk = clk_get(&pdev->dev, "ick");
1463 if (IS_ERR(host->iclk)) {
1464 ret = PTR_ERR(host->iclk);
1465 goto err_free_mmc_host;
1467 clk_enable(host->iclk);
1469 host->fclk = clk_get(&pdev->dev, "fck");
1470 if (IS_ERR(host->fclk)) {
1471 ret = PTR_ERR(host->fclk);
1475 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1479 if (pdata->init != NULL) {
1480 ret = pdata->init(&pdev->dev);
1485 host->nr_slots = pdata->nr_slots;
1486 for (i = 0; i < pdata->nr_slots; i++) {
1487 ret = mmc_omap_new_slot(host, i);
1490 mmc_omap_remove_slot(host->slots[i]);
1492 goto err_plat_cleanup;
1500 pdata->cleanup(&pdev->dev);
1502 free_irq(host->irq, host);
1504 clk_put(host->fclk);
1506 clk_disable(host->iclk);
1507 clk_put(host->iclk);
1509 iounmap(host->virt_base);
1512 err_free_mem_region:
1513 release_mem_region(res->start, res->end - res->start + 1);
1517 static int mmc_omap_remove(struct platform_device *pdev)
1519 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1522 platform_set_drvdata(pdev, NULL);
1524 BUG_ON(host == NULL);
1526 for (i = 0; i < host->nr_slots; i++)
1527 mmc_omap_remove_slot(host->slots[i]);
1529 if (host->pdata->cleanup)
1530 host->pdata->cleanup(&pdev->dev);
1532 mmc_omap_fclk_enable(host, 0);
1533 free_irq(host->irq, host);
1534 clk_put(host->fclk);
1535 clk_disable(host->iclk);
1536 clk_put(host->iclk);
1538 iounmap(host->virt_base);
1539 release_mem_region(pdev->resource[0].start,
1540 pdev->resource[0].end - pdev->resource[0].start + 1);
1548 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1551 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1553 if (host == NULL || host->suspended)
1556 for (i = 0; i < host->nr_slots; i++) {
1557 struct mmc_omap_slot *slot;
1559 slot = host->slots[i];
1560 ret = mmc_suspend_host(slot->mmc, mesg);
1563 slot = host->slots[i];
1564 mmc_resume_host(slot->mmc);
1569 host->suspended = 1;
1573 static int mmc_omap_resume(struct platform_device *pdev)
1576 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1578 if (host == NULL || !host->suspended)
1581 for (i = 0; i < host->nr_slots; i++) {
1582 struct mmc_omap_slot *slot;
1583 slot = host->slots[i];
1584 ret = mmc_resume_host(slot->mmc);
1588 host->suspended = 0;
1593 #define mmc_omap_suspend NULL
1594 #define mmc_omap_resume NULL
1597 static struct platform_driver mmc_omap_driver = {
1598 .remove = mmc_omap_remove,
1599 .suspend = mmc_omap_suspend,
1600 .resume = mmc_omap_resume,
1602 .name = DRIVER_NAME,
1603 .owner = THIS_MODULE,
1607 static int __init mmc_omap_init(void)
1609 return platform_driver_probe(&mmc_omap_driver, mmc_omap_probe);
1612 static void __exit mmc_omap_exit(void)
1614 platform_driver_unregister(&mmc_omap_driver);
1617 module_init(mmc_omap_init);
1618 module_exit(mmc_omap_exit);
1620 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1621 MODULE_LICENSE("GPL");
1622 MODULE_ALIAS("platform:" DRIVER_NAME);
1623 MODULE_AUTHOR("Juha Yrjölä");