drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVS_MASK               0x00000E00
  60 #define SDVSCLR                 0xFFFFF1FF
  61 #define SDVSDET                 0x00000400
  62 #define AUTOIDLE                0x1
  63 #define SDBP                    (1 << 8)
  64 #define DTO                     0xe
  65 #define ICE                     0x1
  66 #define ICS                     0x2
  67 #define CEN                     (1 << 2)
  68 #define CLKD_MASK               0x0000FFC0
  69 #define CLKD_SHIFT              6
  70 #define DTO_MASK                0x000F0000
  71 #define DTO_SHIFT               16
  72 #define INT_EN_MASK             0x307F0033
  73 #define INIT_STREAM             (1 << 1)
  74 #define DP_SELECT               (1 << 21)
  75 #define DDIR                    (1 << 4)
  76 #define DMA_EN                  0x1
  77 #define MSBS                    (1 << 5)
  78 #define BCE                     (1 << 1)
  79 #define FOUR_BIT                (1 << 1)
  80 #define DW8                     (1 << 5)
  81 #define CC                      0x1
  82 #define TC                      0x02
  83 #define OD                      0x1
  84 #define ERR                     (1 << 15)
  85 #define CMD_TIMEOUT             (1 << 16)
  86 #define DATA_TIMEOUT            (1 << 20)
  87 #define CMD_CRC                 (1 << 17)
  88 #define DATA_CRC                (1 << 21)
  89 #define CARD_ERR                (1 << 28)
  90 #define STAT_CLEAR              0xFFFFFFFF
  91 #define INIT_STREAM_CMD         0x00000000
  92 #define DUAL_VOLT_OCR_BIT       7
  93 #define SRC                     (1 << 25)
  94 #define SRD                     (1 << 26)
  95
  96 /*
  97  * FIXME: Most likely all the data using these _DEVID defines should come
  98  * from the platform_data, or implemented in controller and slot specific
  99  * functions.
 100  */
 101 #define OMAP_MMC1_DEVID         0
 102 #define OMAP_MMC2_DEVID         1
 103 #define OMAP_MMC3_DEVID         2
 104
 105 #define MMC_TIMEOUT_MS          20
 106 #define OMAP_MMC_MASTER_CLOCK   96000000
 107 #define DRIVER_NAME             "mmci-omap-hs"
 108
 109 /*
 110  * One controller can have multiple slots, like on some omap boards using
 111  * omap.c controller driver. Luckily this is not currently done on any known
 112  * omap_hsmmc.c device.
 113  */
 114 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 115
 116 /*
 117  * MMC Host controller read/write API's
 118  */
 119 #define OMAP_HSMMC_READ(base, reg)      \
 120         __raw_readl((base) + OMAP_HSMMC_##reg)
 121
 122 #define OMAP_HSMMC_WRITE(base, reg, val) \
 123         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 124
 125 struct mmc_omap_host {
 126         struct  device          *dev;
 127         struct  mmc_host        *mmc;
 128         struct  mmc_request     *mrq;
 129         struct  mmc_command     *cmd;
 130         struct  mmc_data        *data;
 131         struct  clk             *fclk;
 132         struct  clk             *iclk;
 133         struct  clk             *dbclk;
 134         struct  semaphore       sem;
 135         struct  work_struct     mmc_carddetect_work;
 136         void    __iomem         *base;
 137         resource_size_t         mapbase;
 138         unsigned int            id;
 139         unsigned int            dma_len;
 140         unsigned int            dma_sg_idx;
 141         unsigned char           bus_mode;
 142         u32                     *buffer;
 143         u32                     bytesleft;
 144         int                     suspended;
 145         int                     irq;
 146         int                     carddetect;
 147         int                     use_dma, dma_ch;
 148         int                     dma_line_tx, dma_line_rx;
 149         int                     slot_id;
 150         int                     dbclk_enabled;
 151         int                     response_busy;
 152         struct  omap_mmc_platform_data  *pdata;
 153 };
 154
 155 /*
 156  * Stop clock to the card
 157  */
 158 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 159 {
 160         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 161                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 162         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 163                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 164 }
 165
 166 /*
 167  * Send init stream sequence to card
 168  * before sending IDLE command
 169  */
 170 static void send_init_stream(struct mmc_omap_host *host)
 171 {
 172         int reg = 0;
 173         unsigned long timeout;
 174
 175         disable_irq(host->irq);
 176         OMAP_HSMMC_WRITE(host->base, CON,
 177                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 178         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 179
 180         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 181         while ((reg != CC) && time_before(jiffies, timeout))
 182                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 183
 184         OMAP_HSMMC_WRITE(host->base, CON,
 185                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 186         enable_irq(host->irq);
 187 }
 188
 189 static inline
 190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 191 {
 192         int r = 1;
 193
 194         if (host->pdata->slots[host->slot_id].get_cover_state)
 195                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 196                         host->slot_id);
 197         return r;
 198 }
 199
 200 static ssize_t
 201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 202                            char *buf)
 203 {
 204         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 205         struct mmc_omap_host *host = mmc_priv(mmc);
 206
 207         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 208                        "open");
 209 }
 210
 211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 212
 213 static ssize_t
 214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 215                         char *buf)
 216 {
 217         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 218         struct mmc_omap_host *host = mmc_priv(mmc);
 219         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 220
 221         return sprintf(buf, "%s\n", slot.name);
 222 }
 223
 224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 225
 226 /*
 227  * Configure the response type and send the cmd.
 228  */
 229 static void
 230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 231         struct mmc_data *data)
 232 {
 233         int cmdreg = 0, resptype = 0, cmdtype = 0;
 234
 235         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 236                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 237         host->cmd = cmd;
 238
 239         /*
 240          * Clear status bits and enable interrupts
 241          */
 242         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 243         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 244         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 245
 246         host->response_busy = 0;
 247         if (cmd->flags & MMC_RSP_PRESENT) {
 248                 if (cmd->flags & MMC_RSP_136)
 249                         resptype = 1;
 250                 else if (cmd->flags & MMC_RSP_BUSY) {
 251                         resptype = 3;
 252                         host->response_busy = 1;
 253                 } else
 254                         resptype = 2;
 255         }
 256
 257         /*
 258          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 259          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 260          * a val of 0x3, rest 0x0.
 261          */
 262         if (cmd == host->mrq->stop)
 263                 cmdtype = 0x3;
 264
 265         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 266
 267         if (data) {
 268                 cmdreg |= DP_SELECT | MSBS | BCE;
 269                 if (data->flags & MMC_DATA_READ)
 270                         cmdreg |= DDIR;
 271                 else
 272                         cmdreg &= ~(DDIR);
 273         }
 274
 275         if (host->use_dma)
 276                 cmdreg |= DMA_EN;
 277
 278         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 279         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 280 }
 281
 282 static int
 283 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 284 {
 285         if (data->flags & MMC_DATA_WRITE)
 286                 return DMA_TO_DEVICE;
 287         else
 288                 return DMA_FROM_DEVICE;
 289 }
 290
 291 /*
 292  * Notify the transfer complete to MMC core
 293  */
 294 static void
 295 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 296 {
 297         if (!data) {
 298                 struct mmc_request *mrq = host->mrq;
 299
 300                 host->mrq = NULL;
 301                 mmc_omap_fclk_lazy_disable(host);
 302                 mmc_request_done(host->mmc, mrq);
 303                 return;
 304         }
 305
 306         host->data = NULL;
 307
 308         if (host->use_dma && host->dma_ch != -1)
 309                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 310                         mmc_omap_get_dma_dir(host, data));
 311
 312         if (!data->error)
 313                 data->bytes_xfered += data->blocks * (data->blksz);
 314         else
 315                 data->bytes_xfered = 0;
 316
 317         if (!data->stop) {
 318                 host->mrq = NULL;
 319                 mmc_request_done(host->mmc, data->mrq);
 320                 return;
 321         }
 322         mmc_omap_start_command(host, data->stop, NULL);
 323 }
 324
 325 /*
 326  * Notify the core about command completion
 327  */
 328 static void
 329 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 330 {
 331         host->cmd = NULL;
 332
 333         if (cmd->flags & MMC_RSP_PRESENT) {
 334                 if (cmd->flags & MMC_RSP_136) {
 335                         /* response type 2 */
 336                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 337                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 338                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 339                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 340                 } else {
 341                         /* response types 1, 1b, 3, 4, 5, 6 */
 342                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 343                 }
 344         }
 345         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 346                 host->mrq = NULL;
 347                 mmc_request_done(host->mmc, cmd->mrq);
 348         }
 349 }
 350
 351 /*
 352  * DMA clean up for command errors
 353  */
 354 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 355 {
 356         host->data->error = errno;
 357
 358         if (host->use_dma && host->dma_ch != -1) {
 359                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 360                         mmc_omap_get_dma_dir(host, host->data));
 361                 omap_free_dma(host->dma_ch);
 362                 host->dma_ch = -1;
 363                 up(&host->sem);
 364         }
 365         host->data = NULL;
 366 }
 367
 368 /*
 369  * Readable error output
 370  */
 371 #ifdef CONFIG_MMC_DEBUG
 372 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 373 {
 374         /* --- means reserved bit without definition at documentation */
 375         static const char *mmc_omap_status_bits[] = {
 376                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 377                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 378                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 379                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 380         };
 381         char res[256];
 382         char *buf = res;
 383         int len, i;
 384
 385         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 386         buf += len;
 387
 388         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 389                 if (status & (1 << i)) {
 390                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 391                         buf += len;
 392                 }
 393
 394         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 395 }
 396 #endif  /* CONFIG_MMC_DEBUG */
 397
 398 /*
 399  * MMC controller internal state machines reset
 400  *
 401  * Used to reset command or data internal state machines, using respectively
 402  *  SRC or SRD bit of SYSCTL register
 403  * Can be called from interrupt context
 404  */
 405 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 406                 unsigned long bit)
 407 {
 408         unsigned long i = 0;
 409         unsigned long limit = (loops_per_jiffy *
 410                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 411
 412         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 413                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 414
 415         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 416                 (i++ < limit))
 417                 cpu_relax();
 418
 419         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 420                 dev_err(mmc_dev(host->mmc),
 421                         "Timeout waiting on controller reset in %s\n",
 422                         __func__);
 423 }
 424
 425 /*
 426  * MMC controller IRQ handler
 427  */
 428 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 429 {
 430         struct mmc_omap_host *host = dev_id;
 431         struct mmc_data *data;
 432         int end_cmd = 0, end_trans = 0, status;
 433
 434         if (host->mrq == NULL) {
 435                 OMAP_HSMMC_WRITE(host->base, STAT,
 436                         OMAP_HSMMC_READ(host->base, STAT));
 437                 return IRQ_HANDLED;
 438         }
 439
 440         data = host->data;
 441         status = OMAP_HSMMC_READ(host->base, STAT);
 442         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 443
 444         if (status & ERR) {
 445 #ifdef CONFIG_MMC_DEBUG
 446                 mmc_omap_report_irq(host, status);
 447 #endif
 448                 if ((status & CMD_TIMEOUT) ||
 449                         (status & CMD_CRC)) {
 450                         if (host->cmd) {
 451                                 if (status & CMD_TIMEOUT) {
 452                                         mmc_omap_reset_controller_fsm(host, SRC);
 453                                         host->cmd->error = -ETIMEDOUT;
 454                                 } else {
 455                                         host->cmd->error = -EILSEQ;
 456                                 }
 457                                 end_cmd = 1;
 458                         }
 459                         if (host->data || host->response_busy) {
 460                                 if (host->data)
 461                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 462                                 host->response_busy = 0;
 463                                 mmc_omap_reset_controller_fsm(host, SRD);
 464                         }
 465                 }
 466                 if ((status & DATA_TIMEOUT) ||
 467                         (status & DATA_CRC)) {
 468                         if (host->data || host->response_busy) {
 469                                 int err = (status & DATA_TIMEOUT) ?
 470                                                 -ETIMEDOUT : -EILSEQ;
 471
 472                                 if (host->data)
 473                                         mmc_dma_cleanup(host, err);
 474                                 else
 475                                         host->mrq->cmd->error = err;
 476                                 host->response_busy = 0;
 477                                 mmc_omap_reset_controller_fsm(host, SRD);
 478                                 end_trans = 1;
 479                         }
 480                 }
 481                 if (status & CARD_ERR) {
 482                         dev_dbg(mmc_dev(host->mmc),
 483                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 484                         if (host->cmd)
 485                                 end_cmd = 1;
 486                         if (host->data)
 487                                 end_trans = 1;
 488                 }
 489         }
 490
 491         OMAP_HSMMC_WRITE(host->base, STAT, status);
 492
 493         if (end_cmd || (status & CC))
 494                 mmc_omap_cmd_done(host, host->cmd);
 495         if (end_trans || (status & TC))
 496                 mmc_omap_xfer_done(host, data);
 497
 498         return IRQ_HANDLED;
 499 }
 500
 501 static void set_sd_bus_power(struct mmc_omap_host *host)
 502 {
 503         unsigned long i;
 504
 505         OMAP_HSMMC_WRITE(host->base, HCTL,
 506                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 507         for (i = 0; i < loops_per_jiffy; i++) {
 508                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 509                         break;
 510                 cpu_relax();
 511         }
 512 }
 513
 514 /*
 515  * Switch MMC interface voltage ... only relevant for MMC1.
 516  *
 517  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 518  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 519  * Some chips, like eMMC ones, use internal transceivers.
 520  */
 521 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 522 {
 523         u32 reg_val = 0;
 524         int ret;
 525
 526         /* Disable the clocks */
 527         clk_disable(host->fclk);
 528         clk_disable(host->iclk);
 529         clk_disable(host->dbclk);
 530
 531         /* Turn the power off */
 532         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 533         if (ret != 0)
 534                 goto err;
 535
 536         /* Turn the power ON with given VDD 1.8 or 3.0v */
 537         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 538         if (ret != 0)
 539                 goto err;
 540
 541         clk_enable(host->fclk);
 542         clk_enable(host->iclk);
 543         clk_enable(host->dbclk);
 544
 545         OMAP_HSMMC_WRITE(host->base, HCTL,
 546                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 547         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 548
 549         /*
 550          * If a MMC dual voltage card is detected, the set_ios fn calls
 551          * this fn with VDD bit set for 1.8V. Upon card removal from the
 552          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 553          *
 554          * Cope with a bit of slop in the range ... per data sheets:
 555          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 556          *    but recommended values are 1.71V to 1.89V
 557          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 558          *    but recommended values are 2.7V to 3.3V
 559          *
 560          * Board setup code shouldn't permit anything very out-of-range.
 561          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 562          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 563          */
 564         if ((1 << vdd) <= MMC_VDD_23_24)
 565                 reg_val |= SDVS18;
 566         else
 567                 reg_val |= SDVS30;
 568
 569         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 570         set_sd_bus_power(host);
 571
 572         return 0;
 573 err:
 574         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 575         return ret;
 576 }
 577
 578 /*
 579  * Work Item to notify the core about card insertion/removal
 580  */
 581 static void mmc_omap_detect(struct work_struct *work)
 582 {
 583         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 584                                                 mmc_carddetect_work);
 585         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 586
 587         if (mmc_slot(host).card_detect)
 588                 host->carddetect = slot->card_detect(slot->card_detect_irq);
 589         else
 590                 host->carddetect = -ENOSYS;
 591
 592         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 593         if (host->carddetect) {
 594                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 595         } else {
 596                 mmc_omap_reset_controller_fsm(host, SRD);
 597                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 598         }
 599 }
 600
 601 /*
 602  * ISR for handling card insertion and removal
 603  */
 604 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 605 {
 606         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 607
 608         schedule_work(&host->mmc_carddetect_work);
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 614                                      struct mmc_data *data)
 615 {
 616         int sync_dev;
 617
 618         if (data->flags & MMC_DATA_WRITE)
 619                 sync_dev = host->dma_line_tx;
 620         else
 621                 sync_dev = host->dma_line_rx;
 622         return sync_dev;
 623 }
 624
 625 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 626                                        struct mmc_data *data,
 627                                        struct scatterlist *sgl)
 628 {
 629         int blksz, nblk, dma_ch;
 630
 631         dma_ch = host->dma_ch;
 632         if (data->flags & MMC_DATA_WRITE) {
 633                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 634                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 635                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 636                         sg_dma_address(sgl), 0, 0);
 637         } else {
 638                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 639                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 640                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 641                         sg_dma_address(sgl), 0, 0);
 642         }
 643
 644         blksz = host->data->blksz;
 645         nblk = sg_dma_len(sgl) / blksz;
 646
 647         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 648                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 649                         mmc_omap_get_dma_sync_dev(host, data),
 650                         !(data->flags & MMC_DATA_WRITE));
 651
 652         omap_start_dma(dma_ch);
 653 }
 654
 655 /*
 656  * DMA call back function
 657  */
 658 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 659 {
 660         struct mmc_omap_host *host = data;
 661
 662         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 663                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 664
 665         if (host->dma_ch < 0)
 666                 return;
 667
 668         host->dma_sg_idx++;
 669         if (host->dma_sg_idx < host->dma_len) {
 670                 /* Fire up the next transfer. */
 671                 mmc_omap_config_dma_params(host, host->data,
 672                                            host->data->sg + host->dma_sg_idx);
 673                 return;
 674         }
 675
 676         omap_free_dma(host->dma_ch);
 677         host->dma_ch = -1;
 678         /*
 679          * DMA Callback: run in interrupt context.
 680          * mutex_unlock will through a kernel warning if used.
 681          */
 682         up(&host->sem);
 683 }
 684
 685 /*
 686  * Routine to configure and start DMA for the MMC card
 687  */
 688 static int
 689 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 690 {
 691         int dma_ch = 0, ret = 0, err = 1, i;
 692         struct mmc_data *data = req->data;
 693
 694         /* Sanity check: all the SG entries must be aligned by block size. */
 695         for (i = 0; i < host->dma_len; i++) {
 696                 struct scatterlist *sgl;
 697
 698                 sgl = data->sg + i;
 699                 if (sgl->length % data->blksz)
 700                         return -EINVAL;
 701         }
 702         if ((data->blksz % 4) != 0)
 703                 /* REVISIT: The MMC buffer increments only when MSB is written.
 704                  * Return error for blksz which is non multiple of four.
 705                  */
 706                 return -EINVAL;
 707
 708         /*
 709          * If for some reason the DMA transfer is still active,
 710          * we wait for timeout period and free the dma
 711          */
 712         if (host->dma_ch != -1) {
 713                 set_current_state(TASK_UNINTERRUPTIBLE);
 714                 schedule_timeout(100);
 715                 if (down_trylock(&host->sem)) {
 716                         omap_free_dma(host->dma_ch);
 717                         host->dma_ch = -1;
 718                         up(&host->sem);
 719                         return err;
 720                 }
 721         } else {
 722                 if (down_trylock(&host->sem))
 723                         return err;
 724         }
 725
 726         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 727                                mmc_omap_dma_cb,host, &dma_ch);
 728         if (ret != 0) {
 729                 dev_err(mmc_dev(host->mmc),
 730                         "%s: omap_request_dma() failed with %d\n",
 731                         mmc_hostname(host->mmc), ret);
 732                 return ret;
 733         }
 734
 735         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 736                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 737         host->dma_ch = dma_ch;
 738         host->dma_sg_idx = 0;
 739
 740         mmc_omap_config_dma_params(host, data, data->sg);
 741
 742         return 0;
 743 }
 744
 745 static void set_data_timeout(struct mmc_omap_host *host,
 746                              struct mmc_request *req)
 747 {
 748         unsigned int timeout, cycle_ns;
 749         uint32_t reg, clkd, dto = 0;
 750
 751         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 752         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 753         if (clkd == 0)
 754                 clkd = 1;
 755
 756         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 757         timeout = req->data->timeout_ns / cycle_ns;
 758         timeout += req->data->timeout_clks;
 759         if (timeout) {
 760                 while ((timeout & 0x80000000) == 0) {
 761                         dto += 1;
 762                         timeout <<= 1;
 763                 }
 764                 dto = 31 - dto;
 765                 timeout <<= 1;
 766                 if (timeout && dto)
 767                         dto += 1;
 768                 if (dto >= 13)
 769                         dto -= 13;
 770                 else
 771                         dto = 0;
 772                 if (dto > 14)
 773                         dto = 14;
 774         }
 775
 776         reg &= ~DTO_MASK;
 777         reg |= dto << DTO_SHIFT;
 778         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 779 }
 780
 781 /*
 782  * Configure block length for MMC/SD cards and initiate the transfer.
 783  */
 784 static int
 785 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 786 {
 787         int ret;
 788         host->data = req->data;
 789
 790         if (req->data == NULL) {
 791                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 792                 return 0;
 793         }
 794
 795         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 796                                         | (req->data->blocks << 16));
 797         set_data_timeout(host, req);
 798
 799         if (host->use_dma) {
 800                 ret = mmc_omap_start_dma_transfer(host, req);
 801                 if (ret != 0) {
 802                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 803                         return ret;
 804                 }
 805         }
 806         return 0;
 807 }
 808
 809 /*
 810  * Request function. for read/write operation
 811  */
 812 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 813 {
 814         struct mmc_omap_host *host = mmc_priv(mmc);
 815
 816         WARN_ON(host->mrq != NULL);
 817         host->mrq = req;
 818         mmc_omap_prepare_data(host, req);
 819         mmc_omap_start_command(host, req->cmd, req->data);
 820 }
 821
 822
 823 /* Routine to configure clock values. Exposed API to core */
 824 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 825 {
 826         struct mmc_omap_host *host = mmc_priv(mmc);
 827         u16 dsor = 0;
 828         unsigned long regval;
 829         unsigned long timeout;
 830         u32 con;
 831
 832         switch (ios->power_mode) {
 833         case MMC_POWER_OFF:
 834                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 835                 break;
 836         case MMC_POWER_UP:
 837                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 838                 break;
 839         }
 840
 841         con = OMAP_HSMMC_READ(host->base, CON);
 842         switch (mmc->ios.bus_width) {
 843         case MMC_BUS_WIDTH_8:
 844                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 845                 break;
 846         case MMC_BUS_WIDTH_4:
 847                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 848                 OMAP_HSMMC_WRITE(host->base, HCTL,
 849                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 850                 break;
 851         case MMC_BUS_WIDTH_1:
 852                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 853                 OMAP_HSMMC_WRITE(host->base, HCTL,
 854                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 855                 break;
 856         }
 857
 858         if (host->id == OMAP_MMC1_DEVID) {
 859                 /* Only MMC1 can interface at 3V without some flavor
 860                  * of external transceiver; but they all handle 1.8V.
 861                  */
 862                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 863                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 864                                 /*
 865                                  * The mmc_select_voltage fn of the core does
 866                                  * not seem to set the power_mode to
 867                                  * MMC_POWER_UP upon recalculating the voltage.
 868                                  * vdd 1.8v.
 869                                  */
 870                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 871                                         dev_dbg(mmc_dev(host->mmc),
 872                                                 "Switch operation failed\n");
 873                 }
 874         }
 875
 876         if (ios->clock) {
 877                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 878                 if (dsor < 1)
 879                         dsor = 1;
 880
 881                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 882                         dsor++;
 883
 884                 if (dsor > 250)
 885                         dsor = 250;
 886         }
 887         omap_mmc_stop_clock(host);
 888         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 889         regval = regval & ~(CLKD_MASK);
 890         regval = regval | (dsor << 6) | (DTO << 16);
 891         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 892         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 893                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 894
 895         /* Wait till the ICS bit is set */
 896         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 897         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 898                 && time_before(jiffies, timeout))
 899                 msleep(1);
 900
 901         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 902                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 903
 904         if (ios->power_mode == MMC_POWER_ON)
 905                 send_init_stream(host);
 906
 907         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 908                 OMAP_HSMMC_WRITE(host->base, CON,
 909                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 910 }
 911
 912 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 913 {
 914         struct mmc_omap_host *host = mmc_priv(mmc);
 915         struct omap_mmc_platform_data *pdata = host->pdata;
 916
 917         if (!pdata->slots[0].card_detect)
 918                 return -ENOSYS;
 919         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 920 }
 921
 922 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 923 {
 924         struct mmc_omap_host *host = mmc_priv(mmc);
 925         struct omap_mmc_platform_data *pdata = host->pdata;
 926
 927         if (!pdata->slots[0].get_ro)
 928                 return -ENOSYS;
 929         return pdata->slots[0].get_ro(host->dev, 0);
 930 }
 931
 932 static void omap_hsmmc_init(struct mmc_omap_host *host)
 933 {
 934         u32 hctl, capa, value;
 935
 936         /* Only MMC1 supports 3.0V */
 937         if (host->id == OMAP_MMC1_DEVID) {
 938                 hctl = SDVS30;
 939                 capa = VS30 | VS18;
 940         } else {
 941                 hctl = SDVS18;
 942                 capa = VS18;
 943         }
 944
 945         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
 946         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
 947
 948         value = OMAP_HSMMC_READ(host->base, CAPA);
 949         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
 950
 951         /* Set the controller to AUTO IDLE mode */
 952         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
 953         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
 954
 955         /* Set SD bus power bit */
 956         set_sd_bus_power(host);
 957 }
 958
 959 static struct mmc_host_ops mmc_omap_ops = {
 960         .request = omap_mmc_request,
 961         .set_ios = omap_mmc_set_ios,
 962         .get_cd = omap_hsmmc_get_cd,
 963         .get_ro = omap_hsmmc_get_ro,
 964         /* NYET -- enable_sdio_irq */
 965 };
 966
 967 static int __init omap_mmc_probe(struct platform_device *pdev)
 968 {
 969         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 970         struct mmc_host *mmc;
 971         struct mmc_omap_host *host = NULL;
 972         struct resource *res;
 973         int ret = 0, irq;
 974
 975         if (pdata == NULL) {
 976                 dev_err(&pdev->dev, "Platform Data is missing\n");
 977                 return -ENXIO;
 978         }
 979
 980         if (pdata->nr_slots == 0) {
 981                 dev_err(&pdev->dev, "No Slots\n");
 982                 return -ENXIO;
 983         }
 984
 985         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 986         irq = platform_get_irq(pdev, 0);
 987         if (res == NULL || irq < 0)
 988                 return -ENXIO;
 989
 990         res = request_mem_region(res->start, res->end - res->start + 1,
 991                                                         pdev->name);
 992         if (res == NULL)
 993                 return -EBUSY;
 994
 995         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 996         if (!mmc) {
 997                 ret = -ENOMEM;
 998                 goto err;
 999         }
1000
1001         host            = mmc_priv(mmc);
1002         host->mmc       = mmc;
1003         host->pdata     = pdata;
1004         host->dev       = &pdev->dev;
1005         host->use_dma   = 1;
1006         host->dev->dma_mask = &pdata->dma_mask;
1007         host->dma_ch    = -1;
1008         host->irq       = irq;
1009         host->id        = pdev->id;
1010         host->slot_id   = 0;
1011         host->mapbase   = res->start;
1012         host->base      = ioremap(host->mapbase, SZ_4K);
1013
1014         platform_set_drvdata(pdev, host);
1015         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1016
1017         mmc->ops        = &mmc_omap_ops;
1018         mmc->f_min      = 400000;
1019         mmc->f_max      = 52000000;
1020
1021         sema_init(&host->sem, 1);
1022
1023         host->iclk = clk_get(&pdev->dev, "ick");
1024         if (IS_ERR(host->iclk)) {
1025                 ret = PTR_ERR(host->iclk);
1026                 host->iclk = NULL;
1027                 goto err1;
1028         }
1029         host->fclk = clk_get(&pdev->dev, "fck");
1030         if (IS_ERR(host->fclk)) {
1031                 ret = PTR_ERR(host->fclk);
1032                 host->fclk = NULL;
1033                 clk_put(host->iclk);
1034                 goto err1;
1035         }
1036
1037         if (clk_enable(host->fclk) != 0) {
1038                 clk_put(host->iclk);
1039                 clk_put(host->fclk);
1040                 goto err1;
1041         }
1042
1043         if (clk_enable(host->iclk) != 0) {
1044                 clk_disable(host->fclk);
1045                 clk_put(host->iclk);
1046                 clk_put(host->fclk);
1047                 goto err1;
1048         }
1049
1050         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1051         /*
1052          * MMC can still work without debounce clock.
1053          */
1054         if (IS_ERR(host->dbclk))
1055                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1056         else
1057                 if (clk_enable(host->dbclk) != 0)
1058                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1059                                                         " clk failed\n");
1060                 else
1061                         host->dbclk_enabled = 1;
1062
1063         /* Since we do only SG emulation, we can have as many segs
1064          * as we want. */
1065         mmc->max_phys_segs = 1024;
1066         mmc->max_hw_segs = 1024;
1067
1068         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1069         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1070         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1071         mmc->max_seg_size = mmc->max_req_size;
1072
1073         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1074         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1075
1076         if (pdata->slots[host->slot_id].wires >= 8)
1077                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1078         else if (pdata->slots[host->slot_id].wires >= 4)
1079                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1080
1081         omap_hsmmc_init(host);
1082
1083         /* Select DMA lines */
1084         switch (host->id) {
1085         case OMAP_MMC1_DEVID:
1086                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1087                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1088                 break;
1089         case OMAP_MMC2_DEVID:
1090                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1091                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1092                 break;
1093         case OMAP_MMC3_DEVID:
1094                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1095                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1096                 break;
1097         default:
1098                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1099                 goto err_irq;
1100         }
1101
1102         /* Request IRQ for MMC operations */
1103         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1104                         mmc_hostname(mmc), host);
1105         if (ret) {
1106                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1107                 goto err_irq;
1108         }
1109
1110         if (pdata->init != NULL) {
1111                 if (pdata->init(&pdev->dev) != 0) {
1112                         dev_dbg(mmc_dev(host->mmc),
1113                                 "Unable to configure MMC IRQs\n");
1114                         goto err_irq_cd_init;
1115                 }
1116         }
1117
1118         /* Request IRQ for card detect */
1119         if ((mmc_slot(host).card_detect_irq)) {
1120                 ret = request_irq(mmc_slot(host).card_detect_irq,
1121                                   omap_mmc_cd_handler,
1122                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1123                                           | IRQF_DISABLED,
1124                                   mmc_hostname(mmc), host);
1125                 if (ret) {
1126                         dev_dbg(mmc_dev(host->mmc),
1127                                 "Unable to grab MMC CD IRQ\n");
1128                         goto err_irq_cd;
1129                 }
1130         }
1131
1132         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1133         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1134
1135         mmc_add_host(mmc);
1136
1137         if (host->pdata->slots[host->slot_id].name != NULL) {
1138                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1139                 if (ret < 0)
1140                         goto err_slot_name;
1141         }
1142         if (mmc_slot(host).card_detect_irq &&
1143             host->pdata->slots[host->slot_id].get_cover_state) {
1144                 ret = device_create_file(&mmc->class_dev,
1145                                         &dev_attr_cover_switch);
1146                 if (ret < 0)
1147                         goto err_cover_switch;
1148         }
1149
1150         return 0;
1151
1152 err_cover_switch:
1153         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1154 err_slot_name:
1155         mmc_remove_host(mmc);
1156 err_irq_cd:
1157         free_irq(mmc_slot(host).card_detect_irq, host);
1158 err_irq_cd_init:
1159         free_irq(host->irq, host);
1160 err_irq:
1161         clk_disable(host->fclk);
1162         clk_disable(host->iclk);
1163         clk_put(host->fclk);
1164         clk_put(host->iclk);
1165         if (host->dbclk_enabled) {
1166                 clk_disable(host->dbclk);
1167                 clk_put(host->dbclk);
1168         }
1169
1170 err1:
1171         iounmap(host->base);
1172 err:
1173         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1174         release_mem_region(res->start, res->end - res->start + 1);
1175         if (host)
1176                 mmc_free_host(mmc);
1177         return ret;
1178 }
1179
1180 static int omap_mmc_remove(struct platform_device *pdev)
1181 {
1182         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1183         struct resource *res;
1184
1185         if (host) {
1186                 mmc_remove_host(host->mmc);
1187                 if (host->pdata->cleanup)
1188                         host->pdata->cleanup(&pdev->dev);
1189                 free_irq(host->irq, host);
1190                 if (mmc_slot(host).card_detect_irq)
1191                         free_irq(mmc_slot(host).card_detect_irq, host);
1192                 flush_scheduled_work();
1193
1194                 clk_disable(host->fclk);
1195                 clk_disable(host->iclk);
1196                 clk_put(host->fclk);
1197                 clk_put(host->iclk);
1198                 if (host->dbclk_enabled) {
1199                         clk_disable(host->dbclk);
1200                         clk_put(host->dbclk);
1201                 }
1202
1203                 mmc_free_host(host->mmc);
1204                 iounmap(host->base);
1205         }
1206
1207         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1208         if (res)
1209                 release_mem_region(res->start, res->end - res->start + 1);
1210         platform_set_drvdata(pdev, NULL);
1211
1212         return 0;
1213 }
1214
1215 #ifdef CONFIG_PM
1216 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1217 {
1218         int ret = 0;
1219         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1220
1221         if (host && host->suspended)
1222                 return 0;
1223
1224         if (host) {
1225                 ret = mmc_suspend_host(host->mmc, state);
1226                 if (ret == 0) {
1227                         host->suspended = 1;
1228
1229                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1230                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1231
1232                         if (host->pdata->suspend) {
1233                                 ret = host->pdata->suspend(&pdev->dev,
1234                                                                 host->slot_id);
1235                                 if (ret)
1236                                         dev_dbg(mmc_dev(host->mmc),
1237                                                 "Unable to handle MMC board"
1238                                                 " level suspend\n");
1239                         }
1240
1241                         OMAP_HSMMC_WRITE(host->base, HCTL,
1242                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1243                         clk_disable(host->fclk);
1244                         clk_disable(host->iclk);
1245                         clk_disable(host->dbclk);
1246                 }
1247
1248         }
1249         return ret;
1250 }
1251
1252 /* Routine to resume the MMC device */
1253 static int omap_mmc_resume(struct platform_device *pdev)
1254 {
1255         int ret = 0;
1256         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1257
1258         if (host && !host->suspended)
1259                 return 0;
1260
1261         if (host) {
1262
1263                 ret = clk_enable(host->fclk);
1264                 if (ret)
1265                         goto clk_en_err;
1266
1267                 ret = clk_enable(host->iclk);
1268                 if (ret) {
1269                         clk_disable(host->fclk);
1270                         clk_put(host->fclk);
1271                         goto clk_en_err;
1272                 }
1273
1274                 if (clk_enable(host->dbclk) != 0)
1275                         dev_dbg(mmc_dev(host->mmc),
1276                                         "Enabling debounce clk failed\n");
1277
1278                 omap_hsmmc_init(host);
1279
1280                 if (host->pdata->resume) {
1281                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1282                         if (ret)
1283                                 dev_dbg(mmc_dev(host->mmc),
1284                                         "Unmask interrupt failed\n");
1285                 }
1286
1287                 /* Notify the core to resume the host */
1288                 ret = mmc_resume_host(host->mmc);
1289                 if (ret == 0)
1290                         host->suspended = 0;
1291         }
1292
1293         return ret;
1294
1295 clk_en_err:
1296         dev_dbg(mmc_dev(host->mmc),
1297                 "Failed to enable MMC clocks during resume\n");
1298         return ret;
1299 }
1300
1301 #else
1302 #define omap_mmc_suspend        NULL
1303 #define omap_mmc_resume         NULL
1304 #endif
1305
1306 static struct platform_driver omap_mmc_driver = {
1307         .probe          = omap_mmc_probe,
1308         .remove         = omap_mmc_remove,
1309         .suspend        = omap_mmc_suspend,
1310         .resume         = omap_mmc_resume,
1311         .driver         = {
1312                 .name = DRIVER_NAME,
1313                 .owner = THIS_MODULE,
1314         },
1315 };
1316
1317 static int __init omap_mmc_init(void)
1318 {
1319         /* Register the MMC driver */
1320         return platform_driver_register(&omap_mmc_driver);
1321 }
1322
1323 static void __exit omap_mmc_cleanup(void)
1324 {
1325         /* Unregister MMC driver */
1326         platform_driver_unregister(&omap_mmc_driver);
1327 }
1328
1329 module_init(omap_mmc_init);
1330 module_exit(omap_mmc_cleanup);
1331
1332 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1333 MODULE_LICENSE("GPL");
1334 MODULE_ALIAS("platform:" DRIVER_NAME);
1335 MODULE_AUTHOR("Texas Instruments Inc");