2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
40 #include <linux/irq.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/platform_data/mmc-omap.h>
47 /* OMAP HSMMC Host Controller Registers */
48 #define OMAP_HSMMC_SYSSTATUS 0x0014
49 #define OMAP_HSMMC_CON 0x002C
50 #define OMAP_HSMMC_SDMASA 0x0100
51 #define OMAP_HSMMC_BLK 0x0104
52 #define OMAP_HSMMC_ARG 0x0108
53 #define OMAP_HSMMC_CMD 0x010C
54 #define OMAP_HSMMC_RSP10 0x0110
55 #define OMAP_HSMMC_RSP32 0x0114
56 #define OMAP_HSMMC_RSP54 0x0118
57 #define OMAP_HSMMC_RSP76 0x011C
58 #define OMAP_HSMMC_DATA 0x0120
59 #define OMAP_HSMMC_PSTATE 0x0124
60 #define OMAP_HSMMC_HCTL 0x0128
61 #define OMAP_HSMMC_SYSCTL 0x012C
62 #define OMAP_HSMMC_STAT 0x0130
63 #define OMAP_HSMMC_IE 0x0134
64 #define OMAP_HSMMC_ISE 0x0138
65 #define OMAP_HSMMC_AC12 0x013C
66 #define OMAP_HSMMC_CAPA 0x0140
68 #define VS18 (1 << 26)
69 #define VS30 (1 << 25)
71 #define SDVS18 (0x5 << 9)
72 #define SDVS30 (0x6 << 9)
73 #define SDVS33 (0x7 << 9)
74 #define SDVS_MASK 0x00000E00
75 #define SDVSCLR 0xFFFFF1FF
76 #define SDVSDET 0x00000400
83 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
84 #define CLKD_MASK 0x0000FFC0
86 #define DTO_MASK 0x000F0000
88 #define INIT_STREAM (1 << 1)
89 #define ACEN_ACMD23 (2 << 2)
90 #define DP_SELECT (1 << 21)
95 #define FOUR_BIT (1 << 1)
99 #define CLKEXTFREE (1 << 16)
100 #define CTPL (1 << 11)
103 #define STAT_CLEAR 0xFFFFFFFF
104 #define INIT_STREAM_CMD 0x00000000
105 #define DUAL_VOLT_OCR_BIT 7
106 #define SRC (1 << 25)
107 #define SRD (1 << 26)
108 #define SOFTRESET (1 << 1)
111 #define DLEV_DAT(x) (1 << (20 + (x)))
113 /* Interrupt masks for IE and ISE register */
114 #define CC_EN (1 << 0)
115 #define TC_EN (1 << 1)
116 #define BWR_EN (1 << 4)
117 #define BRR_EN (1 << 5)
118 #define CIRQ_EN (1 << 8)
119 #define ERR_EN (1 << 15)
120 #define CTO_EN (1 << 16)
121 #define CCRC_EN (1 << 17)
122 #define CEB_EN (1 << 18)
123 #define CIE_EN (1 << 19)
124 #define DTO_EN (1 << 20)
125 #define DCRC_EN (1 << 21)
126 #define DEB_EN (1 << 22)
127 #define ACE_EN (1 << 24)
128 #define CERR_EN (1 << 28)
129 #define BADA_EN (1 << 29)
131 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
132 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
133 BRR_EN | BWR_EN | TC_EN | CC_EN)
136 #define ACIE (1 << 4)
137 #define ACEB (1 << 3)
138 #define ACCE (1 << 2)
139 #define ACTO (1 << 1)
140 #define ACNE (1 << 0)
142 #define MMC_AUTOSUSPEND_DELAY 100
143 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
144 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
145 #define OMAP_MMC_MIN_CLOCK 400000
146 #define OMAP_MMC_MAX_CLOCK 52000000
147 #define DRIVER_NAME "omap_hsmmc"
149 #define VDD_1V8 1800000 /* 180000 uV */
150 #define VDD_3V0 3000000 /* 300000 uV */
151 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
154 * One controller can have multiple slots, like on some omap boards using
155 * omap.c controller driver. Luckily this is not currently done on any known
156 * omap_hsmmc.c device.
158 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
161 * MMC Host controller read/write API's
163 #define OMAP_HSMMC_READ(base, reg) \
164 __raw_readl((base) + OMAP_HSMMC_##reg)
166 #define OMAP_HSMMC_WRITE(base, reg, val) \
167 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
169 struct omap_hsmmc_next {
170 unsigned int dma_len;
174 struct omap_hsmmc_host {
176 struct mmc_host *mmc;
177 struct mmc_request *mrq;
178 struct mmc_command *cmd;
179 struct mmc_data *data;
183 * vcc == configured supply
184 * vcc_aux == optional
185 * - MMC1, supply for DAT4..DAT7
186 * - MMC2/MMC2, external level shifter voltage supply, for
187 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
189 struct regulator *vcc;
190 struct regulator *vcc_aux;
191 struct regulator *pbias;
194 resource_size_t mapbase;
195 spinlock_t irq_lock; /* Prevent races with irq handler */
196 unsigned int dma_len;
197 unsigned int dma_sg_idx;
198 unsigned char bus_mode;
199 unsigned char power_mode;
208 struct dma_chan *tx_chan;
209 struct dma_chan *rx_chan;
217 unsigned long clk_rate;
219 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
220 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
221 #define HSMMC_WAKE_IRQ_ENABLED (1 << 2)
222 struct omap_hsmmc_next next_data;
223 struct omap_mmc_platform_data *pdata;
226 struct omap_mmc_of_data {
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233 static int omap_hsmmc_card_detect(struct device *dev, int slot)
235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
236 struct omap_mmc_platform_data *mmc = host->pdata;
238 /* NOTE: assumes card detect signal is active-low */
239 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
242 static int omap_hsmmc_get_wp(struct device *dev, int slot)
244 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
245 struct omap_mmc_platform_data *mmc = host->pdata;
247 /* NOTE: assumes write protect signal is active-high */
248 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
251 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
253 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
254 struct omap_mmc_platform_data *mmc = host->pdata;
256 /* NOTE: assumes card detect signal is active-low */
257 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
262 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
264 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
265 struct omap_mmc_platform_data *mmc = host->pdata;
267 disable_irq(mmc->slots[0].card_detect_irq);
271 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
273 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
274 struct omap_mmc_platform_data *mmc = host->pdata;
276 enable_irq(mmc->slots[0].card_detect_irq);
282 #define omap_hsmmc_suspend_cdirq NULL
283 #define omap_hsmmc_resume_cdirq NULL
287 #ifdef CONFIG_REGULATOR
289 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
292 struct omap_hsmmc_host *host =
293 platform_get_drvdata(to_platform_device(dev));
297 * If we don't see a Vcc regulator, assume it's a fixed
298 * voltage always-on regulator.
303 if (mmc_slot(host).before_set_reg)
304 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
307 if (host->pbias_enabled == 1) {
308 ret = regulator_disable(host->pbias);
310 host->pbias_enabled = 0;
312 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
316 * Assume Vcc regulator is used only to power the card ... OMAP
317 * VDDS is used to power the pins, optionally with a transceiver to
318 * support cards using voltages other than VDDS (1.8V nominal). When a
319 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
321 * In some cases this regulator won't support enable/disable;
322 * e.g. it's a fixed rail for a WLAN chip.
324 * In other cases vcc_aux switches interface power. Example, for
325 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
326 * chips/cards need an interface voltage rail too.
330 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
331 /* Enable interface voltage rail, if needed */
332 if (ret == 0 && host->vcc_aux) {
333 ret = regulator_enable(host->vcc_aux);
334 if (ret < 0 && host->vcc)
335 ret = mmc_regulator_set_ocr(host->mmc,
339 /* Shut down the rail */
341 ret = regulator_disable(host->vcc_aux);
343 /* Then proceed to shut down the local regulator */
344 ret = mmc_regulator_set_ocr(host->mmc,
350 if (vdd <= VDD_165_195)
351 ret = regulator_set_voltage(host->pbias, VDD_1V8,
354 ret = regulator_set_voltage(host->pbias, VDD_3V0,
357 goto error_set_power;
359 if (host->pbias_enabled == 0) {
360 ret = regulator_enable(host->pbias);
362 host->pbias_enabled = 1;
366 if (mmc_slot(host).after_set_reg)
367 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
373 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
375 struct regulator *reg;
378 reg = devm_regulator_get(host->dev, "vmmc");
380 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
385 ocr_value = mmc_regulator_get_ocrmask(reg);
386 if (!mmc_slot(host).ocr_mask) {
387 mmc_slot(host).ocr_mask = ocr_value;
389 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
390 dev_err(host->dev, "ocrmask %x is not supported\n",
391 mmc_slot(host).ocr_mask);
392 mmc_slot(host).ocr_mask = 0;
397 mmc_slot(host).set_power = omap_hsmmc_set_power;
399 /* Allow an aux regulator */
400 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
401 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
403 reg = devm_regulator_get_optional(host->dev, "pbias");
404 host->pbias = IS_ERR(reg) ? NULL : reg;
406 /* For eMMC do not power off when not in sleep state */
407 if (mmc_slot(host).no_regulator_off_init)
410 * To disable boot_on regulator, enable regulator
411 * to increase usecount and then disable it.
413 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
414 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
415 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
417 mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
418 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
424 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
426 mmc_slot(host).set_power = NULL;
429 static inline int omap_hsmmc_have_reg(void)
436 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
441 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
445 static inline int omap_hsmmc_have_reg(void)
452 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
456 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
457 if (pdata->slots[0].cover)
458 pdata->slots[0].get_cover_state =
459 omap_hsmmc_get_cover_state;
461 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
462 pdata->slots[0].card_detect_irq =
463 gpio_to_irq(pdata->slots[0].switch_pin);
464 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
467 ret = gpio_direction_input(pdata->slots[0].switch_pin);
471 pdata->slots[0].switch_pin = -EINVAL;
473 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
474 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
475 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
478 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
482 pdata->slots[0].gpio_wp = -EINVAL;
487 gpio_free(pdata->slots[0].gpio_wp);
489 if (gpio_is_valid(pdata->slots[0].switch_pin))
491 gpio_free(pdata->slots[0].switch_pin);
495 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
497 if (gpio_is_valid(pdata->slots[0].gpio_wp))
498 gpio_free(pdata->slots[0].gpio_wp);
499 if (gpio_is_valid(pdata->slots[0].switch_pin))
500 gpio_free(pdata->slots[0].switch_pin);
504 * Start clock to the card
506 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
508 OMAP_HSMMC_WRITE(host->base, SYSCTL,
509 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
513 * Stop clock to the card
515 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
517 OMAP_HSMMC_WRITE(host->base, SYSCTL,
518 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
519 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
520 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
523 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
524 struct mmc_command *cmd)
526 u32 irq_mask = INT_EN_MASK;
530 irq_mask &= ~(BRR_EN | BWR_EN);
532 /* Disable timeout for erases */
533 if (cmd->opcode == MMC_ERASE)
536 spin_lock_irqsave(&host->irq_lock, flags);
537 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
538 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
540 /* latch pending CIRQ, but don't signal MMC core */
541 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
543 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
544 spin_unlock_irqrestore(&host->irq_lock, flags);
547 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
552 spin_lock_irqsave(&host->irq_lock, flags);
553 /* no transfer running but need to keep cirq if enabled */
554 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
556 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
557 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
558 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
559 spin_unlock_irqrestore(&host->irq_lock, flags);
562 /* Calculate divisor for the given clock frequency */
563 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
568 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
576 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
578 struct mmc_ios *ios = &host->mmc->ios;
579 unsigned long regval;
580 unsigned long timeout;
581 unsigned long clkdiv;
583 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
585 omap_hsmmc_stop_clock(host);
587 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
588 regval = regval & ~(CLKD_MASK | DTO_MASK);
589 clkdiv = calc_divisor(host, ios);
590 regval = regval | (clkdiv << 6) | (DTO << 16);
591 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
592 OMAP_HSMMC_WRITE(host->base, SYSCTL,
593 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
595 /* Wait till the ICS bit is set */
596 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
597 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
598 && time_before(jiffies, timeout))
602 * Enable High-Speed Support
604 * - Controller should support High-Speed-Enable Bit
605 * - Controller should not be using DDR Mode
606 * - Controller should advertise that it supports High Speed
607 * in capabilities register
608 * - MMC/SD clock coming out of controller > 25MHz
610 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
611 (ios->timing != MMC_TIMING_MMC_DDR52) &&
612 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
613 regval = OMAP_HSMMC_READ(host->base, HCTL);
614 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
619 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
622 omap_hsmmc_start_clock(host);
625 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
627 struct mmc_ios *ios = &host->mmc->ios;
630 con = OMAP_HSMMC_READ(host->base, CON);
631 if (ios->timing == MMC_TIMING_MMC_DDR52)
632 con |= DDR; /* configure in DDR mode */
635 switch (ios->bus_width) {
636 case MMC_BUS_WIDTH_8:
637 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
639 case MMC_BUS_WIDTH_4:
640 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
641 OMAP_HSMMC_WRITE(host->base, HCTL,
642 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
644 case MMC_BUS_WIDTH_1:
645 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
646 OMAP_HSMMC_WRITE(host->base, HCTL,
647 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
652 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
654 struct mmc_ios *ios = &host->mmc->ios;
657 con = OMAP_HSMMC_READ(host->base, CON);
658 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
659 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
661 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
667 * Restore the MMC host context, if it was lost as result of a
668 * power state change.
670 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
672 struct mmc_ios *ios = &host->mmc->ios;
674 unsigned long timeout;
676 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
677 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
678 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
679 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
682 host->context_loss++;
684 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
685 if (host->power_mode != MMC_POWER_OFF &&
686 (1 << ios->vdd) <= MMC_VDD_23_24)
696 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
699 OMAP_HSMMC_WRITE(host->base, HCTL,
700 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
702 OMAP_HSMMC_WRITE(host->base, CAPA,
703 OMAP_HSMMC_READ(host->base, CAPA) | capa);
705 OMAP_HSMMC_WRITE(host->base, HCTL,
706 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
708 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
709 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
710 && time_before(jiffies, timeout))
713 OMAP_HSMMC_WRITE(host->base, ISE, 0);
714 OMAP_HSMMC_WRITE(host->base, IE, 0);
715 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
717 /* Do not initialize card-specific things if the power is off */
718 if (host->power_mode == MMC_POWER_OFF)
721 omap_hsmmc_set_bus_width(host);
723 omap_hsmmc_set_clock(host);
725 omap_hsmmc_set_bus_mode(host);
728 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
734 * Save the MMC host context (store the number of power state changes so far).
736 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
738 host->con = OMAP_HSMMC_READ(host->base, CON);
739 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
740 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
741 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
746 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
751 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
758 * Send init stream sequence to card
759 * before sending IDLE command
761 static void send_init_stream(struct omap_hsmmc_host *host)
764 unsigned long timeout;
766 if (host->protect_card)
769 disable_irq(host->irq);
771 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
772 OMAP_HSMMC_WRITE(host->base, CON,
773 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
774 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
776 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
777 while ((reg != CC_EN) && time_before(jiffies, timeout))
778 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
780 OMAP_HSMMC_WRITE(host->base, CON,
781 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
783 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
784 OMAP_HSMMC_READ(host->base, STAT);
786 enable_irq(host->irq);
790 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
794 if (mmc_slot(host).get_cover_state)
795 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
800 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
803 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
804 struct omap_hsmmc_host *host = mmc_priv(mmc);
806 return sprintf(buf, "%s\n",
807 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
810 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
813 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
816 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
817 struct omap_hsmmc_host *host = mmc_priv(mmc);
819 return sprintf(buf, "%s\n", mmc_slot(host).name);
822 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
825 * Configure the response type and send the cmd.
828 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
829 struct mmc_data *data)
831 int cmdreg = 0, resptype = 0, cmdtype = 0;
833 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
834 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
837 omap_hsmmc_enable_irq(host, cmd);
839 host->response_busy = 0;
840 if (cmd->flags & MMC_RSP_PRESENT) {
841 if (cmd->flags & MMC_RSP_136)
843 else if (cmd->flags & MMC_RSP_BUSY) {
845 host->response_busy = 1;
851 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
852 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
853 * a val of 0x3, rest 0x0.
855 if (cmd == host->mrq->stop)
858 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
860 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
862 cmdreg |= ACEN_ACMD23;
863 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
866 cmdreg |= DP_SELECT | MSBS | BCE;
867 if (data->flags & MMC_DATA_READ)
876 host->req_in_progress = 1;
878 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
879 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
883 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
885 if (data->flags & MMC_DATA_WRITE)
886 return DMA_TO_DEVICE;
888 return DMA_FROM_DEVICE;
891 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
892 struct mmc_data *data)
894 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
897 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
902 spin_lock_irqsave(&host->irq_lock, flags);
903 host->req_in_progress = 0;
904 dma_ch = host->dma_ch;
905 spin_unlock_irqrestore(&host->irq_lock, flags);
907 omap_hsmmc_disable_irq(host);
908 /* Do not complete the request if DMA is still in progress */
909 if (mrq->data && host->use_dma && dma_ch != -1)
912 mmc_request_done(host->mmc, mrq);
916 * Notify the transfer complete to MMC core
919 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
922 struct mmc_request *mrq = host->mrq;
924 /* TC before CC from CMD6 - don't know why, but it happens */
925 if (host->cmd && host->cmd->opcode == 6 &&
926 host->response_busy) {
927 host->response_busy = 0;
931 omap_hsmmc_request_done(host, mrq);
938 data->bytes_xfered += data->blocks * (data->blksz);
940 data->bytes_xfered = 0;
942 if (data->stop && (data->error || !host->mrq->sbc))
943 omap_hsmmc_start_command(host, data->stop, NULL);
945 omap_hsmmc_request_done(host, data->mrq);
949 * Notify the core about command completion
952 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
954 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
955 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
957 omap_hsmmc_start_dma_transfer(host);
958 omap_hsmmc_start_command(host, host->mrq->cmd,
965 if (cmd->flags & MMC_RSP_PRESENT) {
966 if (cmd->flags & MMC_RSP_136) {
967 /* response type 2 */
968 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
969 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
970 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
971 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
973 /* response types 1, 1b, 3, 4, 5, 6 */
974 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
977 if ((host->data == NULL && !host->response_busy) || cmd->error)
978 omap_hsmmc_request_done(host, host->mrq);
982 * DMA clean up for command errors
984 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
989 host->data->error = errno;
991 spin_lock_irqsave(&host->irq_lock, flags);
992 dma_ch = host->dma_ch;
994 spin_unlock_irqrestore(&host->irq_lock, flags);
996 if (host->use_dma && dma_ch != -1) {
997 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
999 dmaengine_terminate_all(chan);
1000 dma_unmap_sg(chan->device->dev,
1001 host->data->sg, host->data->sg_len,
1002 omap_hsmmc_get_dma_dir(host, host->data));
1004 host->data->host_cookie = 0;
1010 * Readable error output
1012 #ifdef CONFIG_MMC_DEBUG
1013 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1015 /* --- means reserved bit without definition at documentation */
1016 static const char *omap_hsmmc_status_bits[] = {
1017 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1018 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1019 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1020 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1026 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1029 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1030 if (status & (1 << i)) {
1031 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1035 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1038 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1042 #endif /* CONFIG_MMC_DEBUG */
1045 * MMC controller internal state machines reset
1047 * Used to reset command or data internal state machines, using respectively
1048 * SRC or SRD bit of SYSCTL register
1049 * Can be called from interrupt context
1051 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1054 unsigned long i = 0;
1055 unsigned long limit = MMC_TIMEOUT_US;
1057 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1058 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1061 * OMAP4 ES2 and greater has an updated reset logic.
1062 * Monitor a 0->1 transition first
1064 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1065 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1071 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1075 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1076 dev_err(mmc_dev(host->mmc),
1077 "Timeout waiting on controller reset in %s\n",
1081 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1082 int err, int end_cmd)
1085 omap_hsmmc_reset_controller_fsm(host, SRC);
1087 host->cmd->error = err;
1091 omap_hsmmc_reset_controller_fsm(host, SRD);
1092 omap_hsmmc_dma_cleanup(host, err);
1093 } else if (host->mrq && host->mrq->cmd)
1094 host->mrq->cmd->error = err;
1097 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1099 struct mmc_data *data;
1100 int end_cmd = 0, end_trans = 0;
1104 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1106 if (status & ERR_EN) {
1107 omap_hsmmc_dbg_report_irq(host, status);
1109 if (status & (CTO_EN | CCRC_EN))
1111 if (status & (CTO_EN | DTO_EN))
1112 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1113 else if (status & (CCRC_EN | DCRC_EN))
1114 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1116 if (status & ACE_EN) {
1118 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1119 if (!(ac12 & ACNE) && host->mrq->sbc) {
1123 else if (ac12 & (ACCE | ACEB | ACIE))
1125 host->mrq->sbc->error = error;
1126 hsmmc_command_incomplete(host, error, end_cmd);
1128 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1130 if (host->data || host->response_busy) {
1131 end_trans = !end_cmd;
1132 host->response_busy = 0;
1136 OMAP_HSMMC_WRITE(host->base, STAT, status);
1137 if (end_cmd || ((status & CC_EN) && host->cmd))
1138 omap_hsmmc_cmd_done(host, host->cmd);
1139 if ((end_trans || (status & TC_EN)) && host->mrq)
1140 omap_hsmmc_xfer_done(host, data);
1144 * MMC controller IRQ handler
1146 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1148 struct omap_hsmmc_host *host = dev_id;
1151 status = OMAP_HSMMC_READ(host->base, STAT);
1152 while (status & (INT_EN_MASK | CIRQ_EN)) {
1153 if (host->req_in_progress)
1154 omap_hsmmc_do_irq(host, status);
1156 if (status & CIRQ_EN)
1157 mmc_signal_sdio_irq(host->mmc);
1159 /* Flush posted write */
1160 status = OMAP_HSMMC_READ(host->base, STAT);
1166 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1168 struct omap_hsmmc_host *host = dev_id;
1170 /* cirq is level triggered, disable to avoid infinite loop */
1171 spin_lock(&host->irq_lock);
1172 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1173 disable_irq_nosync(host->wake_irq);
1174 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1176 spin_unlock(&host->irq_lock);
1177 pm_request_resume(host->dev); /* no use counter */
1182 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1186 OMAP_HSMMC_WRITE(host->base, HCTL,
1187 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1188 for (i = 0; i < loops_per_jiffy; i++) {
1189 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1196 * Switch MMC interface voltage ... only relevant for MMC1.
1198 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1199 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1200 * Some chips, like eMMC ones, use internal transceivers.
1202 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1207 /* Disable the clocks */
1208 pm_runtime_put_sync(host->dev);
1210 clk_disable_unprepare(host->dbclk);
1212 /* Turn the power off */
1213 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1215 /* Turn the power ON with given VDD 1.8 or 3.0v */
1217 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1219 pm_runtime_get_sync(host->dev);
1221 clk_prepare_enable(host->dbclk);
1226 OMAP_HSMMC_WRITE(host->base, HCTL,
1227 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1228 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1231 * If a MMC dual voltage card is detected, the set_ios fn calls
1232 * this fn with VDD bit set for 1.8V. Upon card removal from the
1233 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1235 * Cope with a bit of slop in the range ... per data sheets:
1236 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1237 * but recommended values are 1.71V to 1.89V
1238 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1239 * but recommended values are 2.7V to 3.3V
1241 * Board setup code shouldn't permit anything very out-of-range.
1242 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1243 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1245 if ((1 << vdd) <= MMC_VDD_23_24)
1250 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1251 set_sd_bus_power(host);
1255 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1259 /* Protect the card while the cover is open */
1260 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1262 if (!mmc_slot(host).get_cover_state)
1265 host->reqs_blocked = 0;
1266 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1267 if (host->protect_card) {
1268 dev_info(host->dev, "%s: cover is closed, "
1269 "card is now accessible\n",
1270 mmc_hostname(host->mmc));
1271 host->protect_card = 0;
1274 if (!host->protect_card) {
1275 dev_info(host->dev, "%s: cover is open, "
1276 "card is now inaccessible\n",
1277 mmc_hostname(host->mmc));
1278 host->protect_card = 1;
1284 * irq handler to notify the core about card insertion/removal
1286 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1288 struct omap_hsmmc_host *host = dev_id;
1289 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1292 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1294 if (slot->card_detect)
1295 carddetect = slot->card_detect(host->dev, host->slot_id);
1297 omap_hsmmc_protect_card(host);
1298 carddetect = -ENOSYS;
1302 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1304 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1308 static void omap_hsmmc_dma_callback(void *param)
1310 struct omap_hsmmc_host *host = param;
1311 struct dma_chan *chan;
1312 struct mmc_data *data;
1313 int req_in_progress;
1315 spin_lock_irq(&host->irq_lock);
1316 if (host->dma_ch < 0) {
1317 spin_unlock_irq(&host->irq_lock);
1321 data = host->mrq->data;
1322 chan = omap_hsmmc_get_dma_chan(host, data);
1323 if (!data->host_cookie)
1324 dma_unmap_sg(chan->device->dev,
1325 data->sg, data->sg_len,
1326 omap_hsmmc_get_dma_dir(host, data));
1328 req_in_progress = host->req_in_progress;
1330 spin_unlock_irq(&host->irq_lock);
1332 /* If DMA has finished after TC, complete the request */
1333 if (!req_in_progress) {
1334 struct mmc_request *mrq = host->mrq;
1337 mmc_request_done(host->mmc, mrq);
1341 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1342 struct mmc_data *data,
1343 struct omap_hsmmc_next *next,
1344 struct dma_chan *chan)
1348 if (!next && data->host_cookie &&
1349 data->host_cookie != host->next_data.cookie) {
1350 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1351 " host->next_data.cookie %d\n",
1352 __func__, data->host_cookie, host->next_data.cookie);
1353 data->host_cookie = 0;
1356 /* Check if next job is already prepared */
1357 if (next || data->host_cookie != host->next_data.cookie) {
1358 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1359 omap_hsmmc_get_dma_dir(host, data));
1362 dma_len = host->next_data.dma_len;
1363 host->next_data.dma_len = 0;
1371 next->dma_len = dma_len;
1372 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1374 host->dma_len = dma_len;
1380 * Routine to configure and start DMA for the MMC card
1382 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1383 struct mmc_request *req)
1385 struct dma_slave_config cfg;
1386 struct dma_async_tx_descriptor *tx;
1388 struct mmc_data *data = req->data;
1389 struct dma_chan *chan;
1391 /* Sanity check: all the SG entries must be aligned by block size. */
1392 for (i = 0; i < data->sg_len; i++) {
1393 struct scatterlist *sgl;
1396 if (sgl->length % data->blksz)
1399 if ((data->blksz % 4) != 0)
1400 /* REVISIT: The MMC buffer increments only when MSB is written.
1401 * Return error for blksz which is non multiple of four.
1405 BUG_ON(host->dma_ch != -1);
1407 chan = omap_hsmmc_get_dma_chan(host, data);
1409 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1410 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1411 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1412 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1413 cfg.src_maxburst = data->blksz / 4;
1414 cfg.dst_maxburst = data->blksz / 4;
1416 ret = dmaengine_slave_config(chan, &cfg);
1420 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1424 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1425 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1426 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1428 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1429 /* FIXME: cleanup */
1433 tx->callback = omap_hsmmc_dma_callback;
1434 tx->callback_param = host;
1437 dmaengine_submit(tx);
1444 static void set_data_timeout(struct omap_hsmmc_host *host,
1445 unsigned int timeout_ns,
1446 unsigned int timeout_clks)
1448 unsigned int timeout, cycle_ns;
1449 uint32_t reg, clkd, dto = 0;
1451 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1452 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1456 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1457 timeout = timeout_ns / cycle_ns;
1458 timeout += timeout_clks;
1460 while ((timeout & 0x80000000) == 0) {
1477 reg |= dto << DTO_SHIFT;
1478 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1481 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1483 struct mmc_request *req = host->mrq;
1484 struct dma_chan *chan;
1488 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1489 | (req->data->blocks << 16));
1490 set_data_timeout(host, req->data->timeout_ns,
1491 req->data->timeout_clks);
1492 chan = omap_hsmmc_get_dma_chan(host, req->data);
1493 dma_async_issue_pending(chan);
1497 * Configure block length for MMC/SD cards and initiate the transfer.
1500 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1503 host->data = req->data;
1505 if (req->data == NULL) {
1506 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1508 * Set an arbitrary 100ms data timeout for commands with
1511 if (req->cmd->flags & MMC_RSP_BUSY)
1512 set_data_timeout(host, 100000000U, 0);
1516 if (host->use_dma) {
1517 ret = omap_hsmmc_setup_dma_transfer(host, req);
1519 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1526 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1529 struct omap_hsmmc_host *host = mmc_priv(mmc);
1530 struct mmc_data *data = mrq->data;
1532 if (host->use_dma && data->host_cookie) {
1533 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1535 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1536 omap_hsmmc_get_dma_dir(host, data));
1537 data->host_cookie = 0;
1541 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1544 struct omap_hsmmc_host *host = mmc_priv(mmc);
1546 if (mrq->data->host_cookie) {
1547 mrq->data->host_cookie = 0;
1551 if (host->use_dma) {
1552 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1554 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1555 &host->next_data, c))
1556 mrq->data->host_cookie = 0;
1561 * Request function. for read/write operation
1563 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1565 struct omap_hsmmc_host *host = mmc_priv(mmc);
1568 BUG_ON(host->req_in_progress);
1569 BUG_ON(host->dma_ch != -1);
1570 if (host->protect_card) {
1571 if (host->reqs_blocked < 3) {
1573 * Ensure the controller is left in a consistent
1574 * state by resetting the command and data state
1577 omap_hsmmc_reset_controller_fsm(host, SRD);
1578 omap_hsmmc_reset_controller_fsm(host, SRC);
1579 host->reqs_blocked += 1;
1581 req->cmd->error = -EBADF;
1583 req->data->error = -EBADF;
1584 req->cmd->retries = 0;
1585 mmc_request_done(mmc, req);
1587 } else if (host->reqs_blocked)
1588 host->reqs_blocked = 0;
1589 WARN_ON(host->mrq != NULL);
1591 host->clk_rate = clk_get_rate(host->fclk);
1592 err = omap_hsmmc_prepare_data(host, req);
1594 req->cmd->error = err;
1596 req->data->error = err;
1598 mmc_request_done(mmc, req);
1601 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1602 omap_hsmmc_start_command(host, req->sbc, NULL);
1606 omap_hsmmc_start_dma_transfer(host);
1607 omap_hsmmc_start_command(host, req->cmd, req->data);
1610 /* Routine to configure clock values. Exposed API to core */
1611 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1613 struct omap_hsmmc_host *host = mmc_priv(mmc);
1614 int do_send_init_stream = 0;
1616 pm_runtime_get_sync(host->dev);
1618 if (ios->power_mode != host->power_mode) {
1619 switch (ios->power_mode) {
1621 mmc_slot(host).set_power(host->dev, host->slot_id,
1625 mmc_slot(host).set_power(host->dev, host->slot_id,
1629 do_send_init_stream = 1;
1632 host->power_mode = ios->power_mode;
1635 /* FIXME: set registers based only on changes to ios */
1637 omap_hsmmc_set_bus_width(host);
1639 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1640 /* Only MMC1 can interface at 3V without some flavor
1641 * of external transceiver; but they all handle 1.8V.
1643 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1644 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1646 * The mmc_select_voltage fn of the core does
1647 * not seem to set the power_mode to
1648 * MMC_POWER_UP upon recalculating the voltage.
1651 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1652 dev_dbg(mmc_dev(host->mmc),
1653 "Switch operation failed\n");
1657 omap_hsmmc_set_clock(host);
1659 if (do_send_init_stream)
1660 send_init_stream(host);
1662 omap_hsmmc_set_bus_mode(host);
1664 pm_runtime_put_autosuspend(host->dev);
1667 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1669 struct omap_hsmmc_host *host = mmc_priv(mmc);
1671 if (!mmc_slot(host).card_detect)
1673 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1676 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1678 struct omap_hsmmc_host *host = mmc_priv(mmc);
1680 if (!mmc_slot(host).get_ro)
1682 return mmc_slot(host).get_ro(host->dev, 0);
1685 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1687 struct omap_hsmmc_host *host = mmc_priv(mmc);
1689 if (mmc_slot(host).init_card)
1690 mmc_slot(host).init_card(card);
1693 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1695 struct omap_hsmmc_host *host = mmc_priv(mmc);
1697 unsigned long flags;
1699 spin_lock_irqsave(&host->irq_lock, flags);
1701 con = OMAP_HSMMC_READ(host->base, CON);
1702 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1704 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1705 irq_mask |= CIRQ_EN;
1706 con |= CTPL | CLKEXTFREE;
1708 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1709 irq_mask &= ~CIRQ_EN;
1710 con &= ~(CTPL | CLKEXTFREE);
1712 OMAP_HSMMC_WRITE(host->base, CON, con);
1713 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1716 * if enable, piggy back detection on current request
1717 * but always disable immediately
1719 if (!host->req_in_progress || !enable)
1720 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1722 /* flush posted write */
1723 OMAP_HSMMC_READ(host->base, IE);
1725 spin_unlock_irqrestore(&host->irq_lock, flags);
1728 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1730 struct mmc_host *mmc = host->mmc;
1734 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1735 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1736 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1737 * with functional clock disabled.
1739 if (!host->dev->of_node || !host->wake_irq)
1742 /* Prevent auto-enabling of IRQ */
1743 irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1744 ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1745 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1746 mmc_hostname(mmc), host);
1748 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1753 * Some omaps don't have wake-up path from deeper idle states
1754 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1756 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1757 struct pinctrl *p = devm_pinctrl_get(host->dev);
1762 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1763 dev_info(host->dev, "missing default pinctrl state\n");
1764 devm_pinctrl_put(p);
1769 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1770 dev_info(host->dev, "missing idle pinctrl state\n");
1771 devm_pinctrl_put(p);
1775 devm_pinctrl_put(p);
1778 OMAP_HSMMC_WRITE(host->base, HCTL,
1779 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1783 devm_free_irq(host->dev, host->wake_irq, host);
1785 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1790 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1792 u32 hctl, capa, value;
1794 /* Only MMC1 supports 3.0V */
1795 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1803 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1804 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1806 value = OMAP_HSMMC_READ(host->base, CAPA);
1807 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1809 /* Set SD bus power bit */
1810 set_sd_bus_power(host);
1813 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1815 struct omap_hsmmc_host *host = mmc_priv(mmc);
1817 pm_runtime_get_sync(host->dev);
1822 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1824 struct omap_hsmmc_host *host = mmc_priv(mmc);
1826 pm_runtime_mark_last_busy(host->dev);
1827 pm_runtime_put_autosuspend(host->dev);
1832 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1833 unsigned int direction, int blk_size)
1835 /* This controller can't do multiblock reads due to hw bugs */
1836 if (direction == MMC_DATA_READ)
1842 static struct mmc_host_ops omap_hsmmc_ops = {
1843 .enable = omap_hsmmc_enable_fclk,
1844 .disable = omap_hsmmc_disable_fclk,
1845 .post_req = omap_hsmmc_post_req,
1846 .pre_req = omap_hsmmc_pre_req,
1847 .request = omap_hsmmc_request,
1848 .set_ios = omap_hsmmc_set_ios,
1849 .get_cd = omap_hsmmc_get_cd,
1850 .get_ro = omap_hsmmc_get_ro,
1851 .init_card = omap_hsmmc_init_card,
1852 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1855 #ifdef CONFIG_DEBUG_FS
1857 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1859 struct mmc_host *mmc = s->private;
1860 struct omap_hsmmc_host *host = mmc_priv(mmc);
1862 seq_printf(s, "mmc%d:\n", mmc->index);
1863 seq_printf(s, "sdio irq mode\t%s\n",
1864 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1866 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1867 seq_printf(s, "sdio irq \t%s\n",
1868 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1871 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1873 pm_runtime_get_sync(host->dev);
1874 seq_puts(s, "\nregs:\n");
1875 seq_printf(s, "CON:\t\t0x%08x\n",
1876 OMAP_HSMMC_READ(host->base, CON));
1877 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1878 OMAP_HSMMC_READ(host->base, PSTATE));
1879 seq_printf(s, "HCTL:\t\t0x%08x\n",
1880 OMAP_HSMMC_READ(host->base, HCTL));
1881 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1882 OMAP_HSMMC_READ(host->base, SYSCTL));
1883 seq_printf(s, "IE:\t\t0x%08x\n",
1884 OMAP_HSMMC_READ(host->base, IE));
1885 seq_printf(s, "ISE:\t\t0x%08x\n",
1886 OMAP_HSMMC_READ(host->base, ISE));
1887 seq_printf(s, "CAPA:\t\t0x%08x\n",
1888 OMAP_HSMMC_READ(host->base, CAPA));
1890 pm_runtime_mark_last_busy(host->dev);
1891 pm_runtime_put_autosuspend(host->dev);
1896 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1898 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1901 static const struct file_operations mmc_regs_fops = {
1902 .open = omap_hsmmc_regs_open,
1904 .llseek = seq_lseek,
1905 .release = single_release,
1908 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1910 if (mmc->debugfs_root)
1911 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1912 mmc, &mmc_regs_fops);
1917 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1924 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1925 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1926 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1929 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1930 .reg_offset = 0x100,
1932 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1933 .reg_offset = 0x100,
1934 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1937 static const struct of_device_id omap_mmc_of_match[] = {
1939 .compatible = "ti,omap2-hsmmc",
1942 .compatible = "ti,omap3-pre-es3-hsmmc",
1943 .data = &omap3_pre_es3_mmc_of_data,
1946 .compatible = "ti,omap3-hsmmc",
1949 .compatible = "ti,omap4-hsmmc",
1950 .data = &omap4_mmc_of_data,
1953 .compatible = "ti,am33xx-hsmmc",
1954 .data = &am33xx_mmc_of_data,
1958 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1960 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1962 struct omap_mmc_platform_data *pdata;
1963 struct device_node *np = dev->of_node;
1964 u32 bus_width, max_freq;
1965 int cd_gpio, wp_gpio;
1967 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1968 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1969 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1970 return ERR_PTR(-EPROBE_DEFER);
1972 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1974 return ERR_PTR(-ENOMEM); /* out of memory */
1976 if (of_find_property(np, "ti,dual-volt", NULL))
1977 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1979 /* This driver only supports 1 slot */
1980 pdata->nr_slots = 1;
1981 pdata->slots[0].switch_pin = cd_gpio;
1982 pdata->slots[0].gpio_wp = wp_gpio;
1984 if (of_find_property(np, "ti,non-removable", NULL)) {
1985 pdata->slots[0].nonremovable = true;
1986 pdata->slots[0].no_regulator_off_init = true;
1988 of_property_read_u32(np, "bus-width", &bus_width);
1990 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1991 else if (bus_width == 8)
1992 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1994 if (of_find_property(np, "ti,needs-special-reset", NULL))
1995 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1997 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1998 pdata->max_freq = max_freq;
2000 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
2001 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
2003 if (of_find_property(np, "keep-power-in-suspend", NULL))
2004 pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER;
2006 if (of_find_property(np, "enable-sdio-wakeup", NULL))
2007 pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2012 static inline struct omap_mmc_platform_data
2013 *of_get_hsmmc_pdata(struct device *dev)
2015 return ERR_PTR(-EINVAL);
2019 static int omap_hsmmc_probe(struct platform_device *pdev)
2021 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2022 struct mmc_host *mmc;
2023 struct omap_hsmmc_host *host = NULL;
2024 struct resource *res;
2026 const struct of_device_id *match;
2027 dma_cap_mask_t mask;
2028 unsigned tx_req, rx_req;
2029 const struct omap_mmc_of_data *data;
2032 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2034 pdata = of_get_hsmmc_pdata(&pdev->dev);
2037 return PTR_ERR(pdata);
2041 pdata->reg_offset = data->reg_offset;
2042 pdata->controller_flags |= data->controller_flags;
2046 if (pdata == NULL) {
2047 dev_err(&pdev->dev, "Platform Data is missing\n");
2051 if (pdata->nr_slots == 0) {
2052 dev_err(&pdev->dev, "No Slots\n");
2056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2057 irq = platform_get_irq(pdev, 0);
2058 if (res == NULL || irq < 0)
2061 base = devm_ioremap_resource(&pdev->dev, res);
2063 return PTR_ERR(base);
2065 ret = omap_hsmmc_gpio_init(pdata);
2069 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2075 host = mmc_priv(mmc);
2077 host->pdata = pdata;
2078 host->dev = &pdev->dev;
2083 host->mapbase = res->start + pdata->reg_offset;
2084 host->base = base + pdata->reg_offset;
2085 host->power_mode = MMC_POWER_OFF;
2086 host->next_data.cookie = 1;
2087 host->pbias_enabled = 0;
2089 platform_set_drvdata(pdev, host);
2091 if (pdev->dev.of_node)
2092 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2094 mmc->ops = &omap_hsmmc_ops;
2096 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2098 if (pdata->max_freq > 0)
2099 mmc->f_max = pdata->max_freq;
2101 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2103 spin_lock_init(&host->irq_lock);
2105 host->fclk = devm_clk_get(&pdev->dev, "fck");
2106 if (IS_ERR(host->fclk)) {
2107 ret = PTR_ERR(host->fclk);
2112 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2113 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2114 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2117 pm_runtime_enable(host->dev);
2118 pm_runtime_get_sync(host->dev);
2119 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2120 pm_runtime_use_autosuspend(host->dev);
2122 omap_hsmmc_context_save(host);
2124 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2126 * MMC can still work without debounce clock.
2128 if (IS_ERR(host->dbclk)) {
2130 } else if (clk_prepare_enable(host->dbclk) != 0) {
2131 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2135 /* Since we do only SG emulation, we can have as many segs
2137 mmc->max_segs = 1024;
2139 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2140 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2141 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2142 mmc->max_seg_size = mmc->max_req_size;
2144 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2145 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2147 mmc->caps |= mmc_slot(host).caps;
2148 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2149 mmc->caps |= MMC_CAP_4_BIT_DATA;
2151 if (mmc_slot(host).nonremovable)
2152 mmc->caps |= MMC_CAP_NONREMOVABLE;
2154 mmc->pm_caps = mmc_slot(host).pm_caps;
2156 omap_hsmmc_conf_bus_power(host);
2158 if (!pdev->dev.of_node) {
2159 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2161 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2165 tx_req = res->start;
2167 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2169 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2173 rx_req = res->start;
2177 dma_cap_set(DMA_SLAVE, mask);
2180 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2181 &rx_req, &pdev->dev, "rx");
2183 if (!host->rx_chan) {
2184 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2190 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2191 &tx_req, &pdev->dev, "tx");
2193 if (!host->tx_chan) {
2194 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2199 /* Request IRQ for MMC operations */
2200 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2201 mmc_hostname(mmc), host);
2203 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2207 if (pdata->init != NULL) {
2208 if (pdata->init(&pdev->dev) != 0) {
2209 dev_err(mmc_dev(host->mmc),
2210 "Unable to configure MMC IRQs\n");
2215 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2216 ret = omap_hsmmc_reg_get(host);
2222 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2224 /* Request IRQ for card detect */
2225 if ((mmc_slot(host).card_detect_irq)) {
2226 ret = devm_request_threaded_irq(&pdev->dev,
2227 mmc_slot(host).card_detect_irq,
2228 NULL, omap_hsmmc_detect,
2229 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2230 mmc_hostname(mmc), host);
2232 dev_err(mmc_dev(host->mmc),
2233 "Unable to grab MMC CD IRQ\n");
2236 pdata->suspend = omap_hsmmc_suspend_cdirq;
2237 pdata->resume = omap_hsmmc_resume_cdirq;
2240 omap_hsmmc_disable_irq(host);
2243 * For now, only support SDIO interrupt if we have a separate
2244 * wake-up interrupt configured from device tree. This is because
2245 * the wake-up interrupt is needed for idle state and some
2246 * platforms need special quirks. And we don't want to add new
2247 * legacy mux platform init code callbacks any longer as we
2248 * are moving to DT based booting anyways.
2250 ret = omap_hsmmc_configure_wake_irq(host);
2252 mmc->caps |= MMC_CAP_SDIO_IRQ;
2254 omap_hsmmc_protect_card(host);
2258 if (mmc_slot(host).name != NULL) {
2259 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2263 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2264 ret = device_create_file(&mmc->class_dev,
2265 &dev_attr_cover_switch);
2270 omap_hsmmc_debugfs(mmc);
2271 pm_runtime_mark_last_busy(host->dev);
2272 pm_runtime_put_autosuspend(host->dev);
2277 mmc_remove_host(mmc);
2280 omap_hsmmc_reg_put(host);
2282 if (host->pdata->cleanup)
2283 host->pdata->cleanup(&pdev->dev);
2286 dma_release_channel(host->tx_chan);
2288 dma_release_channel(host->rx_chan);
2289 pm_runtime_put_sync(host->dev);
2290 pm_runtime_disable(host->dev);
2292 clk_disable_unprepare(host->dbclk);
2296 omap_hsmmc_gpio_free(pdata);
2301 static int omap_hsmmc_remove(struct platform_device *pdev)
2303 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2305 pm_runtime_get_sync(host->dev);
2306 mmc_remove_host(host->mmc);
2308 omap_hsmmc_reg_put(host);
2309 if (host->pdata->cleanup)
2310 host->pdata->cleanup(&pdev->dev);
2313 dma_release_channel(host->tx_chan);
2315 dma_release_channel(host->rx_chan);
2317 pm_runtime_put_sync(host->dev);
2318 pm_runtime_disable(host->dev);
2320 clk_disable_unprepare(host->dbclk);
2322 omap_hsmmc_gpio_free(host->pdata);
2323 mmc_free_host(host->mmc);
2329 static int omap_hsmmc_prepare(struct device *dev)
2331 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2333 if (host->pdata->suspend)
2334 return host->pdata->suspend(dev, host->slot_id);
2339 static void omap_hsmmc_complete(struct device *dev)
2341 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2343 if (host->pdata->resume)
2344 host->pdata->resume(dev, host->slot_id);
2348 static int omap_hsmmc_suspend(struct device *dev)
2350 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2355 pm_runtime_get_sync(host->dev);
2357 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2358 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2359 OMAP_HSMMC_WRITE(host->base, IE, 0);
2360 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2361 OMAP_HSMMC_WRITE(host->base, HCTL,
2362 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2365 /* do not wake up due to sdio irq */
2366 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2367 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2368 disable_irq(host->wake_irq);
2371 clk_disable_unprepare(host->dbclk);
2373 pm_runtime_put_sync(host->dev);
2377 /* Routine to resume the MMC device */
2378 static int omap_hsmmc_resume(struct device *dev)
2380 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2385 pm_runtime_get_sync(host->dev);
2388 clk_prepare_enable(host->dbclk);
2390 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2391 omap_hsmmc_conf_bus_power(host);
2393 omap_hsmmc_protect_card(host);
2395 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2396 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2397 enable_irq(host->wake_irq);
2399 pm_runtime_mark_last_busy(host->dev);
2400 pm_runtime_put_autosuspend(host->dev);
2405 #define omap_hsmmc_prepare NULL
2406 #define omap_hsmmc_complete NULL
2407 #define omap_hsmmc_suspend NULL
2408 #define omap_hsmmc_resume NULL
2411 static int omap_hsmmc_runtime_suspend(struct device *dev)
2413 struct omap_hsmmc_host *host;
2414 unsigned long flags;
2417 host = platform_get_drvdata(to_platform_device(dev));
2418 omap_hsmmc_context_save(host);
2419 dev_dbg(dev, "disabled\n");
2421 spin_lock_irqsave(&host->irq_lock, flags);
2422 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2423 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2424 /* disable sdio irq handling to prevent race */
2425 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2426 OMAP_HSMMC_WRITE(host->base, IE, 0);
2428 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2430 * dat1 line low, pending sdio irq
2431 * race condition: possible irq handler running on
2434 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2435 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2436 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2437 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2438 pm_runtime_mark_last_busy(dev);
2443 pinctrl_pm_select_idle_state(dev);
2445 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2446 enable_irq(host->wake_irq);
2447 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2449 pinctrl_pm_select_idle_state(dev);
2453 spin_unlock_irqrestore(&host->irq_lock, flags);
2457 static int omap_hsmmc_runtime_resume(struct device *dev)
2459 struct omap_hsmmc_host *host;
2460 unsigned long flags;
2462 host = platform_get_drvdata(to_platform_device(dev));
2463 omap_hsmmc_context_restore(host);
2464 dev_dbg(dev, "enabled\n");
2466 spin_lock_irqsave(&host->irq_lock, flags);
2467 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2468 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2469 /* sdio irq flag can't change while in runtime suspend */
2470 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2471 disable_irq_nosync(host->wake_irq);
2472 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2475 pinctrl_pm_select_default_state(host->dev);
2477 /* irq lost, if pinmux incorrect */
2478 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2479 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2480 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2482 pinctrl_pm_select_default_state(host->dev);
2484 spin_unlock_irqrestore(&host->irq_lock, flags);
2488 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2489 .suspend = omap_hsmmc_suspend,
2490 .resume = omap_hsmmc_resume,
2491 .prepare = omap_hsmmc_prepare,
2492 .complete = omap_hsmmc_complete,
2493 .runtime_suspend = omap_hsmmc_runtime_suspend,
2494 .runtime_resume = omap_hsmmc_runtime_resume,
2497 static struct platform_driver omap_hsmmc_driver = {
2498 .probe = omap_hsmmc_probe,
2499 .remove = omap_hsmmc_remove,
2501 .name = DRIVER_NAME,
2502 .pm = &omap_hsmmc_dev_pm_ops,
2503 .of_match_table = of_match_ptr(omap_mmc_of_match),
2507 module_platform_driver(omap_hsmmc_driver);
2508 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2509 MODULE_LICENSE("GPL");
2510 MODULE_ALIAS("platform:" DRIVER_NAME);
2511 MODULE_AUTHOR("Texas Instruments Inc");