2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG 0x0010
45 #define OMAP_HSMMC_SYSSTATUS 0x0014
46 #define OMAP_HSMMC_CON 0x002C
47 #define OMAP_HSMMC_BLK 0x0104
48 #define OMAP_HSMMC_ARG 0x0108
49 #define OMAP_HSMMC_CMD 0x010C
50 #define OMAP_HSMMC_RSP10 0x0110
51 #define OMAP_HSMMC_RSP32 0x0114
52 #define OMAP_HSMMC_RSP54 0x0118
53 #define OMAP_HSMMC_RSP76 0x011C
54 #define OMAP_HSMMC_DATA 0x0120
55 #define OMAP_HSMMC_HCTL 0x0128
56 #define OMAP_HSMMC_SYSCTL 0x012C
57 #define OMAP_HSMMC_STAT 0x0130
58 #define OMAP_HSMMC_IE 0x0134
59 #define OMAP_HSMMC_ISE 0x0138
60 #define OMAP_HSMMC_CAPA 0x0140
62 #define VS18 (1 << 26)
63 #define VS30 (1 << 25)
64 #define SDVS18 (0x5 << 9)
65 #define SDVS30 (0x6 << 9)
66 #define SDVS33 (0x7 << 9)
67 #define SDVS_MASK 0x00000E00
68 #define SDVSCLR 0xFFFFF1FF
69 #define SDVSDET 0x00000400
76 #define CLKD_MASK 0x0000FFC0
78 #define DTO_MASK 0x000F0000
80 #define INT_EN_MASK 0x307F0033
81 #define BWR_ENABLE (1 << 4)
82 #define BRR_ENABLE (1 << 5)
83 #define DTO_ENABLE (1 << 20)
84 #define INIT_STREAM (1 << 1)
85 #define DP_SELECT (1 << 21)
90 #define FOUR_BIT (1 << 1)
96 #define CMD_TIMEOUT (1 << 16)
97 #define DATA_TIMEOUT (1 << 20)
98 #define CMD_CRC (1 << 17)
99 #define DATA_CRC (1 << 21)
100 #define CARD_ERR (1 << 28)
101 #define STAT_CLEAR 0xFFFFFFFF
102 #define INIT_STREAM_CMD 0x00000000
103 #define DUAL_VOLT_OCR_BIT 7
104 #define SRC (1 << 25)
105 #define SRD (1 << 26)
106 #define SOFTRESET (1 << 1)
107 #define RESETDONE (1 << 0)
110 * FIXME: Most likely all the data using these _DEVID defines should come
111 * from the platform_data, or implemented in controller and slot specific
114 #define OMAP_MMC1_DEVID 0
115 #define OMAP_MMC2_DEVID 1
116 #define OMAP_MMC3_DEVID 2
117 #define OMAP_MMC4_DEVID 3
118 #define OMAP_MMC5_DEVID 4
120 #define MMC_AUTOSUSPEND_DELAY 100
121 #define MMC_TIMEOUT_MS 20
122 #define OMAP_MMC_MIN_CLOCK 400000
123 #define OMAP_MMC_MAX_CLOCK 52000000
124 #define DRIVER_NAME "omap_hsmmc"
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
131 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134 * MMC Host controller read/write API's
136 #define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142 struct omap_hsmmc_next {
143 unsigned int dma_len;
147 struct omap_hsmmc_host {
149 struct mmc_host *mmc;
150 struct mmc_request *mrq;
151 struct mmc_command *cmd;
152 struct mmc_data *data;
156 * vcc == configured supply
157 * vcc_aux == optional
158 * - MMC1, supply for DAT4..DAT7
159 * - MMC2/MMC2, external level shifter voltage supply, for
160 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
162 struct regulator *vcc;
163 struct regulator *vcc_aux;
165 resource_size_t mapbase;
166 spinlock_t irq_lock; /* Prevent races with irq handler */
168 unsigned int dma_len;
169 unsigned int dma_sg_idx;
170 unsigned char bus_mode;
171 unsigned char power_mode;
177 int dma_line_tx, dma_line_rx;
188 struct omap_hsmmc_next next_data;
190 struct omap_mmc_platform_data *pdata;
193 static int omap_hsmmc_card_detect(struct device *dev, int slot)
195 struct omap_mmc_platform_data *mmc = dev->platform_data;
197 /* NOTE: assumes card detect signal is active-low */
198 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
201 static int omap_hsmmc_get_wp(struct device *dev, int slot)
203 struct omap_mmc_platform_data *mmc = dev->platform_data;
205 /* NOTE: assumes write protect signal is active-high */
206 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
209 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
211 struct omap_mmc_platform_data *mmc = dev->platform_data;
213 /* NOTE: assumes card detect signal is active-low */
214 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
221 struct omap_mmc_platform_data *mmc = dev->platform_data;
223 disable_irq(mmc->slots[0].card_detect_irq);
227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
229 struct omap_mmc_platform_data *mmc = dev->platform_data;
231 enable_irq(mmc->slots[0].card_detect_irq);
237 #define omap_hsmmc_suspend_cdirq NULL
238 #define omap_hsmmc_resume_cdirq NULL
242 #ifdef CONFIG_REGULATOR
244 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
247 struct omap_hsmmc_host *host =
248 platform_get_drvdata(to_platform_device(dev));
252 * If we don't see a Vcc regulator, assume it's a fixed
253 * voltage always-on regulator.
258 if (mmc_slot(host).before_set_reg)
259 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
262 * Assume Vcc regulator is used only to power the card ... OMAP
263 * VDDS is used to power the pins, optionally with a transceiver to
264 * support cards using voltages other than VDDS (1.8V nominal). When a
265 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
267 * In some cases this regulator won't support enable/disable;
268 * e.g. it's a fixed rail for a WLAN chip.
270 * In other cases vcc_aux switches interface power. Example, for
271 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
272 * chips/cards need an interface voltage rail too.
275 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
276 /* Enable interface voltage rail, if needed */
277 if (ret == 0 && host->vcc_aux) {
278 ret = regulator_enable(host->vcc_aux);
280 ret = mmc_regulator_set_ocr(host->mmc,
284 /* Shut down the rail */
286 ret = regulator_disable(host->vcc_aux);
288 /* Then proceed to shut down the local regulator */
289 ret = mmc_regulator_set_ocr(host->mmc,
294 if (mmc_slot(host).after_set_reg)
295 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
300 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
302 struct regulator *reg;
306 mmc_slot(host).set_power = omap_hsmmc_set_power;
308 reg = regulator_get(host->dev, "vmmc");
310 dev_dbg(host->dev, "vmmc regulator missing\n");
312 * HACK: until fixed.c regulator is usable,
313 * we don't require a main regulator
316 if (host->id == OMAP_MMC1_DEVID) {
322 ocr_value = mmc_regulator_get_ocrmask(reg);
323 if (!mmc_slot(host).ocr_mask) {
324 mmc_slot(host).ocr_mask = ocr_value;
326 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
327 pr_err("MMC%d ocrmask %x is not supported\n",
328 host->id, mmc_slot(host).ocr_mask);
329 mmc_slot(host).ocr_mask = 0;
334 /* Allow an aux regulator */
335 reg = regulator_get(host->dev, "vmmc_aux");
336 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
338 /* For eMMC do not power off when not in sleep state */
339 if (mmc_slot(host).no_regulator_off_init)
342 * UGLY HACK: workaround regulator framework bugs.
343 * When the bootloader leaves a supply active, it's
344 * initialized with zero usecount ... and we can't
345 * disable it without first enabling it. Until the
346 * framework is fixed, we need a workaround like this
347 * (which is safe for MMC, but not in general).
349 if (regulator_is_enabled(host->vcc) > 0 ||
350 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
351 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
353 mmc_slot(host).set_power(host->dev, host->slot_id,
355 mmc_slot(host).set_power(host->dev, host->slot_id,
363 mmc_slot(host).set_power = NULL;
367 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
369 regulator_put(host->vcc);
370 regulator_put(host->vcc_aux);
371 mmc_slot(host).set_power = NULL;
374 static inline int omap_hsmmc_have_reg(void)
381 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
390 static inline int omap_hsmmc_have_reg(void)
397 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
401 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
402 if (pdata->slots[0].cover)
403 pdata->slots[0].get_cover_state =
404 omap_hsmmc_get_cover_state;
406 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
407 pdata->slots[0].card_detect_irq =
408 gpio_to_irq(pdata->slots[0].switch_pin);
409 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
412 ret = gpio_direction_input(pdata->slots[0].switch_pin);
416 pdata->slots[0].switch_pin = -EINVAL;
418 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
419 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
420 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
423 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
427 pdata->slots[0].gpio_wp = -EINVAL;
432 gpio_free(pdata->slots[0].gpio_wp);
434 if (gpio_is_valid(pdata->slots[0].switch_pin))
436 gpio_free(pdata->slots[0].switch_pin);
440 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
442 if (gpio_is_valid(pdata->slots[0].gpio_wp))
443 gpio_free(pdata->slots[0].gpio_wp);
444 if (gpio_is_valid(pdata->slots[0].switch_pin))
445 gpio_free(pdata->slots[0].switch_pin);
449 * Start clock to the card
451 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
453 OMAP_HSMMC_WRITE(host->base, SYSCTL,
454 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
458 * Stop clock to the card
460 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
462 OMAP_HSMMC_WRITE(host->base, SYSCTL,
463 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
464 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
465 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
468 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
469 struct mmc_command *cmd)
471 unsigned int irq_mask;
474 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
476 irq_mask = INT_EN_MASK;
478 /* Disable timeout for erases */
479 if (cmd->opcode == MMC_ERASE)
480 irq_mask &= ~DTO_ENABLE;
482 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
483 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
484 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
487 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
489 OMAP_HSMMC_WRITE(host->base, ISE, 0);
490 OMAP_HSMMC_WRITE(host->base, IE, 0);
491 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
494 /* Calculate divisor for the given clock frequency */
495 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
500 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
508 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
510 struct mmc_ios *ios = &host->mmc->ios;
511 unsigned long regval;
512 unsigned long timeout;
514 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
516 omap_hsmmc_stop_clock(host);
518 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
519 regval = regval & ~(CLKD_MASK | DTO_MASK);
520 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
521 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
522 OMAP_HSMMC_WRITE(host->base, SYSCTL,
523 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
525 /* Wait till the ICS bit is set */
526 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
527 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
528 && time_before(jiffies, timeout))
531 omap_hsmmc_start_clock(host);
534 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
536 struct mmc_ios *ios = &host->mmc->ios;
539 con = OMAP_HSMMC_READ(host->base, CON);
540 switch (ios->bus_width) {
541 case MMC_BUS_WIDTH_8:
542 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
544 case MMC_BUS_WIDTH_4:
545 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
546 OMAP_HSMMC_WRITE(host->base, HCTL,
547 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
549 case MMC_BUS_WIDTH_1:
550 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
551 OMAP_HSMMC_WRITE(host->base, HCTL,
552 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
557 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
559 struct mmc_ios *ios = &host->mmc->ios;
562 con = OMAP_HSMMC_READ(host->base, CON);
563 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
564 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
566 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
572 * Restore the MMC host context, if it was lost as result of a
573 * power state change.
575 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
577 struct mmc_ios *ios = &host->mmc->ios;
578 struct omap_mmc_platform_data *pdata = host->pdata;
579 int context_loss = 0;
581 unsigned long timeout;
583 if (pdata->get_context_loss_count) {
584 context_loss = pdata->get_context_loss_count(host->dev);
585 if (context_loss < 0)
589 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
590 context_loss == host->context_loss ? "not " : "");
591 if (host->context_loss == context_loss)
594 /* Wait for hardware reset */
595 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
596 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
597 && time_before(jiffies, timeout))
600 /* Do software reset */
601 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
602 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
603 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
604 && time_before(jiffies, timeout))
607 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
608 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
610 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
611 if (host->power_mode != MMC_POWER_OFF &&
612 (1 << ios->vdd) <= MMC_VDD_23_24)
622 OMAP_HSMMC_WRITE(host->base, HCTL,
623 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
625 OMAP_HSMMC_WRITE(host->base, CAPA,
626 OMAP_HSMMC_READ(host->base, CAPA) | capa);
628 OMAP_HSMMC_WRITE(host->base, HCTL,
629 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
631 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
632 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
633 && time_before(jiffies, timeout))
636 omap_hsmmc_disable_irq(host);
638 /* Do not initialize card-specific things if the power is off */
639 if (host->power_mode == MMC_POWER_OFF)
642 omap_hsmmc_set_bus_width(host);
644 omap_hsmmc_set_clock(host);
646 omap_hsmmc_set_bus_mode(host);
649 host->context_loss = context_loss;
651 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
656 * Save the MMC host context (store the number of power state changes so far).
658 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
660 struct omap_mmc_platform_data *pdata = host->pdata;
663 if (pdata->get_context_loss_count) {
664 context_loss = pdata->get_context_loss_count(host->dev);
665 if (context_loss < 0)
667 host->context_loss = context_loss;
673 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
678 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
685 * Send init stream sequence to card
686 * before sending IDLE command
688 static void send_init_stream(struct omap_hsmmc_host *host)
691 unsigned long timeout;
693 if (host->protect_card)
696 disable_irq(host->irq);
698 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
699 OMAP_HSMMC_WRITE(host->base, CON,
700 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
701 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
703 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
704 while ((reg != CC) && time_before(jiffies, timeout))
705 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
707 OMAP_HSMMC_WRITE(host->base, CON,
708 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
710 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
711 OMAP_HSMMC_READ(host->base, STAT);
713 enable_irq(host->irq);
717 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
721 if (mmc_slot(host).get_cover_state)
722 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
727 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
730 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
731 struct omap_hsmmc_host *host = mmc_priv(mmc);
733 return sprintf(buf, "%s\n",
734 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
737 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
740 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
743 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
744 struct omap_hsmmc_host *host = mmc_priv(mmc);
746 return sprintf(buf, "%s\n", mmc_slot(host).name);
749 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
752 * Configure the response type and send the cmd.
755 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
756 struct mmc_data *data)
758 int cmdreg = 0, resptype = 0, cmdtype = 0;
760 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
761 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
764 omap_hsmmc_enable_irq(host, cmd);
766 host->response_busy = 0;
767 if (cmd->flags & MMC_RSP_PRESENT) {
768 if (cmd->flags & MMC_RSP_136)
770 else if (cmd->flags & MMC_RSP_BUSY) {
772 host->response_busy = 1;
778 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
779 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
780 * a val of 0x3, rest 0x0.
782 if (cmd == host->mrq->stop)
785 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
788 cmdreg |= DP_SELECT | MSBS | BCE;
789 if (data->flags & MMC_DATA_READ)
798 host->req_in_progress = 1;
800 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
801 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
805 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
807 if (data->flags & MMC_DATA_WRITE)
808 return DMA_TO_DEVICE;
810 return DMA_FROM_DEVICE;
813 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
817 spin_lock(&host->irq_lock);
818 host->req_in_progress = 0;
819 dma_ch = host->dma_ch;
820 spin_unlock(&host->irq_lock);
822 omap_hsmmc_disable_irq(host);
823 /* Do not complete the request if DMA is still in progress */
824 if (mrq->data && host->use_dma && dma_ch != -1)
827 mmc_request_done(host->mmc, mrq);
831 * Notify the transfer complete to MMC core
834 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
837 struct mmc_request *mrq = host->mrq;
839 /* TC before CC from CMD6 - don't know why, but it happens */
840 if (host->cmd && host->cmd->opcode == 6 &&
841 host->response_busy) {
842 host->response_busy = 0;
846 omap_hsmmc_request_done(host, mrq);
853 data->bytes_xfered += data->blocks * (data->blksz);
855 data->bytes_xfered = 0;
858 omap_hsmmc_request_done(host, data->mrq);
861 omap_hsmmc_start_command(host, data->stop, NULL);
865 * Notify the core about command completion
868 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
872 if (cmd->flags & MMC_RSP_PRESENT) {
873 if (cmd->flags & MMC_RSP_136) {
874 /* response type 2 */
875 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
876 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
877 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
878 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
880 /* response types 1, 1b, 3, 4, 5, 6 */
881 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
884 if ((host->data == NULL && !host->response_busy) || cmd->error)
885 omap_hsmmc_request_done(host, cmd->mrq);
889 * DMA clean up for command errors
891 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
895 host->data->error = errno;
897 spin_lock(&host->irq_lock);
898 dma_ch = host->dma_ch;
900 spin_unlock(&host->irq_lock);
902 if (host->use_dma && dma_ch != -1) {
903 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
905 omap_hsmmc_get_dma_dir(host, host->data));
906 omap_free_dma(dma_ch);
907 host->data->host_cookie = 0;
913 * Readable error output
915 #ifdef CONFIG_MMC_DEBUG
916 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
918 /* --- means reserved bit without definition at documentation */
919 static const char *omap_hsmmc_status_bits[] = {
920 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
921 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
922 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
923 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
929 len = sprintf(buf, "MMC IRQ 0x%x :", status);
932 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
933 if (status & (1 << i)) {
934 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
938 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
941 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
945 #endif /* CONFIG_MMC_DEBUG */
948 * MMC controller internal state machines reset
950 * Used to reset command or data internal state machines, using respectively
951 * SRC or SRD bit of SYSCTL register
952 * Can be called from interrupt context
954 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
958 unsigned long limit = (loops_per_jiffy *
959 msecs_to_jiffies(MMC_TIMEOUT_MS));
961 OMAP_HSMMC_WRITE(host->base, SYSCTL,
962 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
965 * OMAP4 ES2 and greater has an updated reset logic.
966 * Monitor a 0->1 transition first
968 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
969 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
975 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
979 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
980 dev_err(mmc_dev(host->mmc),
981 "Timeout waiting on controller reset in %s\n",
985 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
987 struct mmc_data *data;
988 int end_cmd = 0, end_trans = 0;
990 if (!host->req_in_progress) {
992 OMAP_HSMMC_WRITE(host->base, STAT, status);
993 /* Flush posted write */
994 status = OMAP_HSMMC_READ(host->base, STAT);
995 } while (status & INT_EN_MASK);
1000 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1003 omap_hsmmc_dbg_report_irq(host, status);
1004 if ((status & CMD_TIMEOUT) ||
1005 (status & CMD_CRC)) {
1007 if (status & CMD_TIMEOUT) {
1008 omap_hsmmc_reset_controller_fsm(host,
1010 host->cmd->error = -ETIMEDOUT;
1012 host->cmd->error = -EILSEQ;
1016 if (host->data || host->response_busy) {
1018 omap_hsmmc_dma_cleanup(host,
1020 host->response_busy = 0;
1021 omap_hsmmc_reset_controller_fsm(host, SRD);
1024 if ((status & DATA_TIMEOUT) ||
1025 (status & DATA_CRC)) {
1026 if (host->data || host->response_busy) {
1027 int err = (status & DATA_TIMEOUT) ?
1028 -ETIMEDOUT : -EILSEQ;
1031 omap_hsmmc_dma_cleanup(host, err);
1033 host->mrq->cmd->error = err;
1034 host->response_busy = 0;
1035 omap_hsmmc_reset_controller_fsm(host, SRD);
1039 if (status & CARD_ERR) {
1040 dev_dbg(mmc_dev(host->mmc),
1041 "Ignoring card err CMD%d\n", host->cmd->opcode);
1049 OMAP_HSMMC_WRITE(host->base, STAT, status);
1051 if (end_cmd || ((status & CC) && host->cmd))
1052 omap_hsmmc_cmd_done(host, host->cmd);
1053 if ((end_trans || (status & TC)) && host->mrq)
1054 omap_hsmmc_xfer_done(host, data);
1058 * MMC controller IRQ handler
1060 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1062 struct omap_hsmmc_host *host = dev_id;
1065 status = OMAP_HSMMC_READ(host->base, STAT);
1067 omap_hsmmc_do_irq(host, status);
1068 /* Flush posted write */
1069 status = OMAP_HSMMC_READ(host->base, STAT);
1070 } while (status & INT_EN_MASK);
1075 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1079 OMAP_HSMMC_WRITE(host->base, HCTL,
1080 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1081 for (i = 0; i < loops_per_jiffy; i++) {
1082 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1089 * Switch MMC interface voltage ... only relevant for MMC1.
1091 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1092 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1093 * Some chips, like eMMC ones, use internal transceivers.
1095 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1100 /* Disable the clocks */
1101 pm_runtime_put_sync(host->dev);
1102 if (host->got_dbclk)
1103 clk_disable(host->dbclk);
1105 /* Turn the power off */
1106 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1108 /* Turn the power ON with given VDD 1.8 or 3.0v */
1110 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1112 pm_runtime_get_sync(host->dev);
1113 if (host->got_dbclk)
1114 clk_enable(host->dbclk);
1119 OMAP_HSMMC_WRITE(host->base, HCTL,
1120 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1121 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1124 * If a MMC dual voltage card is detected, the set_ios fn calls
1125 * this fn with VDD bit set for 1.8V. Upon card removal from the
1126 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1128 * Cope with a bit of slop in the range ... per data sheets:
1129 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1130 * but recommended values are 1.71V to 1.89V
1131 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1132 * but recommended values are 2.7V to 3.3V
1134 * Board setup code shouldn't permit anything very out-of-range.
1135 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1136 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1138 if ((1 << vdd) <= MMC_VDD_23_24)
1143 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1144 set_sd_bus_power(host);
1148 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1152 /* Protect the card while the cover is open */
1153 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1155 if (!mmc_slot(host).get_cover_state)
1158 host->reqs_blocked = 0;
1159 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1160 if (host->protect_card) {
1161 pr_info("%s: cover is closed, "
1162 "card is now accessible\n",
1163 mmc_hostname(host->mmc));
1164 host->protect_card = 0;
1167 if (!host->protect_card) {
1168 pr_info("%s: cover is open, "
1169 "card is now inaccessible\n",
1170 mmc_hostname(host->mmc));
1171 host->protect_card = 1;
1177 * irq handler to notify the core about card insertion/removal
1179 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1181 struct omap_hsmmc_host *host = dev_id;
1182 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1185 if (host->suspended)
1188 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1190 if (slot->card_detect)
1191 carddetect = slot->card_detect(host->dev, host->slot_id);
1193 omap_hsmmc_protect_card(host);
1194 carddetect = -ENOSYS;
1198 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1200 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1204 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1205 struct mmc_data *data)
1209 if (data->flags & MMC_DATA_WRITE)
1210 sync_dev = host->dma_line_tx;
1212 sync_dev = host->dma_line_rx;
1216 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1217 struct mmc_data *data,
1218 struct scatterlist *sgl)
1220 int blksz, nblk, dma_ch;
1222 dma_ch = host->dma_ch;
1223 if (data->flags & MMC_DATA_WRITE) {
1224 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1225 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1226 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1227 sg_dma_address(sgl), 0, 0);
1229 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1230 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1231 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1232 sg_dma_address(sgl), 0, 0);
1235 blksz = host->data->blksz;
1236 nblk = sg_dma_len(sgl) / blksz;
1238 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1239 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1240 omap_hsmmc_get_dma_sync_dev(host, data),
1241 !(data->flags & MMC_DATA_WRITE));
1243 omap_start_dma(dma_ch);
1247 * DMA call back function
1249 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1251 struct omap_hsmmc_host *host = cb_data;
1252 struct mmc_data *data;
1253 int dma_ch, req_in_progress;
1255 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1256 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1261 spin_lock(&host->irq_lock);
1262 if (host->dma_ch < 0) {
1263 spin_unlock(&host->irq_lock);
1267 data = host->mrq->data;
1269 if (host->dma_sg_idx < host->dma_len) {
1270 /* Fire up the next transfer. */
1271 omap_hsmmc_config_dma_params(host, data,
1272 data->sg + host->dma_sg_idx);
1273 spin_unlock(&host->irq_lock);
1277 if (!data->host_cookie)
1278 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1279 omap_hsmmc_get_dma_dir(host, data));
1281 req_in_progress = host->req_in_progress;
1282 dma_ch = host->dma_ch;
1284 spin_unlock(&host->irq_lock);
1286 omap_free_dma(dma_ch);
1288 /* If DMA has finished after TC, complete the request */
1289 if (!req_in_progress) {
1290 struct mmc_request *mrq = host->mrq;
1293 mmc_request_done(host->mmc, mrq);
1297 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1298 struct mmc_data *data,
1299 struct omap_hsmmc_next *next)
1303 if (!next && data->host_cookie &&
1304 data->host_cookie != host->next_data.cookie) {
1305 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1306 " host->next_data.cookie %d\n",
1307 __func__, data->host_cookie, host->next_data.cookie);
1308 data->host_cookie = 0;
1311 /* Check if next job is already prepared */
1313 (!next && data->host_cookie != host->next_data.cookie)) {
1314 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1316 omap_hsmmc_get_dma_dir(host, data));
1319 dma_len = host->next_data.dma_len;
1320 host->next_data.dma_len = 0;
1328 next->dma_len = dma_len;
1329 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1331 host->dma_len = dma_len;
1337 * Routine to configure and start DMA for the MMC card
1339 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1340 struct mmc_request *req)
1342 int dma_ch = 0, ret = 0, i;
1343 struct mmc_data *data = req->data;
1345 /* Sanity check: all the SG entries must be aligned by block size. */
1346 for (i = 0; i < data->sg_len; i++) {
1347 struct scatterlist *sgl;
1350 if (sgl->length % data->blksz)
1353 if ((data->blksz % 4) != 0)
1354 /* REVISIT: The MMC buffer increments only when MSB is written.
1355 * Return error for blksz which is non multiple of four.
1359 BUG_ON(host->dma_ch != -1);
1361 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1362 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1364 dev_err(mmc_dev(host->mmc),
1365 "%s: omap_request_dma() failed with %d\n",
1366 mmc_hostname(host->mmc), ret);
1369 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1373 host->dma_ch = dma_ch;
1374 host->dma_sg_idx = 0;
1376 omap_hsmmc_config_dma_params(host, data, data->sg);
1381 static void set_data_timeout(struct omap_hsmmc_host *host,
1382 unsigned int timeout_ns,
1383 unsigned int timeout_clks)
1385 unsigned int timeout, cycle_ns;
1386 uint32_t reg, clkd, dto = 0;
1388 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1389 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1393 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1394 timeout = timeout_ns / cycle_ns;
1395 timeout += timeout_clks;
1397 while ((timeout & 0x80000000) == 0) {
1414 reg |= dto << DTO_SHIFT;
1415 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1419 * Configure block length for MMC/SD cards and initiate the transfer.
1422 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1425 host->data = req->data;
1427 if (req->data == NULL) {
1428 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1430 * Set an arbitrary 100ms data timeout for commands with
1433 if (req->cmd->flags & MMC_RSP_BUSY)
1434 set_data_timeout(host, 100000000U, 0);
1438 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1439 | (req->data->blocks << 16));
1440 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1442 if (host->use_dma) {
1443 ret = omap_hsmmc_start_dma_transfer(host, req);
1445 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1452 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1455 struct omap_hsmmc_host *host = mmc_priv(mmc);
1456 struct mmc_data *data = mrq->data;
1458 if (host->use_dma) {
1459 if (data->host_cookie)
1460 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1462 omap_hsmmc_get_dma_dir(host, data));
1463 data->host_cookie = 0;
1467 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1470 struct omap_hsmmc_host *host = mmc_priv(mmc);
1472 if (mrq->data->host_cookie) {
1473 mrq->data->host_cookie = 0;
1478 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1480 mrq->data->host_cookie = 0;
1484 * Request function. for read/write operation
1486 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1488 struct omap_hsmmc_host *host = mmc_priv(mmc);
1491 BUG_ON(host->req_in_progress);
1492 BUG_ON(host->dma_ch != -1);
1493 if (host->protect_card) {
1494 if (host->reqs_blocked < 3) {
1496 * Ensure the controller is left in a consistent
1497 * state by resetting the command and data state
1500 omap_hsmmc_reset_controller_fsm(host, SRD);
1501 omap_hsmmc_reset_controller_fsm(host, SRC);
1502 host->reqs_blocked += 1;
1504 req->cmd->error = -EBADF;
1506 req->data->error = -EBADF;
1507 req->cmd->retries = 0;
1508 mmc_request_done(mmc, req);
1510 } else if (host->reqs_blocked)
1511 host->reqs_blocked = 0;
1512 WARN_ON(host->mrq != NULL);
1514 err = omap_hsmmc_prepare_data(host, req);
1516 req->cmd->error = err;
1518 req->data->error = err;
1520 mmc_request_done(mmc, req);
1524 omap_hsmmc_start_command(host, req->cmd, req->data);
1527 /* Routine to configure clock values. Exposed API to core */
1528 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1530 struct omap_hsmmc_host *host = mmc_priv(mmc);
1531 int do_send_init_stream = 0;
1533 pm_runtime_get_sync(host->dev);
1535 if (ios->power_mode != host->power_mode) {
1536 switch (ios->power_mode) {
1538 mmc_slot(host).set_power(host->dev, host->slot_id,
1543 mmc_slot(host).set_power(host->dev, host->slot_id,
1545 host->vdd = ios->vdd;
1548 do_send_init_stream = 1;
1551 host->power_mode = ios->power_mode;
1554 /* FIXME: set registers based only on changes to ios */
1556 omap_hsmmc_set_bus_width(host);
1558 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1559 /* Only MMC1 can interface at 3V without some flavor
1560 * of external transceiver; but they all handle 1.8V.
1562 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1563 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1565 * The mmc_select_voltage fn of the core does
1566 * not seem to set the power_mode to
1567 * MMC_POWER_UP upon recalculating the voltage.
1570 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1571 dev_dbg(mmc_dev(host->mmc),
1572 "Switch operation failed\n");
1576 omap_hsmmc_set_clock(host);
1578 if (do_send_init_stream)
1579 send_init_stream(host);
1581 omap_hsmmc_set_bus_mode(host);
1583 pm_runtime_put_autosuspend(host->dev);
1586 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1588 struct omap_hsmmc_host *host = mmc_priv(mmc);
1590 if (!mmc_slot(host).card_detect)
1592 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1595 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1597 struct omap_hsmmc_host *host = mmc_priv(mmc);
1599 if (!mmc_slot(host).get_ro)
1601 return mmc_slot(host).get_ro(host->dev, 0);
1604 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1606 struct omap_hsmmc_host *host = mmc_priv(mmc);
1608 if (mmc_slot(host).init_card)
1609 mmc_slot(host).init_card(card);
1612 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1614 u32 hctl, capa, value;
1616 /* Only MMC1 supports 3.0V */
1617 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1625 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1626 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1628 value = OMAP_HSMMC_READ(host->base, CAPA);
1629 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1631 /* Set the controller to AUTO IDLE mode */
1632 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1633 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1635 /* Set SD bus power bit */
1636 set_sd_bus_power(host);
1639 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1641 struct omap_hsmmc_host *host = mmc_priv(mmc);
1643 pm_runtime_get_sync(host->dev);
1648 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1650 struct omap_hsmmc_host *host = mmc_priv(mmc);
1652 pm_runtime_mark_last_busy(host->dev);
1653 pm_runtime_put_autosuspend(host->dev);
1658 static const struct mmc_host_ops omap_hsmmc_ops = {
1659 .enable = omap_hsmmc_enable_fclk,
1660 .disable = omap_hsmmc_disable_fclk,
1661 .post_req = omap_hsmmc_post_req,
1662 .pre_req = omap_hsmmc_pre_req,
1663 .request = omap_hsmmc_request,
1664 .set_ios = omap_hsmmc_set_ios,
1665 .get_cd = omap_hsmmc_get_cd,
1666 .get_ro = omap_hsmmc_get_ro,
1667 .init_card = omap_hsmmc_init_card,
1668 /* NYET -- enable_sdio_irq */
1671 #ifdef CONFIG_DEBUG_FS
1673 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1675 struct mmc_host *mmc = s->private;
1676 struct omap_hsmmc_host *host = mmc_priv(mmc);
1677 int context_loss = 0;
1679 if (host->pdata->get_context_loss_count)
1680 context_loss = host->pdata->get_context_loss_count(host->dev);
1682 seq_printf(s, "mmc%d:\n"
1685 " nesting_cnt:\t%d\n"
1686 " ctx_loss:\t%d:%d\n"
1688 mmc->index, mmc->enabled ? 1 : 0,
1689 host->dpm_state, mmc->nesting_cnt,
1690 host->context_loss, context_loss);
1692 if (host->suspended) {
1693 seq_printf(s, "host suspended, can't read registers\n");
1697 pm_runtime_get_sync(host->dev);
1699 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1700 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1701 seq_printf(s, "CON:\t\t0x%08x\n",
1702 OMAP_HSMMC_READ(host->base, CON));
1703 seq_printf(s, "HCTL:\t\t0x%08x\n",
1704 OMAP_HSMMC_READ(host->base, HCTL));
1705 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1706 OMAP_HSMMC_READ(host->base, SYSCTL));
1707 seq_printf(s, "IE:\t\t0x%08x\n",
1708 OMAP_HSMMC_READ(host->base, IE));
1709 seq_printf(s, "ISE:\t\t0x%08x\n",
1710 OMAP_HSMMC_READ(host->base, ISE));
1711 seq_printf(s, "CAPA:\t\t0x%08x\n",
1712 OMAP_HSMMC_READ(host->base, CAPA));
1714 pm_runtime_mark_last_busy(host->dev);
1715 pm_runtime_put_autosuspend(host->dev);
1720 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1722 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1725 static const struct file_operations mmc_regs_fops = {
1726 .open = omap_hsmmc_regs_open,
1728 .llseek = seq_lseek,
1729 .release = single_release,
1732 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1734 if (mmc->debugfs_root)
1735 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1736 mmc, &mmc_regs_fops);
1741 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1747 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1749 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1750 struct mmc_host *mmc;
1751 struct omap_hsmmc_host *host = NULL;
1752 struct resource *res;
1755 if (pdata == NULL) {
1756 dev_err(&pdev->dev, "Platform Data is missing\n");
1760 if (pdata->nr_slots == 0) {
1761 dev_err(&pdev->dev, "No Slots\n");
1765 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1766 irq = platform_get_irq(pdev, 0);
1767 if (res == NULL || irq < 0)
1770 res->start += pdata->reg_offset;
1771 res->end += pdata->reg_offset;
1772 res = request_mem_region(res->start, resource_size(res), pdev->name);
1776 ret = omap_hsmmc_gpio_init(pdata);
1780 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1786 host = mmc_priv(mmc);
1788 host->pdata = pdata;
1789 host->dev = &pdev->dev;
1791 host->dev->dma_mask = &pdata->dma_mask;
1794 host->id = pdev->id;
1796 host->mapbase = res->start;
1797 host->base = ioremap(host->mapbase, SZ_4K);
1798 host->power_mode = MMC_POWER_OFF;
1799 host->next_data.cookie = 1;
1801 platform_set_drvdata(pdev, host);
1803 mmc->ops = &omap_hsmmc_ops;
1806 * If regulator_disable can only put vcc_aux to sleep then there is
1809 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1810 mmc_slot(host).no_off = 1;
1812 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1814 if (pdata->max_freq > 0)
1815 mmc->f_max = pdata->max_freq;
1817 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1819 spin_lock_init(&host->irq_lock);
1821 host->fclk = clk_get(&pdev->dev, "fck");
1822 if (IS_ERR(host->fclk)) {
1823 ret = PTR_ERR(host->fclk);
1828 omap_hsmmc_context_save(host);
1830 mmc->caps |= MMC_CAP_DISABLE;
1831 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1832 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1833 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1836 pm_runtime_enable(host->dev);
1837 pm_runtime_get_sync(host->dev);
1838 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1839 pm_runtime_use_autosuspend(host->dev);
1841 if (cpu_is_omap2430()) {
1842 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1844 * MMC can still work without debounce clock.
1846 if (IS_ERR(host->dbclk))
1847 dev_warn(mmc_dev(host->mmc),
1848 "Failed to get debounce clock\n");
1850 host->got_dbclk = 1;
1852 if (host->got_dbclk)
1853 if (clk_enable(host->dbclk) != 0)
1854 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1858 /* Since we do only SG emulation, we can have as many segs
1860 mmc->max_segs = 1024;
1862 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1863 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1864 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1865 mmc->max_seg_size = mmc->max_req_size;
1867 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1868 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1870 mmc->caps |= mmc_slot(host).caps;
1871 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1872 mmc->caps |= MMC_CAP_4_BIT_DATA;
1874 if (mmc_slot(host).nonremovable)
1875 mmc->caps |= MMC_CAP_NONREMOVABLE;
1877 mmc->pm_caps = mmc_slot(host).pm_caps;
1879 omap_hsmmc_conf_bus_power(host);
1881 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1883 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1886 host->dma_line_tx = res->start;
1888 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1890 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1893 host->dma_line_rx = res->start;
1895 /* Request IRQ for MMC operations */
1896 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1897 mmc_hostname(mmc), host);
1899 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1903 if (pdata->init != NULL) {
1904 if (pdata->init(&pdev->dev) != 0) {
1905 dev_dbg(mmc_dev(host->mmc),
1906 "Unable to configure MMC IRQs\n");
1907 goto err_irq_cd_init;
1911 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1912 ret = omap_hsmmc_reg_get(host);
1918 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1920 /* Request IRQ for card detect */
1921 if ((mmc_slot(host).card_detect_irq)) {
1922 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1925 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1926 mmc_hostname(mmc), host);
1928 dev_dbg(mmc_dev(host->mmc),
1929 "Unable to grab MMC CD IRQ\n");
1932 pdata->suspend = omap_hsmmc_suspend_cdirq;
1933 pdata->resume = omap_hsmmc_resume_cdirq;
1936 omap_hsmmc_disable_irq(host);
1938 omap_hsmmc_protect_card(host);
1942 if (mmc_slot(host).name != NULL) {
1943 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1947 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1948 ret = device_create_file(&mmc->class_dev,
1949 &dev_attr_cover_switch);
1954 omap_hsmmc_debugfs(mmc);
1955 pm_runtime_mark_last_busy(host->dev);
1956 pm_runtime_put_autosuspend(host->dev);
1961 mmc_remove_host(mmc);
1962 free_irq(mmc_slot(host).card_detect_irq, host);
1965 omap_hsmmc_reg_put(host);
1967 if (host->pdata->cleanup)
1968 host->pdata->cleanup(&pdev->dev);
1970 free_irq(host->irq, host);
1972 pm_runtime_mark_last_busy(host->dev);
1973 pm_runtime_put_autosuspend(host->dev);
1974 clk_put(host->fclk);
1975 if (host->got_dbclk) {
1976 clk_disable(host->dbclk);
1977 clk_put(host->dbclk);
1980 iounmap(host->base);
1981 platform_set_drvdata(pdev, NULL);
1984 omap_hsmmc_gpio_free(pdata);
1986 release_mem_region(res->start, resource_size(res));
1990 static int omap_hsmmc_remove(struct platform_device *pdev)
1992 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1993 struct resource *res;
1996 pm_runtime_get_sync(host->dev);
1997 mmc_remove_host(host->mmc);
1999 omap_hsmmc_reg_put(host);
2000 if (host->pdata->cleanup)
2001 host->pdata->cleanup(&pdev->dev);
2002 free_irq(host->irq, host);
2003 if (mmc_slot(host).card_detect_irq)
2004 free_irq(mmc_slot(host).card_detect_irq, host);
2006 pm_runtime_put_sync(host->dev);
2007 pm_runtime_disable(host->dev);
2008 clk_put(host->fclk);
2009 if (host->got_dbclk) {
2010 clk_disable(host->dbclk);
2011 clk_put(host->dbclk);
2014 mmc_free_host(host->mmc);
2015 iounmap(host->base);
2016 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2019 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 release_mem_region(res->start, resource_size(res));
2022 platform_set_drvdata(pdev, NULL);
2028 static int omap_hsmmc_suspend(struct device *dev)
2031 struct platform_device *pdev = to_platform_device(dev);
2032 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2034 if (host && host->suspended)
2038 pm_runtime_get_sync(host->dev);
2039 host->suspended = 1;
2040 if (host->pdata->suspend) {
2041 ret = host->pdata->suspend(&pdev->dev,
2044 dev_dbg(mmc_dev(host->mmc),
2045 "Unable to handle MMC board"
2046 " level suspend\n");
2047 host->suspended = 0;
2051 ret = mmc_suspend_host(host->mmc);
2054 host->suspended = 0;
2055 if (host->pdata->resume) {
2056 ret = host->pdata->resume(&pdev->dev,
2059 dev_dbg(mmc_dev(host->mmc),
2060 "Unmask interrupt failed\n");
2065 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2066 omap_hsmmc_disable_irq(host);
2067 OMAP_HSMMC_WRITE(host->base, HCTL,
2068 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2070 if (host->got_dbclk)
2071 clk_disable(host->dbclk);
2075 pm_runtime_put_sync(host->dev);
2079 /* Routine to resume the MMC device */
2080 static int omap_hsmmc_resume(struct device *dev)
2083 struct platform_device *pdev = to_platform_device(dev);
2084 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2086 if (host && !host->suspended)
2090 pm_runtime_get_sync(host->dev);
2092 if (host->got_dbclk)
2093 clk_enable(host->dbclk);
2095 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2096 omap_hsmmc_conf_bus_power(host);
2098 if (host->pdata->resume) {
2099 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2101 dev_dbg(mmc_dev(host->mmc),
2102 "Unmask interrupt failed\n");
2105 omap_hsmmc_protect_card(host);
2107 /* Notify the core to resume the host */
2108 ret = mmc_resume_host(host->mmc);
2110 host->suspended = 0;
2112 pm_runtime_mark_last_busy(host->dev);
2113 pm_runtime_put_autosuspend(host->dev);
2121 #define omap_hsmmc_suspend NULL
2122 #define omap_hsmmc_resume NULL
2125 static int omap_hsmmc_runtime_suspend(struct device *dev)
2127 struct omap_hsmmc_host *host;
2129 host = platform_get_drvdata(to_platform_device(dev));
2130 omap_hsmmc_context_save(host);
2131 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2136 static int omap_hsmmc_runtime_resume(struct device *dev)
2138 struct omap_hsmmc_host *host;
2140 host = platform_get_drvdata(to_platform_device(dev));
2141 omap_hsmmc_context_restore(host);
2142 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2147 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2148 .suspend = omap_hsmmc_suspend,
2149 .resume = omap_hsmmc_resume,
2150 .runtime_suspend = omap_hsmmc_runtime_suspend,
2151 .runtime_resume = omap_hsmmc_runtime_resume,
2154 static struct platform_driver omap_hsmmc_driver = {
2155 .remove = omap_hsmmc_remove,
2157 .name = DRIVER_NAME,
2158 .owner = THIS_MODULE,
2159 .pm = &omap_hsmmc_dev_pm_ops,
2163 static int __init omap_hsmmc_init(void)
2165 /* Register the MMC driver */
2166 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2169 static void __exit omap_hsmmc_cleanup(void)
2171 /* Unregister MMC driver */
2172 platform_driver_unregister(&omap_hsmmc_driver);
2175 module_init(omap_hsmmc_init);
2176 module_exit(omap_hsmmc_cleanup);
2178 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2179 MODULE_LICENSE("GPL");
2180 MODULE_ALIAS("platform:" DRIVER_NAME);
2181 MODULE_AUTHOR("Texas Instruments Inc");