drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MIN_CLOCK      400000
 123 #define OMAP_MMC_MAX_CLOCK      52000000
 124 #define DRIVER_NAME             "omap_hsmmc"
 125
 126 /*
 127  * One controller can have multiple slots, like on some omap boards using
 128  * omap.c controller driver. Luckily this is not currently done on any known
 129  * omap_hsmmc.c device.
 130  */
 131 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 132
 133 /*
 134  * MMC Host controller read/write API's
 135  */
 136 #define OMAP_HSMMC_READ(base, reg)      \
 137         __raw_readl((base) + OMAP_HSMMC_##reg)
 138
 139 #define OMAP_HSMMC_WRITE(base, reg, val) \
 140         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 141
 142 struct omap_hsmmc_next {
 143         unsigned int    dma_len;
 144         s32             cookie;
 145 };
 146
 147 struct omap_hsmmc_host {
 148         struct  device          *dev;
 149         struct  mmc_host        *mmc;
 150         struct  mmc_request     *mrq;
 151         struct  mmc_command     *cmd;
 152         struct  mmc_data        *data;
 153         struct  clk             *fclk;
 154         struct  clk             *dbclk;
 155         /*
 156          * vcc == configured supply
 157          * vcc_aux == optional
 158          *   -  MMC1, supply for DAT4..DAT7
 159          *   -  MMC2/MMC2, external level shifter voltage supply, for
 160          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 161          */
 162         struct  regulator       *vcc;
 163         struct  regulator       *vcc_aux;
 164         void    __iomem         *base;
 165         resource_size_t         mapbase;
 166         spinlock_t              irq_lock; /* Prevent races with irq handler */
 167         unsigned int            id;
 168         unsigned int            dma_len;
 169         unsigned int            dma_sg_idx;
 170         unsigned char           bus_mode;
 171         unsigned char           power_mode;
 172         u32                     *buffer;
 173         u32                     bytesleft;
 174         int                     suspended;
 175         int                     irq;
 176         int                     use_dma, dma_ch;
 177         int                     dma_line_tx, dma_line_rx;
 178         int                     slot_id;
 179         int                     got_dbclk;
 180         int                     response_busy;
 181         int                     context_loss;
 182         int                     dpm_state;
 183         int                     vdd;
 184         int                     protect_card;
 185         int                     reqs_blocked;
 186         int                     use_reg;
 187         int                     req_in_progress;
 188         struct omap_hsmmc_next  next_data;
 189
 190         struct  omap_mmc_platform_data  *pdata;
 191 };
 192
 193 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 194 {
 195         struct omap_mmc_platform_data *mmc = dev->platform_data;
 196
 197         /* NOTE: assumes card detect signal is active-low */
 198         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 199 }
 200
 201 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 202 {
 203         struct omap_mmc_platform_data *mmc = dev->platform_data;
 204
 205         /* NOTE: assumes write protect signal is active-high */
 206         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 207 }
 208
 209 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 210 {
 211         struct omap_mmc_platform_data *mmc = dev->platform_data;
 212
 213         /* NOTE: assumes card detect signal is active-low */
 214         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 215 }
 216
 217 #ifdef CONFIG_PM
 218
 219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 220 {
 221         struct omap_mmc_platform_data *mmc = dev->platform_data;
 222
 223         disable_irq(mmc->slots[0].card_detect_irq);
 224         return 0;
 225 }
 226
 227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 228 {
 229         struct omap_mmc_platform_data *mmc = dev->platform_data;
 230
 231         enable_irq(mmc->slots[0].card_detect_irq);
 232         return 0;
 233 }
 234
 235 #else
 236
 237 #define omap_hsmmc_suspend_cdirq        NULL
 238 #define omap_hsmmc_resume_cdirq         NULL
 239
 240 #endif
 241
 242 #ifdef CONFIG_REGULATOR
 243
 244 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 245                                    int vdd)
 246 {
 247         struct omap_hsmmc_host *host =
 248                 platform_get_drvdata(to_platform_device(dev));
 249         int ret = 0;
 250
 251         /*
 252          * If we don't see a Vcc regulator, assume it's a fixed
 253          * voltage always-on regulator.
 254          */
 255         if (!host->vcc)
 256                 return 0;
 257
 258         if (mmc_slot(host).before_set_reg)
 259                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 260
 261         /*
 262          * Assume Vcc regulator is used only to power the card ... OMAP
 263          * VDDS is used to power the pins, optionally with a transceiver to
 264          * support cards using voltages other than VDDS (1.8V nominal).  When a
 265          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 266          *
 267          * In some cases this regulator won't support enable/disable;
 268          * e.g. it's a fixed rail for a WLAN chip.
 269          *
 270          * In other cases vcc_aux switches interface power.  Example, for
 271          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 272          * chips/cards need an interface voltage rail too.
 273          */
 274         if (power_on) {
 275                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 276                 /* Enable interface voltage rail, if needed */
 277                 if (ret == 0 && host->vcc_aux) {
 278                         ret = regulator_enable(host->vcc_aux);
 279                         if (ret < 0)
 280                                 ret = mmc_regulator_set_ocr(host->mmc,
 281                                                         host->vcc, 0);
 282                 }
 283         } else {
 284                 /* Shut down the rail */
 285                 if (host->vcc_aux)
 286                         ret = regulator_disable(host->vcc_aux);
 287                 if (!ret) {
 288                         /* Then proceed to shut down the local regulator */
 289                         ret = mmc_regulator_set_ocr(host->mmc,
 290                                                 host->vcc, 0);
 291                 }
 292         }
 293
 294         if (mmc_slot(host).after_set_reg)
 295                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 296
 297         return ret;
 298 }
 299
 300 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 301 {
 302         struct regulator *reg;
 303         int ret = 0;
 304         int ocr_value = 0;
 305
 306         mmc_slot(host).set_power = omap_hsmmc_set_power;
 307
 308         reg = regulator_get(host->dev, "vmmc");
 309         if (IS_ERR(reg)) {
 310                 dev_dbg(host->dev, "vmmc regulator missing\n");
 311                 /*
 312                 * HACK: until fixed.c regulator is usable,
 313                 * we don't require a main regulator
 314                 * for MMC2 or MMC3
 315                 */
 316                 if (host->id == OMAP_MMC1_DEVID) {
 317                         ret = PTR_ERR(reg);
 318                         goto err;
 319                 }
 320         } else {
 321                 host->vcc = reg;
 322                 ocr_value = mmc_regulator_get_ocrmask(reg);
 323                 if (!mmc_slot(host).ocr_mask) {
 324                         mmc_slot(host).ocr_mask = ocr_value;
 325                 } else {
 326                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 327                                 pr_err("MMC%d ocrmask %x is not supported\n",
 328                                         host->id, mmc_slot(host).ocr_mask);
 329                                 mmc_slot(host).ocr_mask = 0;
 330                                 return -EINVAL;
 331                         }
 332                 }
 333
 334                 /* Allow an aux regulator */
 335                 reg = regulator_get(host->dev, "vmmc_aux");
 336                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 337
 338                 /* For eMMC do not power off when not in sleep state */
 339                 if (mmc_slot(host).no_regulator_off_init)
 340                         return 0;
 341                 /*
 342                 * UGLY HACK:  workaround regulator framework bugs.
 343                 * When the bootloader leaves a supply active, it's
 344                 * initialized with zero usecount ... and we can't
 345                 * disable it without first enabling it.  Until the
 346                 * framework is fixed, we need a workaround like this
 347                 * (which is safe for MMC, but not in general).
 348                 */
 349                 if (regulator_is_enabled(host->vcc) > 0 ||
 350                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 351                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 352
 353                         mmc_slot(host).set_power(host->dev, host->slot_id,
 354                                                  1, vdd);
 355                         mmc_slot(host).set_power(host->dev, host->slot_id,
 356                                                  0, 0);
 357                 }
 358         }
 359
 360         return 0;
 361
 362 err:
 363         mmc_slot(host).set_power = NULL;
 364         return ret;
 365 }
 366
 367 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 368 {
 369         regulator_put(host->vcc);
 370         regulator_put(host->vcc_aux);
 371         mmc_slot(host).set_power = NULL;
 372 }
 373
 374 static inline int omap_hsmmc_have_reg(void)
 375 {
 376         return 1;
 377 }
 378
 379 #else
 380
 381 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 382 {
 383         return -EINVAL;
 384 }
 385
 386 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 387 {
 388 }
 389
 390 static inline int omap_hsmmc_have_reg(void)
 391 {
 392         return 0;
 393 }
 394
 395 #endif
 396
 397 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 398 {
 399         int ret;
 400
 401         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 402                 if (pdata->slots[0].cover)
 403                         pdata->slots[0].get_cover_state =
 404                                         omap_hsmmc_get_cover_state;
 405                 else
 406                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 407                 pdata->slots[0].card_detect_irq =
 408                                 gpio_to_irq(pdata->slots[0].switch_pin);
 409                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 410                 if (ret)
 411                         return ret;
 412                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 413                 if (ret)
 414                         goto err_free_sp;
 415         } else
 416                 pdata->slots[0].switch_pin = -EINVAL;
 417
 418         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 419                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 420                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 421                 if (ret)
 422                         goto err_free_cd;
 423                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 424                 if (ret)
 425                         goto err_free_wp;
 426         } else
 427                 pdata->slots[0].gpio_wp = -EINVAL;
 428
 429         return 0;
 430
 431 err_free_wp:
 432         gpio_free(pdata->slots[0].gpio_wp);
 433 err_free_cd:
 434         if (gpio_is_valid(pdata->slots[0].switch_pin))
 435 err_free_sp:
 436                 gpio_free(pdata->slots[0].switch_pin);
 437         return ret;
 438 }
 439
 440 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 441 {
 442         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 443                 gpio_free(pdata->slots[0].gpio_wp);
 444         if (gpio_is_valid(pdata->slots[0].switch_pin))
 445                 gpio_free(pdata->slots[0].switch_pin);
 446 }
 447
 448 /*
 449  * Start clock to the card
 450  */
 451 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 452 {
 453         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 454                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 455 }
 456
 457 /*
 458  * Stop clock to the card
 459  */
 460 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 461 {
 462         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 463                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 464         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 465                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 466 }
 467
 468 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 469                                   struct mmc_command *cmd)
 470 {
 471         unsigned int irq_mask;
 472
 473         if (host->use_dma)
 474                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 475         else
 476                 irq_mask = INT_EN_MASK;
 477
 478         /* Disable timeout for erases */
 479         if (cmd->opcode == MMC_ERASE)
 480                 irq_mask &= ~DTO_ENABLE;
 481
 482         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 483         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 484         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 485 }
 486
 487 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 488 {
 489         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 490         OMAP_HSMMC_WRITE(host->base, IE, 0);
 491         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 492 }
 493
 494 /* Calculate divisor for the given clock frequency */
 495 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 496 {
 497         u16 dsor = 0;
 498
 499         if (ios->clock) {
 500                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 501                 if (dsor > 250)
 502                         dsor = 250;
 503         }
 504
 505         return dsor;
 506 }
 507
 508 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 509 {
 510         struct mmc_ios *ios = &host->mmc->ios;
 511         unsigned long regval;
 512         unsigned long timeout;
 513
 514         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 515
 516         omap_hsmmc_stop_clock(host);
 517
 518         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 519         regval = regval & ~(CLKD_MASK | DTO_MASK);
 520         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 521         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 522         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 523                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 524
 525         /* Wait till the ICS bit is set */
 526         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 527         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 528                 && time_before(jiffies, timeout))
 529                 cpu_relax();
 530
 531         omap_hsmmc_start_clock(host);
 532 }
 533
 534 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 535 {
 536         struct mmc_ios *ios = &host->mmc->ios;
 537         u32 con;
 538
 539         con = OMAP_HSMMC_READ(host->base, CON);
 540         switch (ios->bus_width) {
 541         case MMC_BUS_WIDTH_8:
 542                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 543                 break;
 544         case MMC_BUS_WIDTH_4:
 545                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 546                 OMAP_HSMMC_WRITE(host->base, HCTL,
 547                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 548                 break;
 549         case MMC_BUS_WIDTH_1:
 550                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 551                 OMAP_HSMMC_WRITE(host->base, HCTL,
 552                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 553                 break;
 554         }
 555 }
 556
 557 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 558 {
 559         struct mmc_ios *ios = &host->mmc->ios;
 560         u32 con;
 561
 562         con = OMAP_HSMMC_READ(host->base, CON);
 563         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 564                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 565         else
 566                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 567 }
 568
 569 #ifdef CONFIG_PM
 570
 571 /*
 572  * Restore the MMC host context, if it was lost as result of a
 573  * power state change.
 574  */
 575 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 576 {
 577         struct mmc_ios *ios = &host->mmc->ios;
 578         struct omap_mmc_platform_data *pdata = host->pdata;
 579         int context_loss = 0;
 580         u32 hctl, capa;
 581         unsigned long timeout;
 582
 583         if (pdata->get_context_loss_count) {
 584                 context_loss = pdata->get_context_loss_count(host->dev);
 585                 if (context_loss < 0)
 586                         return 1;
 587         }
 588
 589         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 590                 context_loss == host->context_loss ? "not " : "");
 591         if (host->context_loss == context_loss)
 592                 return 1;
 593
 594         /* Wait for hardware reset */
 595         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 596         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 597                 && time_before(jiffies, timeout))
 598                 ;
 599
 600         /* Do software reset */
 601         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 602         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 603         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 604                 && time_before(jiffies, timeout))
 605                 ;
 606
 607         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 608                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 609
 610         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 611                 if (host->power_mode != MMC_POWER_OFF &&
 612                     (1 << ios->vdd) <= MMC_VDD_23_24)
 613                         hctl = SDVS18;
 614                 else
 615                         hctl = SDVS30;
 616                 capa = VS30 | VS18;
 617         } else {
 618                 hctl = SDVS18;
 619                 capa = VS18;
 620         }
 621
 622         OMAP_HSMMC_WRITE(host->base, HCTL,
 623                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 624
 625         OMAP_HSMMC_WRITE(host->base, CAPA,
 626                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 627
 628         OMAP_HSMMC_WRITE(host->base, HCTL,
 629                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 630
 631         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 632         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 633                 && time_before(jiffies, timeout))
 634                 ;
 635
 636         omap_hsmmc_disable_irq(host);
 637
 638         /* Do not initialize card-specific things if the power is off */
 639         if (host->power_mode == MMC_POWER_OFF)
 640                 goto out;
 641
 642         omap_hsmmc_set_bus_width(host);
 643
 644         omap_hsmmc_set_clock(host);
 645
 646         omap_hsmmc_set_bus_mode(host);
 647
 648 out:
 649         host->context_loss = context_loss;
 650
 651         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 652         return 0;
 653 }
 654
 655 /*
 656  * Save the MMC host context (store the number of power state changes so far).
 657  */
 658 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 659 {
 660         struct omap_mmc_platform_data *pdata = host->pdata;
 661         int context_loss;
 662
 663         if (pdata->get_context_loss_count) {
 664                 context_loss = pdata->get_context_loss_count(host->dev);
 665                 if (context_loss < 0)
 666                         return;
 667                 host->context_loss = context_loss;
 668         }
 669 }
 670
 671 #else
 672
 673 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 674 {
 675         return 0;
 676 }
 677
 678 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 679 {
 680 }
 681
 682 #endif
 683
 684 /*
 685  * Send init stream sequence to card
 686  * before sending IDLE command
 687  */
 688 static void send_init_stream(struct omap_hsmmc_host *host)
 689 {
 690         int reg = 0;
 691         unsigned long timeout;
 692
 693         if (host->protect_card)
 694                 return;
 695
 696         disable_irq(host->irq);
 697
 698         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 699         OMAP_HSMMC_WRITE(host->base, CON,
 700                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 701         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 702
 703         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 704         while ((reg != CC) && time_before(jiffies, timeout))
 705                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 706
 707         OMAP_HSMMC_WRITE(host->base, CON,
 708                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 709
 710         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 711         OMAP_HSMMC_READ(host->base, STAT);
 712
 713         enable_irq(host->irq);
 714 }
 715
 716 static inline
 717 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 718 {
 719         int r = 1;
 720
 721         if (mmc_slot(host).get_cover_state)
 722                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 723         return r;
 724 }
 725
 726 static ssize_t
 727 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 728                            char *buf)
 729 {
 730         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 731         struct omap_hsmmc_host *host = mmc_priv(mmc);
 732
 733         return sprintf(buf, "%s\n",
 734                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 735 }
 736
 737 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 738
 739 static ssize_t
 740 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 741                         char *buf)
 742 {
 743         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 744         struct omap_hsmmc_host *host = mmc_priv(mmc);
 745
 746         return sprintf(buf, "%s\n", mmc_slot(host).name);
 747 }
 748
 749 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 750
 751 /*
 752  * Configure the response type and send the cmd.
 753  */
 754 static void
 755 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 756         struct mmc_data *data)
 757 {
 758         int cmdreg = 0, resptype = 0, cmdtype = 0;
 759
 760         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 761                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 762         host->cmd = cmd;
 763
 764         omap_hsmmc_enable_irq(host, cmd);
 765
 766         host->response_busy = 0;
 767         if (cmd->flags & MMC_RSP_PRESENT) {
 768                 if (cmd->flags & MMC_RSP_136)
 769                         resptype = 1;
 770                 else if (cmd->flags & MMC_RSP_BUSY) {
 771                         resptype = 3;
 772                         host->response_busy = 1;
 773                 } else
 774                         resptype = 2;
 775         }
 776
 777         /*
 778          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 779          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 780          * a val of 0x3, rest 0x0.
 781          */
 782         if (cmd == host->mrq->stop)
 783                 cmdtype = 0x3;
 784
 785         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 786
 787         if (data) {
 788                 cmdreg |= DP_SELECT | MSBS | BCE;
 789                 if (data->flags & MMC_DATA_READ)
 790                         cmdreg |= DDIR;
 791                 else
 792                         cmdreg &= ~(DDIR);
 793         }
 794
 795         if (host->use_dma)
 796                 cmdreg |= DMA_EN;
 797
 798         host->req_in_progress = 1;
 799
 800         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 801         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 802 }
 803
 804 static int
 805 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 806 {
 807         if (data->flags & MMC_DATA_WRITE)
 808                 return DMA_TO_DEVICE;
 809         else
 810                 return DMA_FROM_DEVICE;
 811 }
 812
 813 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 814 {
 815         int dma_ch;
 816
 817         spin_lock(&host->irq_lock);
 818         host->req_in_progress = 0;
 819         dma_ch = host->dma_ch;
 820         spin_unlock(&host->irq_lock);
 821
 822         omap_hsmmc_disable_irq(host);
 823         /* Do not complete the request if DMA is still in progress */
 824         if (mrq->data && host->use_dma && dma_ch != -1)
 825                 return;
 826         host->mrq = NULL;
 827         mmc_request_done(host->mmc, mrq);
 828 }
 829
 830 /*
 831  * Notify the transfer complete to MMC core
 832  */
 833 static void
 834 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 835 {
 836         if (!data) {
 837                 struct mmc_request *mrq = host->mrq;
 838
 839                 /* TC before CC from CMD6 - don't know why, but it happens */
 840                 if (host->cmd && host->cmd->opcode == 6 &&
 841                     host->response_busy) {
 842                         host->response_busy = 0;
 843                         return;
 844                 }
 845
 846                 omap_hsmmc_request_done(host, mrq);
 847                 return;
 848         }
 849
 850         host->data = NULL;
 851
 852         if (!data->error)
 853                 data->bytes_xfered += data->blocks * (data->blksz);
 854         else
 855                 data->bytes_xfered = 0;
 856
 857         if (!data->stop) {
 858                 omap_hsmmc_request_done(host, data->mrq);
 859                 return;
 860         }
 861         omap_hsmmc_start_command(host, data->stop, NULL);
 862 }
 863
 864 /*
 865  * Notify the core about command completion
 866  */
 867 static void
 868 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 869 {
 870         host->cmd = NULL;
 871
 872         if (cmd->flags & MMC_RSP_PRESENT) {
 873                 if (cmd->flags & MMC_RSP_136) {
 874                         /* response type 2 */
 875                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 876                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 877                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 878                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 879                 } else {
 880                         /* response types 1, 1b, 3, 4, 5, 6 */
 881                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 882                 }
 883         }
 884         if ((host->data == NULL && !host->response_busy) || cmd->error)
 885                 omap_hsmmc_request_done(host, cmd->mrq);
 886 }
 887
 888 /*
 889  * DMA clean up for command errors
 890  */
 891 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 892 {
 893         int dma_ch;
 894
 895         host->data->error = errno;
 896
 897         spin_lock(&host->irq_lock);
 898         dma_ch = host->dma_ch;
 899         host->dma_ch = -1;
 900         spin_unlock(&host->irq_lock);
 901
 902         if (host->use_dma && dma_ch != -1) {
 903                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 904                         host->data->sg_len,
 905                         omap_hsmmc_get_dma_dir(host, host->data));
 906                 omap_free_dma(dma_ch);
 907                 host->data->host_cookie = 0;
 908         }
 909         host->data = NULL;
 910 }
 911
 912 /*
 913  * Readable error output
 914  */
 915 #ifdef CONFIG_MMC_DEBUG
 916 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 917 {
 918         /* --- means reserved bit without definition at documentation */
 919         static const char *omap_hsmmc_status_bits[] = {
 920                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 921                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 922                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 923                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 924         };
 925         char res[256];
 926         char *buf = res;
 927         int len, i;
 928
 929         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 930         buf += len;
 931
 932         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 933                 if (status & (1 << i)) {
 934                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 935                         buf += len;
 936                 }
 937
 938         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 939 }
 940 #else
 941 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 942                                              u32 status)
 943 {
 944 }
 945 #endif  /* CONFIG_MMC_DEBUG */
 946
 947 /*
 948  * MMC controller internal state machines reset
 949  *
 950  * Used to reset command or data internal state machines, using respectively
 951  *  SRC or SRD bit of SYSCTL register
 952  * Can be called from interrupt context
 953  */
 954 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 955                                                    unsigned long bit)
 956 {
 957         unsigned long i = 0;
 958         unsigned long limit = (loops_per_jiffy *
 959                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 960
 961         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 962                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 963
 964         /*
 965          * OMAP4 ES2 and greater has an updated reset logic.
 966          * Monitor a 0->1 transition first
 967          */
 968         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 969                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 970                                         && (i++ < limit))
 971                         cpu_relax();
 972         }
 973         i = 0;
 974
 975         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 976                 (i++ < limit))
 977                 cpu_relax();
 978
 979         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 980                 dev_err(mmc_dev(host->mmc),
 981                         "Timeout waiting on controller reset in %s\n",
 982                         __func__);
 983 }
 984
 985 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 986 {
 987         struct mmc_data *data;
 988         int end_cmd = 0, end_trans = 0;
 989
 990         if (!host->req_in_progress) {
 991                 do {
 992                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 993                         /* Flush posted write */
 994                         status = OMAP_HSMMC_READ(host->base, STAT);
 995                 } while (status & INT_EN_MASK);
 996                 return;
 997         }
 998
 999         data = host->data;
1000         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1001
1002         if (status & ERR) {
1003                 omap_hsmmc_dbg_report_irq(host, status);
1004                 if ((status & CMD_TIMEOUT) ||
1005                         (status & CMD_CRC)) {
1006                         if (host->cmd) {
1007                                 if (status & CMD_TIMEOUT) {
1008                                         omap_hsmmc_reset_controller_fsm(host,
1009                                                                         SRC);
1010                                         host->cmd->error = -ETIMEDOUT;
1011                                 } else {
1012                                         host->cmd->error = -EILSEQ;
1013                                 }
1014                                 end_cmd = 1;
1015                         }
1016                         if (host->data || host->response_busy) {
1017                                 if (host->data)
1018                                         omap_hsmmc_dma_cleanup(host,
1019                                                                 -ETIMEDOUT);
1020                                 host->response_busy = 0;
1021                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1022                         }
1023                 }
1024                 if ((status & DATA_TIMEOUT) ||
1025                         (status & DATA_CRC)) {
1026                         if (host->data || host->response_busy) {
1027                                 int err = (status & DATA_TIMEOUT) ?
1028                                                 -ETIMEDOUT : -EILSEQ;
1029
1030                                 if (host->data)
1031                                         omap_hsmmc_dma_cleanup(host, err);
1032                                 else
1033                                         host->mrq->cmd->error = err;
1034                                 host->response_busy = 0;
1035                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1036                                 end_trans = 1;
1037                         }
1038                 }
1039                 if (status & CARD_ERR) {
1040                         dev_dbg(mmc_dev(host->mmc),
1041                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1042                         if (host->cmd)
1043                                 end_cmd = 1;
1044                         if (host->data)
1045                                 end_trans = 1;
1046                 }
1047         }
1048
1049         OMAP_HSMMC_WRITE(host->base, STAT, status);
1050
1051         if (end_cmd || ((status & CC) && host->cmd))
1052                 omap_hsmmc_cmd_done(host, host->cmd);
1053         if ((end_trans || (status & TC)) && host->mrq)
1054                 omap_hsmmc_xfer_done(host, data);
1055 }
1056
1057 /*
1058  * MMC controller IRQ handler
1059  */
1060 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1061 {
1062         struct omap_hsmmc_host *host = dev_id;
1063         int status;
1064
1065         status = OMAP_HSMMC_READ(host->base, STAT);
1066         do {
1067                 omap_hsmmc_do_irq(host, status);
1068                 /* Flush posted write */
1069                 status = OMAP_HSMMC_READ(host->base, STAT);
1070         } while (status & INT_EN_MASK);
1071
1072         return IRQ_HANDLED;
1073 }
1074
1075 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1076 {
1077         unsigned long i;
1078
1079         OMAP_HSMMC_WRITE(host->base, HCTL,
1080                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1081         for (i = 0; i < loops_per_jiffy; i++) {
1082                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1083                         break;
1084                 cpu_relax();
1085         }
1086 }
1087
1088 /*
1089  * Switch MMC interface voltage ... only relevant for MMC1.
1090  *
1091  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1092  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1093  * Some chips, like eMMC ones, use internal transceivers.
1094  */
1095 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1096 {
1097         u32 reg_val = 0;
1098         int ret;
1099
1100         /* Disable the clocks */
1101         pm_runtime_put_sync(host->dev);
1102         if (host->got_dbclk)
1103                 clk_disable(host->dbclk);
1104
1105         /* Turn the power off */
1106         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1107
1108         /* Turn the power ON with given VDD 1.8 or 3.0v */
1109         if (!ret)
1110                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1111                                                vdd);
1112         pm_runtime_get_sync(host->dev);
1113         if (host->got_dbclk)
1114                 clk_enable(host->dbclk);
1115
1116         if (ret != 0)
1117                 goto err;
1118
1119         OMAP_HSMMC_WRITE(host->base, HCTL,
1120                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1121         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1122
1123         /*
1124          * If a MMC dual voltage card is detected, the set_ios fn calls
1125          * this fn with VDD bit set for 1.8V. Upon card removal from the
1126          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1127          *
1128          * Cope with a bit of slop in the range ... per data sheets:
1129          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1130          *    but recommended values are 1.71V to 1.89V
1131          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1132          *    but recommended values are 2.7V to 3.3V
1133          *
1134          * Board setup code shouldn't permit anything very out-of-range.
1135          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1136          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1137          */
1138         if ((1 << vdd) <= MMC_VDD_23_24)
1139                 reg_val |= SDVS18;
1140         else
1141                 reg_val |= SDVS30;
1142
1143         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1144         set_sd_bus_power(host);
1145
1146         return 0;
1147 err:
1148         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1149         return ret;
1150 }
1151
1152 /* Protect the card while the cover is open */
1153 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1154 {
1155         if (!mmc_slot(host).get_cover_state)
1156                 return;
1157
1158         host->reqs_blocked = 0;
1159         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1160                 if (host->protect_card) {
1161                         pr_info("%s: cover is closed, "
1162                                          "card is now accessible\n",
1163                                          mmc_hostname(host->mmc));
1164                         host->protect_card = 0;
1165                 }
1166         } else {
1167                 if (!host->protect_card) {
1168                         pr_info("%s: cover is open, "
1169                                          "card is now inaccessible\n",
1170                                          mmc_hostname(host->mmc));
1171                         host->protect_card = 1;
1172                 }
1173         }
1174 }
1175
1176 /*
1177  * irq handler to notify the core about card insertion/removal
1178  */
1179 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1180 {
1181         struct omap_hsmmc_host *host = dev_id;
1182         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1183         int carddetect;
1184
1185         if (host->suspended)
1186                 return IRQ_HANDLED;
1187
1188         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1189
1190         if (slot->card_detect)
1191                 carddetect = slot->card_detect(host->dev, host->slot_id);
1192         else {
1193                 omap_hsmmc_protect_card(host);
1194                 carddetect = -ENOSYS;
1195         }
1196
1197         if (carddetect)
1198                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1199         else
1200                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1201         return IRQ_HANDLED;
1202 }
1203
1204 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1205                                      struct mmc_data *data)
1206 {
1207         int sync_dev;
1208
1209         if (data->flags & MMC_DATA_WRITE)
1210                 sync_dev = host->dma_line_tx;
1211         else
1212                 sync_dev = host->dma_line_rx;
1213         return sync_dev;
1214 }
1215
1216 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1217                                        struct mmc_data *data,
1218                                        struct scatterlist *sgl)
1219 {
1220         int blksz, nblk, dma_ch;
1221
1222         dma_ch = host->dma_ch;
1223         if (data->flags & MMC_DATA_WRITE) {
1224                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1225                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1226                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1227                         sg_dma_address(sgl), 0, 0);
1228         } else {
1229                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1230                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1231                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1232                         sg_dma_address(sgl), 0, 0);
1233         }
1234
1235         blksz = host->data->blksz;
1236         nblk = sg_dma_len(sgl) / blksz;
1237
1238         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1239                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1240                         omap_hsmmc_get_dma_sync_dev(host, data),
1241                         !(data->flags & MMC_DATA_WRITE));
1242
1243         omap_start_dma(dma_ch);
1244 }
1245
1246 /*
1247  * DMA call back function
1248  */
1249 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1250 {
1251         struct omap_hsmmc_host *host = cb_data;
1252         struct mmc_data *data;
1253         int dma_ch, req_in_progress;
1254
1255         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1256                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1257                         ch_status);
1258                 return;
1259         }
1260
1261         spin_lock(&host->irq_lock);
1262         if (host->dma_ch < 0) {
1263                 spin_unlock(&host->irq_lock);
1264                 return;
1265         }
1266
1267         data = host->mrq->data;
1268         host->dma_sg_idx++;
1269         if (host->dma_sg_idx < host->dma_len) {
1270                 /* Fire up the next transfer. */
1271                 omap_hsmmc_config_dma_params(host, data,
1272                                            data->sg + host->dma_sg_idx);
1273                 spin_unlock(&host->irq_lock);
1274                 return;
1275         }
1276
1277         if (!data->host_cookie)
1278                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1279                              omap_hsmmc_get_dma_dir(host, data));
1280
1281         req_in_progress = host->req_in_progress;
1282         dma_ch = host->dma_ch;
1283         host->dma_ch = -1;
1284         spin_unlock(&host->irq_lock);
1285
1286         omap_free_dma(dma_ch);
1287
1288         /* If DMA has finished after TC, complete the request */
1289         if (!req_in_progress) {
1290                 struct mmc_request *mrq = host->mrq;
1291
1292                 host->mrq = NULL;
1293                 mmc_request_done(host->mmc, mrq);
1294         }
1295 }
1296
1297 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1298                                        struct mmc_data *data,
1299                                        struct omap_hsmmc_next *next)
1300 {
1301         int dma_len;
1302
1303         if (!next && data->host_cookie &&
1304             data->host_cookie != host->next_data.cookie) {
1305                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1306                        " host->next_data.cookie %d\n",
1307                        __func__, data->host_cookie, host->next_data.cookie);
1308                 data->host_cookie = 0;
1309         }
1310
1311         /* Check if next job is already prepared */
1312         if (next ||
1313             (!next && data->host_cookie != host->next_data.cookie)) {
1314                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1315                                      data->sg_len,
1316                                      omap_hsmmc_get_dma_dir(host, data));
1317
1318         } else {
1319                 dma_len = host->next_data.dma_len;
1320                 host->next_data.dma_len = 0;
1321         }
1322
1323
1324         if (dma_len == 0)
1325                 return -EINVAL;
1326
1327         if (next) {
1328                 next->dma_len = dma_len;
1329                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1330         } else
1331                 host->dma_len = dma_len;
1332
1333         return 0;
1334 }
1335
1336 /*
1337  * Routine to configure and start DMA for the MMC card
1338  */
1339 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1340                                         struct mmc_request *req)
1341 {
1342         int dma_ch = 0, ret = 0, i;
1343         struct mmc_data *data = req->data;
1344
1345         /* Sanity check: all the SG entries must be aligned by block size. */
1346         for (i = 0; i < data->sg_len; i++) {
1347                 struct scatterlist *sgl;
1348
1349                 sgl = data->sg + i;
1350                 if (sgl->length % data->blksz)
1351                         return -EINVAL;
1352         }
1353         if ((data->blksz % 4) != 0)
1354                 /* REVISIT: The MMC buffer increments only when MSB is written.
1355                  * Return error for blksz which is non multiple of four.
1356                  */
1357                 return -EINVAL;
1358
1359         BUG_ON(host->dma_ch != -1);
1360
1361         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1362                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1363         if (ret != 0) {
1364                 dev_err(mmc_dev(host->mmc),
1365                         "%s: omap_request_dma() failed with %d\n",
1366                         mmc_hostname(host->mmc), ret);
1367                 return ret;
1368         }
1369         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1370         if (ret)
1371                 return ret;
1372
1373         host->dma_ch = dma_ch;
1374         host->dma_sg_idx = 0;
1375
1376         omap_hsmmc_config_dma_params(host, data, data->sg);
1377
1378         return 0;
1379 }
1380
1381 static void set_data_timeout(struct omap_hsmmc_host *host,
1382                              unsigned int timeout_ns,
1383                              unsigned int timeout_clks)
1384 {
1385         unsigned int timeout, cycle_ns;
1386         uint32_t reg, clkd, dto = 0;
1387
1388         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1389         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1390         if (clkd == 0)
1391                 clkd = 1;
1392
1393         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1394         timeout = timeout_ns / cycle_ns;
1395         timeout += timeout_clks;
1396         if (timeout) {
1397                 while ((timeout & 0x80000000) == 0) {
1398                         dto += 1;
1399                         timeout <<= 1;
1400                 }
1401                 dto = 31 - dto;
1402                 timeout <<= 1;
1403                 if (timeout && dto)
1404                         dto += 1;
1405                 if (dto >= 13)
1406                         dto -= 13;
1407                 else
1408                         dto = 0;
1409                 if (dto > 14)
1410                         dto = 14;
1411         }
1412
1413         reg &= ~DTO_MASK;
1414         reg |= dto << DTO_SHIFT;
1415         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1416 }
1417
1418 /*
1419  * Configure block length for MMC/SD cards and initiate the transfer.
1420  */
1421 static int
1422 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1423 {
1424         int ret;
1425         host->data = req->data;
1426
1427         if (req->data == NULL) {
1428                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1429                 /*
1430                  * Set an arbitrary 100ms data timeout for commands with
1431                  * busy signal.
1432                  */
1433                 if (req->cmd->flags & MMC_RSP_BUSY)
1434                         set_data_timeout(host, 100000000U, 0);
1435                 return 0;
1436         }
1437
1438         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1439                                         | (req->data->blocks << 16));
1440         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1441
1442         if (host->use_dma) {
1443                 ret = omap_hsmmc_start_dma_transfer(host, req);
1444                 if (ret != 0) {
1445                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1446                         return ret;
1447                 }
1448         }
1449         return 0;
1450 }
1451
1452 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1453                                 int err)
1454 {
1455         struct omap_hsmmc_host *host = mmc_priv(mmc);
1456         struct mmc_data *data = mrq->data;
1457
1458         if (host->use_dma) {
1459                 if (data->host_cookie)
1460                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1461                                      data->sg_len,
1462                                      omap_hsmmc_get_dma_dir(host, data));
1463                 data->host_cookie = 0;
1464         }
1465 }
1466
1467 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1468                                bool is_first_req)
1469 {
1470         struct omap_hsmmc_host *host = mmc_priv(mmc);
1471
1472         if (mrq->data->host_cookie) {
1473                 mrq->data->host_cookie = 0;
1474                 return ;
1475         }
1476
1477         if (host->use_dma)
1478                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1479                                                 &host->next_data))
1480                         mrq->data->host_cookie = 0;
1481 }
1482
1483 /*
1484  * Request function. for read/write operation
1485  */
1486 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1487 {
1488         struct omap_hsmmc_host *host = mmc_priv(mmc);
1489         int err;
1490
1491         BUG_ON(host->req_in_progress);
1492         BUG_ON(host->dma_ch != -1);
1493         if (host->protect_card) {
1494                 if (host->reqs_blocked < 3) {
1495                         /*
1496                          * Ensure the controller is left in a consistent
1497                          * state by resetting the command and data state
1498                          * machines.
1499                          */
1500                         omap_hsmmc_reset_controller_fsm(host, SRD);
1501                         omap_hsmmc_reset_controller_fsm(host, SRC);
1502                         host->reqs_blocked += 1;
1503                 }
1504                 req->cmd->error = -EBADF;
1505                 if (req->data)
1506                         req->data->error = -EBADF;
1507                 req->cmd->retries = 0;
1508                 mmc_request_done(mmc, req);
1509                 return;
1510         } else if (host->reqs_blocked)
1511                 host->reqs_blocked = 0;
1512         WARN_ON(host->mrq != NULL);
1513         host->mrq = req;
1514         err = omap_hsmmc_prepare_data(host, req);
1515         if (err) {
1516                 req->cmd->error = err;
1517                 if (req->data)
1518                         req->data->error = err;
1519                 host->mrq = NULL;
1520                 mmc_request_done(mmc, req);
1521                 return;
1522         }
1523
1524         omap_hsmmc_start_command(host, req->cmd, req->data);
1525 }
1526
1527 /* Routine to configure clock values. Exposed API to core */
1528 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1529 {
1530         struct omap_hsmmc_host *host = mmc_priv(mmc);
1531         int do_send_init_stream = 0;
1532
1533         pm_runtime_get_sync(host->dev);
1534
1535         if (ios->power_mode != host->power_mode) {
1536                 switch (ios->power_mode) {
1537                 case MMC_POWER_OFF:
1538                         mmc_slot(host).set_power(host->dev, host->slot_id,
1539                                                  0, 0);
1540                         host->vdd = 0;
1541                         break;
1542                 case MMC_POWER_UP:
1543                         mmc_slot(host).set_power(host->dev, host->slot_id,
1544                                                  1, ios->vdd);
1545                         host->vdd = ios->vdd;
1546                         break;
1547                 case MMC_POWER_ON:
1548                         do_send_init_stream = 1;
1549                         break;
1550                 }
1551                 host->power_mode = ios->power_mode;
1552         }
1553
1554         /* FIXME: set registers based only on changes to ios */
1555
1556         omap_hsmmc_set_bus_width(host);
1557
1558         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1559                 /* Only MMC1 can interface at 3V without some flavor
1560                  * of external transceiver; but they all handle 1.8V.
1561                  */
1562                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1563                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1564                                 /*
1565                                  * The mmc_select_voltage fn of the core does
1566                                  * not seem to set the power_mode to
1567                                  * MMC_POWER_UP upon recalculating the voltage.
1568                                  * vdd 1.8v.
1569                                  */
1570                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1571                                 dev_dbg(mmc_dev(host->mmc),
1572                                                 "Switch operation failed\n");
1573                 }
1574         }
1575
1576         omap_hsmmc_set_clock(host);
1577
1578         if (do_send_init_stream)
1579                 send_init_stream(host);
1580
1581         omap_hsmmc_set_bus_mode(host);
1582
1583         pm_runtime_put_autosuspend(host->dev);
1584 }
1585
1586 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1587 {
1588         struct omap_hsmmc_host *host = mmc_priv(mmc);
1589
1590         if (!mmc_slot(host).card_detect)
1591                 return -ENOSYS;
1592         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1593 }
1594
1595 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1596 {
1597         struct omap_hsmmc_host *host = mmc_priv(mmc);
1598
1599         if (!mmc_slot(host).get_ro)
1600                 return -ENOSYS;
1601         return mmc_slot(host).get_ro(host->dev, 0);
1602 }
1603
1604 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1605 {
1606         struct omap_hsmmc_host *host = mmc_priv(mmc);
1607
1608         if (mmc_slot(host).init_card)
1609                 mmc_slot(host).init_card(card);
1610 }
1611
1612 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1613 {
1614         u32 hctl, capa, value;
1615
1616         /* Only MMC1 supports 3.0V */
1617         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1618                 hctl = SDVS30;
1619                 capa = VS30 | VS18;
1620         } else {
1621                 hctl = SDVS18;
1622                 capa = VS18;
1623         }
1624
1625         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1626         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1627
1628         value = OMAP_HSMMC_READ(host->base, CAPA);
1629         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1630
1631         /* Set the controller to AUTO IDLE mode */
1632         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1633         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1634
1635         /* Set SD bus power bit */
1636         set_sd_bus_power(host);
1637 }
1638
1639 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1640 {
1641         struct omap_hsmmc_host *host = mmc_priv(mmc);
1642
1643         pm_runtime_get_sync(host->dev);
1644
1645         return 0;
1646 }
1647
1648 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1649 {
1650         struct omap_hsmmc_host *host = mmc_priv(mmc);
1651
1652         pm_runtime_mark_last_busy(host->dev);
1653         pm_runtime_put_autosuspend(host->dev);
1654
1655         return 0;
1656 }
1657
1658 static const struct mmc_host_ops omap_hsmmc_ops = {
1659         .enable = omap_hsmmc_enable_fclk,
1660         .disable = omap_hsmmc_disable_fclk,
1661         .post_req = omap_hsmmc_post_req,
1662         .pre_req = omap_hsmmc_pre_req,
1663         .request = omap_hsmmc_request,
1664         .set_ios = omap_hsmmc_set_ios,
1665         .get_cd = omap_hsmmc_get_cd,
1666         .get_ro = omap_hsmmc_get_ro,
1667         .init_card = omap_hsmmc_init_card,
1668         /* NYET -- enable_sdio_irq */
1669 };
1670
1671 #ifdef CONFIG_DEBUG_FS
1672
1673 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1674 {
1675         struct mmc_host *mmc = s->private;
1676         struct omap_hsmmc_host *host = mmc_priv(mmc);
1677         int context_loss = 0;
1678
1679         if (host->pdata->get_context_loss_count)
1680                 context_loss = host->pdata->get_context_loss_count(host->dev);
1681
1682         seq_printf(s, "mmc%d:\n"
1683                         " enabled:\t%d\n"
1684                         " dpm_state:\t%d\n"
1685                         " nesting_cnt:\t%d\n"
1686                         " ctx_loss:\t%d:%d\n"
1687                         "\nregs:\n",
1688                         mmc->index, mmc->enabled ? 1 : 0,
1689                         host->dpm_state, mmc->nesting_cnt,
1690                         host->context_loss, context_loss);
1691
1692         if (host->suspended) {
1693                 seq_printf(s, "host suspended, can't read registers\n");
1694                 return 0;
1695         }
1696
1697         pm_runtime_get_sync(host->dev);
1698
1699         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1700                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1701         seq_printf(s, "CON:\t\t0x%08x\n",
1702                         OMAP_HSMMC_READ(host->base, CON));
1703         seq_printf(s, "HCTL:\t\t0x%08x\n",
1704                         OMAP_HSMMC_READ(host->base, HCTL));
1705         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1706                         OMAP_HSMMC_READ(host->base, SYSCTL));
1707         seq_printf(s, "IE:\t\t0x%08x\n",
1708                         OMAP_HSMMC_READ(host->base, IE));
1709         seq_printf(s, "ISE:\t\t0x%08x\n",
1710                         OMAP_HSMMC_READ(host->base, ISE));
1711         seq_printf(s, "CAPA:\t\t0x%08x\n",
1712                         OMAP_HSMMC_READ(host->base, CAPA));
1713
1714         pm_runtime_mark_last_busy(host->dev);
1715         pm_runtime_put_autosuspend(host->dev);
1716
1717         return 0;
1718 }
1719
1720 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1721 {
1722         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1723 }
1724
1725 static const struct file_operations mmc_regs_fops = {
1726         .open           = omap_hsmmc_regs_open,
1727         .read           = seq_read,
1728         .llseek         = seq_lseek,
1729         .release        = single_release,
1730 };
1731
1732 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1733 {
1734         if (mmc->debugfs_root)
1735                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1736                         mmc, &mmc_regs_fops);
1737 }
1738
1739 #else
1740
1741 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1742 {
1743 }
1744
1745 #endif
1746
1747 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1748 {
1749         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1750         struct mmc_host *mmc;
1751         struct omap_hsmmc_host *host = NULL;
1752         struct resource *res;
1753         int ret, irq;
1754
1755         if (pdata == NULL) {
1756                 dev_err(&pdev->dev, "Platform Data is missing\n");
1757                 return -ENXIO;
1758         }
1759
1760         if (pdata->nr_slots == 0) {
1761                 dev_err(&pdev->dev, "No Slots\n");
1762                 return -ENXIO;
1763         }
1764
1765         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1766         irq = platform_get_irq(pdev, 0);
1767         if (res == NULL || irq < 0)
1768                 return -ENXIO;
1769
1770         res->start += pdata->reg_offset;
1771         res->end += pdata->reg_offset;
1772         res = request_mem_region(res->start, resource_size(res), pdev->name);
1773         if (res == NULL)
1774                 return -EBUSY;
1775
1776         ret = omap_hsmmc_gpio_init(pdata);
1777         if (ret)
1778                 goto err;
1779
1780         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1781         if (!mmc) {
1782                 ret = -ENOMEM;
1783                 goto err_alloc;
1784         }
1785
1786         host            = mmc_priv(mmc);
1787         host->mmc       = mmc;
1788         host->pdata     = pdata;
1789         host->dev       = &pdev->dev;
1790         host->use_dma   = 1;
1791         host->dev->dma_mask = &pdata->dma_mask;
1792         host->dma_ch    = -1;
1793         host->irq       = irq;
1794         host->id        = pdev->id;
1795         host->slot_id   = 0;
1796         host->mapbase   = res->start;
1797         host->base      = ioremap(host->mapbase, SZ_4K);
1798         host->power_mode = MMC_POWER_OFF;
1799         host->next_data.cookie = 1;
1800
1801         platform_set_drvdata(pdev, host);
1802
1803         mmc->ops        = &omap_hsmmc_ops;
1804
1805         /*
1806          * If regulator_disable can only put vcc_aux to sleep then there is
1807          * no off state.
1808          */
1809         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1810                 mmc_slot(host).no_off = 1;
1811
1812         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1813
1814         if (pdata->max_freq > 0)
1815                 mmc->f_max = pdata->max_freq;
1816         else
1817                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1818
1819         spin_lock_init(&host->irq_lock);
1820
1821         host->fclk = clk_get(&pdev->dev, "fck");
1822         if (IS_ERR(host->fclk)) {
1823                 ret = PTR_ERR(host->fclk);
1824                 host->fclk = NULL;
1825                 goto err1;
1826         }
1827
1828         omap_hsmmc_context_save(host);
1829
1830         mmc->caps |= MMC_CAP_DISABLE;
1831         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1832                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1833                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1834         }
1835
1836         pm_runtime_enable(host->dev);
1837         pm_runtime_get_sync(host->dev);
1838         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1839         pm_runtime_use_autosuspend(host->dev);
1840
1841         if (cpu_is_omap2430()) {
1842                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1843                 /*
1844                  * MMC can still work without debounce clock.
1845                  */
1846                 if (IS_ERR(host->dbclk))
1847                         dev_warn(mmc_dev(host->mmc),
1848                                 "Failed to get debounce clock\n");
1849                 else
1850                         host->got_dbclk = 1;
1851
1852                 if (host->got_dbclk)
1853                         if (clk_enable(host->dbclk) != 0)
1854                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1855                                                         " clk failed\n");
1856         }
1857
1858         /* Since we do only SG emulation, we can have as many segs
1859          * as we want. */
1860         mmc->max_segs = 1024;
1861
1862         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1863         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1864         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1865         mmc->max_seg_size = mmc->max_req_size;
1866
1867         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1868                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1869
1870         mmc->caps |= mmc_slot(host).caps;
1871         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1872                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1873
1874         if (mmc_slot(host).nonremovable)
1875                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1876
1877         mmc->pm_caps = mmc_slot(host).pm_caps;
1878
1879         omap_hsmmc_conf_bus_power(host);
1880
1881         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1882         if (!res) {
1883                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1884                 goto err_irq;
1885         }
1886         host->dma_line_tx = res->start;
1887
1888         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1889         if (!res) {
1890                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1891                 goto err_irq;
1892         }
1893         host->dma_line_rx = res->start;
1894
1895         /* Request IRQ for MMC operations */
1896         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1897                         mmc_hostname(mmc), host);
1898         if (ret) {
1899                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1900                 goto err_irq;
1901         }
1902
1903         if (pdata->init != NULL) {
1904                 if (pdata->init(&pdev->dev) != 0) {
1905                         dev_dbg(mmc_dev(host->mmc),
1906                                 "Unable to configure MMC IRQs\n");
1907                         goto err_irq_cd_init;
1908                 }
1909         }
1910
1911         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1912                 ret = omap_hsmmc_reg_get(host);
1913                 if (ret)
1914                         goto err_reg;
1915                 host->use_reg = 1;
1916         }
1917
1918         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1919
1920         /* Request IRQ for card detect */
1921         if ((mmc_slot(host).card_detect_irq)) {
1922                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1923                                            NULL,
1924                                            omap_hsmmc_detect,
1925                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1926                                            mmc_hostname(mmc), host);
1927                 if (ret) {
1928                         dev_dbg(mmc_dev(host->mmc),
1929                                 "Unable to grab MMC CD IRQ\n");
1930                         goto err_irq_cd;
1931                 }
1932                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1933                 pdata->resume = omap_hsmmc_resume_cdirq;
1934         }
1935
1936         omap_hsmmc_disable_irq(host);
1937
1938         omap_hsmmc_protect_card(host);
1939
1940         mmc_add_host(mmc);
1941
1942         if (mmc_slot(host).name != NULL) {
1943                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1944                 if (ret < 0)
1945                         goto err_slot_name;
1946         }
1947         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1948                 ret = device_create_file(&mmc->class_dev,
1949                                         &dev_attr_cover_switch);
1950                 if (ret < 0)
1951                         goto err_slot_name;
1952         }
1953
1954         omap_hsmmc_debugfs(mmc);
1955         pm_runtime_mark_last_busy(host->dev);
1956         pm_runtime_put_autosuspend(host->dev);
1957
1958         return 0;
1959
1960 err_slot_name:
1961         mmc_remove_host(mmc);
1962         free_irq(mmc_slot(host).card_detect_irq, host);
1963 err_irq_cd:
1964         if (host->use_reg)
1965                 omap_hsmmc_reg_put(host);
1966 err_reg:
1967         if (host->pdata->cleanup)
1968                 host->pdata->cleanup(&pdev->dev);
1969 err_irq_cd_init:
1970         free_irq(host->irq, host);
1971 err_irq:
1972         pm_runtime_mark_last_busy(host->dev);
1973         pm_runtime_put_autosuspend(host->dev);
1974         clk_put(host->fclk);
1975         if (host->got_dbclk) {
1976                 clk_disable(host->dbclk);
1977                 clk_put(host->dbclk);
1978         }
1979 err1:
1980         iounmap(host->base);
1981         platform_set_drvdata(pdev, NULL);
1982         mmc_free_host(mmc);
1983 err_alloc:
1984         omap_hsmmc_gpio_free(pdata);
1985 err:
1986         release_mem_region(res->start, resource_size(res));
1987         return ret;
1988 }
1989
1990 static int omap_hsmmc_remove(struct platform_device *pdev)
1991 {
1992         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1993         struct resource *res;
1994
1995         if (host) {
1996                 pm_runtime_get_sync(host->dev);
1997                 mmc_remove_host(host->mmc);
1998                 if (host->use_reg)
1999                         omap_hsmmc_reg_put(host);
2000                 if (host->pdata->cleanup)
2001                         host->pdata->cleanup(&pdev->dev);
2002                 free_irq(host->irq, host);
2003                 if (mmc_slot(host).card_detect_irq)
2004                         free_irq(mmc_slot(host).card_detect_irq, host);
2005
2006                 pm_runtime_put_sync(host->dev);
2007                 pm_runtime_disable(host->dev);
2008                 clk_put(host->fclk);
2009                 if (host->got_dbclk) {
2010                         clk_disable(host->dbclk);
2011                         clk_put(host->dbclk);
2012                 }
2013
2014                 mmc_free_host(host->mmc);
2015                 iounmap(host->base);
2016                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2017         }
2018
2019         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2020         if (res)
2021                 release_mem_region(res->start, resource_size(res));
2022         platform_set_drvdata(pdev, NULL);
2023
2024         return 0;
2025 }
2026
2027 #ifdef CONFIG_PM
2028 static int omap_hsmmc_suspend(struct device *dev)
2029 {
2030         int ret = 0;
2031         struct platform_device *pdev = to_platform_device(dev);
2032         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2033
2034         if (host && host->suspended)
2035                 return 0;
2036
2037         if (host) {
2038                 pm_runtime_get_sync(host->dev);
2039                 host->suspended = 1;
2040                 if (host->pdata->suspend) {
2041                         ret = host->pdata->suspend(&pdev->dev,
2042                                                         host->slot_id);
2043                         if (ret) {
2044                                 dev_dbg(mmc_dev(host->mmc),
2045                                         "Unable to handle MMC board"
2046                                         " level suspend\n");
2047                                 host->suspended = 0;
2048                                 return ret;
2049                         }
2050                 }
2051                 ret = mmc_suspend_host(host->mmc);
2052
2053                 if (ret) {
2054                         host->suspended = 0;
2055                         if (host->pdata->resume) {
2056                                 ret = host->pdata->resume(&pdev->dev,
2057                                                           host->slot_id);
2058                                 if (ret)
2059                                         dev_dbg(mmc_dev(host->mmc),
2060                                                 "Unmask interrupt failed\n");
2061                         }
2062                         goto err;
2063                 }
2064
2065                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2066                         omap_hsmmc_disable_irq(host);
2067                         OMAP_HSMMC_WRITE(host->base, HCTL,
2068                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2069                 }
2070                 if (host->got_dbclk)
2071                         clk_disable(host->dbclk);
2072
2073         }
2074 err:
2075         pm_runtime_put_sync(host->dev);
2076         return ret;
2077 }
2078
2079 /* Routine to resume the MMC device */
2080 static int omap_hsmmc_resume(struct device *dev)
2081 {
2082         int ret = 0;
2083         struct platform_device *pdev = to_platform_device(dev);
2084         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2085
2086         if (host && !host->suspended)
2087                 return 0;
2088
2089         if (host) {
2090                 pm_runtime_get_sync(host->dev);
2091
2092                 if (host->got_dbclk)
2093                         clk_enable(host->dbclk);
2094
2095                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2096                         omap_hsmmc_conf_bus_power(host);
2097
2098                 if (host->pdata->resume) {
2099                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2100                         if (ret)
2101                                 dev_dbg(mmc_dev(host->mmc),
2102                                         "Unmask interrupt failed\n");
2103                 }
2104
2105                 omap_hsmmc_protect_card(host);
2106
2107                 /* Notify the core to resume the host */
2108                 ret = mmc_resume_host(host->mmc);
2109                 if (ret == 0)
2110                         host->suspended = 0;
2111
2112                 pm_runtime_mark_last_busy(host->dev);
2113                 pm_runtime_put_autosuspend(host->dev);
2114         }
2115
2116         return ret;
2117
2118 }
2119
2120 #else
2121 #define omap_hsmmc_suspend      NULL
2122 #define omap_hsmmc_resume               NULL
2123 #endif
2124
2125 static int omap_hsmmc_runtime_suspend(struct device *dev)
2126 {
2127         struct omap_hsmmc_host *host;
2128
2129         host = platform_get_drvdata(to_platform_device(dev));
2130         omap_hsmmc_context_save(host);
2131         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2132
2133         return 0;
2134 }
2135
2136 static int omap_hsmmc_runtime_resume(struct device *dev)
2137 {
2138         struct omap_hsmmc_host *host;
2139
2140         host = platform_get_drvdata(to_platform_device(dev));
2141         omap_hsmmc_context_restore(host);
2142         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2143
2144         return 0;
2145 }
2146
2147 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2148         .suspend        = omap_hsmmc_suspend,
2149         .resume         = omap_hsmmc_resume,
2150         .runtime_suspend = omap_hsmmc_runtime_suspend,
2151         .runtime_resume = omap_hsmmc_runtime_resume,
2152 };
2153
2154 static struct platform_driver omap_hsmmc_driver = {
2155         .remove         = omap_hsmmc_remove,
2156         .driver         = {
2157                 .name = DRIVER_NAME,
2158                 .owner = THIS_MODULE,
2159                 .pm = &omap_hsmmc_dev_pm_ops,
2160         },
2161 };
2162
2163 static int __init omap_hsmmc_init(void)
2164 {
2165         /* Register the MMC driver */
2166         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2167 }
2168
2169 static void __exit omap_hsmmc_cleanup(void)
2170 {
2171         /* Unregister MMC driver */
2172         platform_driver_unregister(&omap_hsmmc_driver);
2173 }
2174
2175 module_init(omap_hsmmc_init);
2176 module_exit(omap_hsmmc_cleanup);
2177
2178 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2179 MODULE_LICENSE("GPL");
2180 MODULE_ALIAS("platform:" DRIVER_NAME);
2181 MODULE_AUTHOR("Texas Instruments Inc");