2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
32 #include <linux/semaphore.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
36 #include <mach/hardware.h>
37 #include <plat/board.h>
41 /* OMAP HSMMC Host Controller Registers */
42 #define OMAP_HSMMC_SYSCONFIG 0x0010
43 #define OMAP_HSMMC_SYSSTATUS 0x0014
44 #define OMAP_HSMMC_CON 0x002C
45 #define OMAP_HSMMC_BLK 0x0104
46 #define OMAP_HSMMC_ARG 0x0108
47 #define OMAP_HSMMC_CMD 0x010C
48 #define OMAP_HSMMC_RSP10 0x0110
49 #define OMAP_HSMMC_RSP32 0x0114
50 #define OMAP_HSMMC_RSP54 0x0118
51 #define OMAP_HSMMC_RSP76 0x011C
52 #define OMAP_HSMMC_DATA 0x0120
53 #define OMAP_HSMMC_HCTL 0x0128
54 #define OMAP_HSMMC_SYSCTL 0x012C
55 #define OMAP_HSMMC_STAT 0x0130
56 #define OMAP_HSMMC_IE 0x0134
57 #define OMAP_HSMMC_ISE 0x0138
58 #define OMAP_HSMMC_CAPA 0x0140
60 #define VS18 (1 << 26)
61 #define VS30 (1 << 25)
62 #define SDVS18 (0x5 << 9)
63 #define SDVS30 (0x6 << 9)
64 #define SDVS33 (0x7 << 9)
65 #define SDVS_MASK 0x00000E00
66 #define SDVSCLR 0xFFFFF1FF
67 #define SDVSDET 0x00000400
74 #define CLKD_MASK 0x0000FFC0
76 #define DTO_MASK 0x000F0000
78 #define INT_EN_MASK 0x307F0033
79 #define BWR_ENABLE (1 << 4)
80 #define BRR_ENABLE (1 << 5)
81 #define INIT_STREAM (1 << 1)
82 #define DP_SELECT (1 << 21)
87 #define FOUR_BIT (1 << 1)
93 #define CMD_TIMEOUT (1 << 16)
94 #define DATA_TIMEOUT (1 << 20)
95 #define CMD_CRC (1 << 17)
96 #define DATA_CRC (1 << 21)
97 #define CARD_ERR (1 << 28)
98 #define STAT_CLEAR 0xFFFFFFFF
99 #define INIT_STREAM_CMD 0x00000000
100 #define DUAL_VOLT_OCR_BIT 7
101 #define SRC (1 << 25)
102 #define SRD (1 << 26)
103 #define SOFTRESET (1 << 1)
104 #define RESETDONE (1 << 0)
107 * FIXME: Most likely all the data using these _DEVID defines should come
108 * from the platform_data, or implemented in controller and slot specific
111 #define OMAP_MMC1_DEVID 0
112 #define OMAP_MMC2_DEVID 1
113 #define OMAP_MMC3_DEVID 2
114 #define OMAP_MMC4_DEVID 3
115 #define OMAP_MMC5_DEVID 4
117 #define MMC_TIMEOUT_MS 20
118 #define OMAP_MMC_MASTER_CLOCK 96000000
119 #define DRIVER_NAME "mmci-omap-hs"
121 /* Timeouts for entering power saving states on inactivity, msec */
122 #define OMAP_MMC_DISABLED_TIMEOUT 100
123 #define OMAP_MMC_SLEEP_TIMEOUT 1000
124 #define OMAP_MMC_OFF_TIMEOUT 8000
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
131 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134 * MMC Host controller read/write API's
136 #define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142 struct omap_hsmmc_host {
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
152 * vcc == configured supply
153 * vcc_aux == optional
154 * - MMC1, supply for DAT4..DAT7
155 * - MMC2/MMC2, external level shifter voltage supply, for
156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
158 struct regulator *vcc;
159 struct regulator *vcc_aux;
160 struct semaphore sem;
161 struct work_struct mmc_carddetect_work;
163 resource_size_t mapbase;
164 spinlock_t irq_lock; /* Prevent races with irq handler */
167 unsigned int dma_len;
168 unsigned int dma_sg_idx;
169 unsigned char bus_mode;
170 unsigned char power_mode;
176 int dma_line_tx, dma_line_rx;
187 struct omap_mmc_platform_data *pdata;
190 static int omap_hsmmc_card_detect(struct device *dev, int slot)
192 struct omap_mmc_platform_data *mmc = dev->platform_data;
194 /* NOTE: assumes card detect signal is active-low */
195 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
198 static int omap_hsmmc_get_wp(struct device *dev, int slot)
200 struct omap_mmc_platform_data *mmc = dev->platform_data;
202 /* NOTE: assumes write protect signal is active-high */
203 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
206 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208 struct omap_mmc_platform_data *mmc = dev->platform_data;
210 /* NOTE: assumes card detect signal is active-low */
211 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
216 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218 struct omap_mmc_platform_data *mmc = dev->platform_data;
220 disable_irq(mmc->slots[0].card_detect_irq);
224 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226 struct omap_mmc_platform_data *mmc = dev->platform_data;
228 enable_irq(mmc->slots[0].card_detect_irq);
234 #define omap_hsmmc_suspend_cdirq NULL
235 #define omap_hsmmc_resume_cdirq NULL
239 #ifdef CONFIG_REGULATOR
241 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
244 struct omap_hsmmc_host *host =
245 platform_get_drvdata(to_platform_device(dev));
248 if (mmc_slot(host).before_set_reg)
249 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
252 ret = mmc_regulator_set_ocr(host->vcc, vdd);
254 ret = mmc_regulator_set_ocr(host->vcc, 0);
256 if (mmc_slot(host).after_set_reg)
257 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
262 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
265 struct omap_hsmmc_host *host =
266 platform_get_drvdata(to_platform_device(dev));
270 * If we don't see a Vcc regulator, assume it's a fixed
271 * voltage always-on regulator.
276 if (mmc_slot(host).before_set_reg)
277 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
280 * Assume Vcc regulator is used only to power the card ... OMAP
281 * VDDS is used to power the pins, optionally with a transceiver to
282 * support cards using voltages other than VDDS (1.8V nominal). When a
283 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 * In some cases this regulator won't support enable/disable;
286 * e.g. it's a fixed rail for a WLAN chip.
288 * In other cases vcc_aux switches interface power. Example, for
289 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
290 * chips/cards need an interface voltage rail too.
293 ret = mmc_regulator_set_ocr(host->vcc, vdd);
294 /* Enable interface voltage rail, if needed */
295 if (ret == 0 && host->vcc_aux) {
296 ret = regulator_enable(host->vcc_aux);
298 ret = mmc_regulator_set_ocr(host->vcc, 0);
302 ret = regulator_disable(host->vcc_aux);
304 ret = mmc_regulator_set_ocr(host->vcc, 0);
307 if (mmc_slot(host).after_set_reg)
308 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
313 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
314 int vdd, int cardsleep)
316 struct omap_hsmmc_host *host =
317 platform_get_drvdata(to_platform_device(dev));
318 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
320 return regulator_set_mode(host->vcc, mode);
323 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
324 int vdd, int cardsleep)
326 struct omap_hsmmc_host *host =
327 platform_get_drvdata(to_platform_device(dev));
331 * If we don't see a Vcc regulator, assume it's a fixed
332 * voltage always-on regulator.
337 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
340 return regulator_set_mode(host->vcc, mode);
343 /* VCC can be turned off if card is asleep */
345 err = mmc_regulator_set_ocr(host->vcc, 0);
347 err = mmc_regulator_set_ocr(host->vcc, vdd);
349 err = regulator_set_mode(host->vcc, mode);
353 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
354 return regulator_set_mode(host->vcc_aux, mode);
357 return regulator_disable(host->vcc_aux);
359 return regulator_enable(host->vcc_aux);
362 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
364 struct regulator *reg;
368 case OMAP_MMC1_DEVID:
369 /* On-chip level shifting via PBIAS0/PBIAS1 */
370 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
371 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
373 case OMAP_MMC2_DEVID:
374 case OMAP_MMC3_DEVID:
375 /* Off-chip level shifting, or none */
376 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
377 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
380 pr_err("MMC%d configuration not supported!\n", host->id);
384 reg = regulator_get(host->dev, "vmmc");
386 dev_dbg(host->dev, "vmmc regulator missing\n");
388 * HACK: until fixed.c regulator is usable,
389 * we don't require a main regulator
392 if (host->id == OMAP_MMC1_DEVID) {
398 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
400 /* Allow an aux regulator */
401 reg = regulator_get(host->dev, "vmmc_aux");
402 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
405 * UGLY HACK: workaround regulator framework bugs.
406 * When the bootloader leaves a supply active, it's
407 * initialized with zero usecount ... and we can't
408 * disable it without first enabling it. Until the
409 * framework is fixed, we need a workaround like this
410 * (which is safe for MMC, but not in general).
412 if (regulator_is_enabled(host->vcc) > 0) {
413 regulator_enable(host->vcc);
414 regulator_disable(host->vcc);
417 if (regulator_is_enabled(reg) > 0) {
418 regulator_enable(reg);
419 regulator_disable(reg);
427 mmc_slot(host).set_power = NULL;
428 mmc_slot(host).set_sleep = NULL;
432 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
434 regulator_put(host->vcc);
435 regulator_put(host->vcc_aux);
436 mmc_slot(host).set_power = NULL;
437 mmc_slot(host).set_sleep = NULL;
440 static inline int omap_hsmmc_have_reg(void)
447 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
452 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
456 static inline int omap_hsmmc_have_reg(void)
463 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
467 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
468 pdata->suspend = omap_hsmmc_suspend_cdirq;
469 pdata->resume = omap_hsmmc_resume_cdirq;
470 if (pdata->slots[0].cover)
471 pdata->slots[0].get_cover_state =
472 omap_hsmmc_get_cover_state;
474 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
475 pdata->slots[0].card_detect_irq =
476 gpio_to_irq(pdata->slots[0].switch_pin);
477 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
480 ret = gpio_direction_input(pdata->slots[0].switch_pin);
484 pdata->slots[0].switch_pin = -EINVAL;
486 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
487 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
488 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
491 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
495 pdata->slots[0].gpio_wp = -EINVAL;
500 gpio_free(pdata->slots[0].gpio_wp);
502 if (gpio_is_valid(pdata->slots[0].switch_pin))
504 gpio_free(pdata->slots[0].switch_pin);
508 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
510 if (gpio_is_valid(pdata->slots[0].gpio_wp))
511 gpio_free(pdata->slots[0].gpio_wp);
512 if (gpio_is_valid(pdata->slots[0].switch_pin))
513 gpio_free(pdata->slots[0].switch_pin);
517 * Stop clock to the card
519 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
521 OMAP_HSMMC_WRITE(host->base, SYSCTL,
522 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
523 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
524 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
530 * Restore the MMC host context, if it was lost as result of a
531 * power state change.
533 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
535 struct mmc_ios *ios = &host->mmc->ios;
536 struct omap_mmc_platform_data *pdata = host->pdata;
537 int context_loss = 0;
540 unsigned long timeout;
542 if (pdata->get_context_loss_count) {
543 context_loss = pdata->get_context_loss_count(host->dev);
544 if (context_loss < 0)
548 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
549 context_loss == host->context_loss ? "not " : "");
550 if (host->context_loss == context_loss)
553 /* Wait for hardware reset */
554 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
555 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
556 && time_before(jiffies, timeout))
559 /* Do software reset */
560 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
561 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
562 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
563 && time_before(jiffies, timeout))
566 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
567 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
569 if (host->id == OMAP_MMC1_DEVID) {
570 if (host->power_mode != MMC_POWER_OFF &&
571 (1 << ios->vdd) <= MMC_VDD_23_24)
581 OMAP_HSMMC_WRITE(host->base, HCTL,
582 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
584 OMAP_HSMMC_WRITE(host->base, CAPA,
585 OMAP_HSMMC_READ(host->base, CAPA) | capa);
587 OMAP_HSMMC_WRITE(host->base, HCTL,
588 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
590 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
591 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
592 && time_before(jiffies, timeout))
595 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
596 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
597 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
599 /* Do not initialize card-specific things if the power is off */
600 if (host->power_mode == MMC_POWER_OFF)
603 con = OMAP_HSMMC_READ(host->base, CON);
604 switch (ios->bus_width) {
605 case MMC_BUS_WIDTH_8:
606 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
608 case MMC_BUS_WIDTH_4:
609 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
610 OMAP_HSMMC_WRITE(host->base, HCTL,
611 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
613 case MMC_BUS_WIDTH_1:
614 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
615 OMAP_HSMMC_WRITE(host->base, HCTL,
616 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
621 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
625 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
632 OMAP_HSMMC_WRITE(host->base, SYSCTL,
633 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
634 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
635 OMAP_HSMMC_WRITE(host->base, SYSCTL,
636 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
638 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
639 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
640 && time_before(jiffies, timeout))
643 OMAP_HSMMC_WRITE(host->base, SYSCTL,
644 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
646 con = OMAP_HSMMC_READ(host->base, CON);
647 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
648 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
650 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
652 host->context_loss = context_loss;
654 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
659 * Save the MMC host context (store the number of power state changes so far).
661 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
663 struct omap_mmc_platform_data *pdata = host->pdata;
666 if (pdata->get_context_loss_count) {
667 context_loss = pdata->get_context_loss_count(host->dev);
668 if (context_loss < 0)
670 host->context_loss = context_loss;
676 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
681 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
688 * Send init stream sequence to card
689 * before sending IDLE command
691 static void send_init_stream(struct omap_hsmmc_host *host)
694 unsigned long timeout;
696 if (host->protect_card)
699 disable_irq(host->irq);
700 OMAP_HSMMC_WRITE(host->base, CON,
701 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
702 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
704 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
705 while ((reg != CC) && time_before(jiffies, timeout))
706 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
708 OMAP_HSMMC_WRITE(host->base, CON,
709 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
711 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
712 OMAP_HSMMC_READ(host->base, STAT);
714 enable_irq(host->irq);
718 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
722 if (mmc_slot(host).get_cover_state)
723 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
728 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
731 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
732 struct omap_hsmmc_host *host = mmc_priv(mmc);
734 return sprintf(buf, "%s\n",
735 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
738 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
741 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
744 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
745 struct omap_hsmmc_host *host = mmc_priv(mmc);
747 return sprintf(buf, "%s\n", mmc_slot(host).name);
750 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
753 * Configure the response type and send the cmd.
756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
757 struct mmc_data *data)
759 int cmdreg = 0, resptype = 0, cmdtype = 0;
761 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
762 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
766 * Clear status bits and enable interrupts
768 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
769 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
772 OMAP_HSMMC_WRITE(host->base, IE,
773 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
775 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
777 host->response_busy = 0;
778 if (cmd->flags & MMC_RSP_PRESENT) {
779 if (cmd->flags & MMC_RSP_136)
781 else if (cmd->flags & MMC_RSP_BUSY) {
783 host->response_busy = 1;
789 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
790 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
791 * a val of 0x3, rest 0x0.
793 if (cmd == host->mrq->stop)
796 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
799 cmdreg |= DP_SELECT | MSBS | BCE;
800 if (data->flags & MMC_DATA_READ)
810 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
811 * by the interrupt handler, otherwise (i.e. for a new request) it is
815 spin_unlock_irqrestore(&host->irq_lock, host->flags);
817 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
818 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
822 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
824 if (data->flags & MMC_DATA_WRITE)
825 return DMA_TO_DEVICE;
827 return DMA_FROM_DEVICE;
831 * Notify the transfer complete to MMC core
834 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
837 struct mmc_request *mrq = host->mrq;
839 /* TC before CC from CMD6 - don't know why, but it happens */
840 if (host->cmd && host->cmd->opcode == 6 &&
841 host->response_busy) {
842 host->response_busy = 0;
847 mmc_request_done(host->mmc, mrq);
853 if (host->use_dma && host->dma_ch != -1)
854 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
855 omap_hsmmc_get_dma_dir(host, data));
858 data->bytes_xfered += data->blocks * (data->blksz);
860 data->bytes_xfered = 0;
864 mmc_request_done(host->mmc, data->mrq);
867 omap_hsmmc_start_command(host, data->stop, NULL);
871 * Notify the core about command completion
874 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
878 if (cmd->flags & MMC_RSP_PRESENT) {
879 if (cmd->flags & MMC_RSP_136) {
880 /* response type 2 */
881 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
882 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
883 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
884 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
886 /* response types 1, 1b, 3, 4, 5, 6 */
887 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
890 if ((host->data == NULL && !host->response_busy) || cmd->error) {
892 mmc_request_done(host->mmc, cmd->mrq);
897 * DMA clean up for command errors
899 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
901 host->data->error = errno;
903 if (host->use_dma && host->dma_ch != -1) {
904 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
905 omap_hsmmc_get_dma_dir(host, host->data));
906 omap_free_dma(host->dma_ch);
914 * Readable error output
916 #ifdef CONFIG_MMC_DEBUG
917 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
919 /* --- means reserved bit without definition at documentation */
920 static const char *omap_hsmmc_status_bits[] = {
921 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
922 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
923 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
924 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
930 len = sprintf(buf, "MMC IRQ 0x%x :", status);
933 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
934 if (status & (1 << i)) {
935 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
939 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
941 #endif /* CONFIG_MMC_DEBUG */
944 * MMC controller internal state machines reset
946 * Used to reset command or data internal state machines, using respectively
947 * SRC or SRD bit of SYSCTL register
948 * Can be called from interrupt context
950 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
954 unsigned long limit = (loops_per_jiffy *
955 msecs_to_jiffies(MMC_TIMEOUT_MS));
957 OMAP_HSMMC_WRITE(host->base, SYSCTL,
958 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
960 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
964 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
965 dev_err(mmc_dev(host->mmc),
966 "Timeout waiting on controller reset in %s\n",
971 * MMC controller IRQ handler
973 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
975 struct omap_hsmmc_host *host = dev_id;
976 struct mmc_data *data;
977 int end_cmd = 0, end_trans = 0, status;
979 spin_lock(&host->irq_lock);
981 if (host->mrq == NULL) {
982 OMAP_HSMMC_WRITE(host->base, STAT,
983 OMAP_HSMMC_READ(host->base, STAT));
984 /* Flush posted write */
985 OMAP_HSMMC_READ(host->base, STAT);
986 spin_unlock(&host->irq_lock);
991 status = OMAP_HSMMC_READ(host->base, STAT);
992 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
995 #ifdef CONFIG_MMC_DEBUG
996 omap_hsmmc_report_irq(host, status);
998 if ((status & CMD_TIMEOUT) ||
999 (status & CMD_CRC)) {
1001 if (status & CMD_TIMEOUT) {
1002 omap_hsmmc_reset_controller_fsm(host,
1004 host->cmd->error = -ETIMEDOUT;
1006 host->cmd->error = -EILSEQ;
1010 if (host->data || host->response_busy) {
1012 omap_hsmmc_dma_cleanup(host,
1014 host->response_busy = 0;
1015 omap_hsmmc_reset_controller_fsm(host, SRD);
1018 if ((status & DATA_TIMEOUT) ||
1019 (status & DATA_CRC)) {
1020 if (host->data || host->response_busy) {
1021 int err = (status & DATA_TIMEOUT) ?
1022 -ETIMEDOUT : -EILSEQ;
1025 omap_hsmmc_dma_cleanup(host, err);
1027 host->mrq->cmd->error = err;
1028 host->response_busy = 0;
1029 omap_hsmmc_reset_controller_fsm(host, SRD);
1033 if (status & CARD_ERR) {
1034 dev_dbg(mmc_dev(host->mmc),
1035 "Ignoring card err CMD%d\n", host->cmd->opcode);
1043 OMAP_HSMMC_WRITE(host->base, STAT, status);
1044 /* Flush posted write */
1045 OMAP_HSMMC_READ(host->base, STAT);
1047 if (end_cmd || ((status & CC) && host->cmd))
1048 omap_hsmmc_cmd_done(host, host->cmd);
1049 if ((end_trans || (status & TC)) && host->mrq)
1050 omap_hsmmc_xfer_done(host, data);
1052 spin_unlock(&host->irq_lock);
1057 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1061 OMAP_HSMMC_WRITE(host->base, HCTL,
1062 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1063 for (i = 0; i < loops_per_jiffy; i++) {
1064 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1071 * Switch MMC interface voltage ... only relevant for MMC1.
1073 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1074 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1075 * Some chips, like eMMC ones, use internal transceivers.
1077 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1082 /* Disable the clocks */
1083 clk_disable(host->fclk);
1084 clk_disable(host->iclk);
1085 if (host->got_dbclk)
1086 clk_disable(host->dbclk);
1088 /* Turn the power off */
1089 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1091 /* Turn the power ON with given VDD 1.8 or 3.0v */
1093 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1095 clk_enable(host->iclk);
1096 clk_enable(host->fclk);
1097 if (host->got_dbclk)
1098 clk_enable(host->dbclk);
1103 OMAP_HSMMC_WRITE(host->base, HCTL,
1104 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1105 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1108 * If a MMC dual voltage card is detected, the set_ios fn calls
1109 * this fn with VDD bit set for 1.8V. Upon card removal from the
1110 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1112 * Cope with a bit of slop in the range ... per data sheets:
1113 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1114 * but recommended values are 1.71V to 1.89V
1115 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1116 * but recommended values are 2.7V to 3.3V
1118 * Board setup code shouldn't permit anything very out-of-range.
1119 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1120 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1122 if ((1 << vdd) <= MMC_VDD_23_24)
1127 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1128 set_sd_bus_power(host);
1132 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1136 /* Protect the card while the cover is open */
1137 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1139 if (!mmc_slot(host).get_cover_state)
1142 host->reqs_blocked = 0;
1143 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1144 if (host->protect_card) {
1145 printk(KERN_INFO "%s: cover is closed, "
1146 "card is now accessible\n",
1147 mmc_hostname(host->mmc));
1148 host->protect_card = 0;
1151 if (!host->protect_card) {
1152 printk(KERN_INFO "%s: cover is open, "
1153 "card is now inaccessible\n",
1154 mmc_hostname(host->mmc));
1155 host->protect_card = 1;
1161 * Work Item to notify the core about card insertion/removal
1163 static void omap_hsmmc_detect(struct work_struct *work)
1165 struct omap_hsmmc_host *host =
1166 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1167 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1170 if (host->suspended)
1173 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1175 if (slot->card_detect)
1176 carddetect = slot->card_detect(host->dev, host->slot_id);
1178 omap_hsmmc_protect_card(host);
1179 carddetect = -ENOSYS;
1183 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1185 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1189 * ISR for handling card insertion and removal
1191 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1193 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1195 if (host->suspended)
1197 schedule_work(&host->mmc_carddetect_work);
1202 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1203 struct mmc_data *data)
1207 if (data->flags & MMC_DATA_WRITE)
1208 sync_dev = host->dma_line_tx;
1210 sync_dev = host->dma_line_rx;
1214 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1215 struct mmc_data *data,
1216 struct scatterlist *sgl)
1218 int blksz, nblk, dma_ch;
1220 dma_ch = host->dma_ch;
1221 if (data->flags & MMC_DATA_WRITE) {
1222 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1223 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1224 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1225 sg_dma_address(sgl), 0, 0);
1227 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1228 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1229 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1230 sg_dma_address(sgl), 0, 0);
1233 blksz = host->data->blksz;
1234 nblk = sg_dma_len(sgl) / blksz;
1236 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1237 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1238 omap_hsmmc_get_dma_sync_dev(host, data),
1239 !(data->flags & MMC_DATA_WRITE));
1241 omap_start_dma(dma_ch);
1245 * DMA call back function
1247 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
1249 struct omap_hsmmc_host *host = data;
1251 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1252 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1254 if (host->dma_ch < 0)
1258 if (host->dma_sg_idx < host->dma_len) {
1259 /* Fire up the next transfer. */
1260 omap_hsmmc_config_dma_params(host, host->data,
1261 host->data->sg + host->dma_sg_idx);
1265 omap_free_dma(host->dma_ch);
1268 * DMA Callback: run in interrupt context.
1269 * mutex_unlock will throw a kernel warning if used.
1275 * Routine to configure and start DMA for the MMC card
1277 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1278 struct mmc_request *req)
1280 int dma_ch = 0, ret = 0, err = 1, i;
1281 struct mmc_data *data = req->data;
1283 /* Sanity check: all the SG entries must be aligned by block size. */
1284 for (i = 0; i < data->sg_len; i++) {
1285 struct scatterlist *sgl;
1288 if (sgl->length % data->blksz)
1291 if ((data->blksz % 4) != 0)
1292 /* REVISIT: The MMC buffer increments only when MSB is written.
1293 * Return error for blksz which is non multiple of four.
1298 * If for some reason the DMA transfer is still active,
1299 * we wait for timeout period and free the dma
1301 if (host->dma_ch != -1) {
1302 set_current_state(TASK_UNINTERRUPTIBLE);
1303 schedule_timeout(100);
1304 if (down_trylock(&host->sem)) {
1305 omap_free_dma(host->dma_ch);
1311 if (down_trylock(&host->sem))
1315 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1316 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1318 dev_err(mmc_dev(host->mmc),
1319 "%s: omap_request_dma() failed with %d\n",
1320 mmc_hostname(host->mmc), ret);
1324 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1325 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1326 host->dma_ch = dma_ch;
1327 host->dma_sg_idx = 0;
1329 omap_hsmmc_config_dma_params(host, data, data->sg);
1334 static void set_data_timeout(struct omap_hsmmc_host *host,
1335 unsigned int timeout_ns,
1336 unsigned int timeout_clks)
1338 unsigned int timeout, cycle_ns;
1339 uint32_t reg, clkd, dto = 0;
1341 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1342 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1346 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1347 timeout = timeout_ns / cycle_ns;
1348 timeout += timeout_clks;
1350 while ((timeout & 0x80000000) == 0) {
1367 reg |= dto << DTO_SHIFT;
1368 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1372 * Configure block length for MMC/SD cards and initiate the transfer.
1375 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1378 host->data = req->data;
1380 if (req->data == NULL) {
1381 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1383 * Set an arbitrary 100ms data timeout for commands with
1386 if (req->cmd->flags & MMC_RSP_BUSY)
1387 set_data_timeout(host, 100000000U, 0);
1391 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1392 | (req->data->blocks << 16));
1393 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1395 if (host->use_dma) {
1396 ret = omap_hsmmc_start_dma_transfer(host, req);
1398 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1406 * Request function. for read/write operation
1408 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1410 struct omap_hsmmc_host *host = mmc_priv(mmc);
1414 * Prevent races with the interrupt handler because of unexpected
1415 * interrupts, but not if we are already in interrupt context i.e.
1418 if (!in_interrupt()) {
1419 spin_lock_irqsave(&host->irq_lock, host->flags);
1421 * Protect the card from I/O if there is a possibility
1422 * it can be removed.
1424 if (host->protect_card) {
1425 if (host->reqs_blocked < 3) {
1427 * Ensure the controller is left in a consistent
1428 * state by resetting the command and data state
1431 omap_hsmmc_reset_controller_fsm(host, SRD);
1432 omap_hsmmc_reset_controller_fsm(host, SRC);
1433 host->reqs_blocked += 1;
1435 req->cmd->error = -EBADF;
1437 req->data->error = -EBADF;
1438 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1439 mmc_request_done(mmc, req);
1441 } else if (host->reqs_blocked)
1442 host->reqs_blocked = 0;
1444 WARN_ON(host->mrq != NULL);
1446 err = omap_hsmmc_prepare_data(host, req);
1448 req->cmd->error = err;
1450 req->data->error = err;
1452 if (!in_interrupt())
1453 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1454 mmc_request_done(mmc, req);
1458 omap_hsmmc_start_command(host, req->cmd, req->data);
1461 /* Routine to configure clock values. Exposed API to core */
1462 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1464 struct omap_hsmmc_host *host = mmc_priv(mmc);
1466 unsigned long regval;
1467 unsigned long timeout;
1469 int do_send_init_stream = 0;
1471 mmc_host_enable(host->mmc);
1473 if (ios->power_mode != host->power_mode) {
1474 switch (ios->power_mode) {
1476 mmc_slot(host).set_power(host->dev, host->slot_id,
1481 mmc_slot(host).set_power(host->dev, host->slot_id,
1483 host->vdd = ios->vdd;
1486 do_send_init_stream = 1;
1489 host->power_mode = ios->power_mode;
1492 /* FIXME: set registers based only on changes to ios */
1494 con = OMAP_HSMMC_READ(host->base, CON);
1495 switch (mmc->ios.bus_width) {
1496 case MMC_BUS_WIDTH_8:
1497 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1499 case MMC_BUS_WIDTH_4:
1500 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1501 OMAP_HSMMC_WRITE(host->base, HCTL,
1502 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1504 case MMC_BUS_WIDTH_1:
1505 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1506 OMAP_HSMMC_WRITE(host->base, HCTL,
1507 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1511 if (host->id == OMAP_MMC1_DEVID) {
1512 /* Only MMC1 can interface at 3V without some flavor
1513 * of external transceiver; but they all handle 1.8V.
1515 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1516 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1518 * The mmc_select_voltage fn of the core does
1519 * not seem to set the power_mode to
1520 * MMC_POWER_UP upon recalculating the voltage.
1523 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1524 dev_dbg(mmc_dev(host->mmc),
1525 "Switch operation failed\n");
1530 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1534 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1540 omap_hsmmc_stop_clock(host);
1541 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1542 regval = regval & ~(CLKD_MASK);
1543 regval = regval | (dsor << 6) | (DTO << 16);
1544 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1545 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1546 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1548 /* Wait till the ICS bit is set */
1549 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1550 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1551 && time_before(jiffies, timeout))
1554 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1555 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1557 if (do_send_init_stream)
1558 send_init_stream(host);
1560 con = OMAP_HSMMC_READ(host->base, CON);
1561 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1562 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1564 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1566 if (host->power_mode == MMC_POWER_OFF)
1567 mmc_host_disable(host->mmc);
1569 mmc_host_lazy_disable(host->mmc);
1572 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1574 struct omap_hsmmc_host *host = mmc_priv(mmc);
1576 if (!mmc_slot(host).card_detect)
1578 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1581 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1583 struct omap_hsmmc_host *host = mmc_priv(mmc);
1585 if (!mmc_slot(host).get_ro)
1587 return mmc_slot(host).get_ro(host->dev, 0);
1590 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1592 u32 hctl, capa, value;
1594 /* Only MMC1 supports 3.0V */
1595 if (host->id == OMAP_MMC1_DEVID) {
1603 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1604 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1606 value = OMAP_HSMMC_READ(host->base, CAPA);
1607 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1609 /* Set the controller to AUTO IDLE mode */
1610 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1611 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1613 /* Set SD bus power bit */
1614 set_sd_bus_power(host);
1618 * Dynamic power saving handling, FSM:
1619 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1621 * |______________________|______________________|
1623 * ENABLED: mmc host is fully functional
1624 * DISABLED: fclk is off
1625 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1626 * REGSLEEP: fclk is off, voltage regulator is asleep
1627 * OFF: fclk is off, voltage regulator is off
1629 * Transition handlers return the timeout for the next state transition
1630 * or negative error.
1633 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1635 /* Handler for [ENABLED -> DISABLED] transition */
1636 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1638 omap_hsmmc_context_save(host);
1639 clk_disable(host->fclk);
1640 host->dpm_state = DISABLED;
1642 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1644 if (host->power_mode == MMC_POWER_OFF)
1647 return OMAP_MMC_SLEEP_TIMEOUT;
1650 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1651 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1655 if (!mmc_try_claim_host(host->mmc))
1658 clk_enable(host->fclk);
1659 omap_hsmmc_context_restore(host);
1660 if (mmc_card_can_sleep(host->mmc)) {
1661 err = mmc_card_sleep(host->mmc);
1663 clk_disable(host->fclk);
1664 mmc_release_host(host->mmc);
1667 new_state = CARDSLEEP;
1669 new_state = REGSLEEP;
1671 if (mmc_slot(host).set_sleep)
1672 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1673 new_state == CARDSLEEP);
1674 /* FIXME: turn off bus power and perhaps interrupts too */
1675 clk_disable(host->fclk);
1676 host->dpm_state = new_state;
1678 mmc_release_host(host->mmc);
1680 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1681 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1683 if (mmc_slot(host).no_off)
1686 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1687 mmc_slot(host).card_detect ||
1688 (mmc_slot(host).get_cover_state &&
1689 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1690 return OMAP_MMC_OFF_TIMEOUT;
1695 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1696 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1698 if (!mmc_try_claim_host(host->mmc))
1701 if (mmc_slot(host).no_off)
1704 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1705 mmc_slot(host).card_detect ||
1706 (mmc_slot(host).get_cover_state &&
1707 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1708 mmc_release_host(host->mmc);
1712 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1714 host->power_mode = MMC_POWER_OFF;
1716 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1717 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1719 host->dpm_state = OFF;
1721 mmc_release_host(host->mmc);
1726 /* Handler for [DISABLED -> ENABLED] transition */
1727 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1731 err = clk_enable(host->fclk);
1735 omap_hsmmc_context_restore(host);
1736 host->dpm_state = ENABLED;
1738 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1743 /* Handler for [SLEEP -> ENABLED] transition */
1744 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1746 if (!mmc_try_claim_host(host->mmc))
1749 clk_enable(host->fclk);
1750 omap_hsmmc_context_restore(host);
1751 if (mmc_slot(host).set_sleep)
1752 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1753 host->vdd, host->dpm_state == CARDSLEEP);
1754 if (mmc_card_can_sleep(host->mmc))
1755 mmc_card_awake(host->mmc);
1757 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1758 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1760 host->dpm_state = ENABLED;
1762 mmc_release_host(host->mmc);
1767 /* Handler for [OFF -> ENABLED] transition */
1768 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1770 clk_enable(host->fclk);
1772 omap_hsmmc_context_restore(host);
1773 omap_hsmmc_conf_bus_power(host);
1774 mmc_power_restore_host(host->mmc);
1776 host->dpm_state = ENABLED;
1778 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1784 * Bring MMC host to ENABLED from any other PM state.
1786 static int omap_hsmmc_enable(struct mmc_host *mmc)
1788 struct omap_hsmmc_host *host = mmc_priv(mmc);
1790 switch (host->dpm_state) {
1792 return omap_hsmmc_disabled_to_enabled(host);
1795 return omap_hsmmc_sleep_to_enabled(host);
1797 return omap_hsmmc_off_to_enabled(host);
1799 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1805 * Bring MMC host in PM state (one level deeper).
1807 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1809 struct omap_hsmmc_host *host = mmc_priv(mmc);
1811 switch (host->dpm_state) {
1815 delay = omap_hsmmc_enabled_to_disabled(host);
1816 if (lazy || delay < 0)
1821 return omap_hsmmc_disabled_to_sleep(host);
1824 return omap_hsmmc_sleep_to_off(host);
1826 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1831 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1833 struct omap_hsmmc_host *host = mmc_priv(mmc);
1836 err = clk_enable(host->fclk);
1839 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1840 omap_hsmmc_context_restore(host);
1844 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1846 struct omap_hsmmc_host *host = mmc_priv(mmc);
1848 omap_hsmmc_context_save(host);
1849 clk_disable(host->fclk);
1850 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1854 static const struct mmc_host_ops omap_hsmmc_ops = {
1855 .enable = omap_hsmmc_enable_fclk,
1856 .disable = omap_hsmmc_disable_fclk,
1857 .request = omap_hsmmc_request,
1858 .set_ios = omap_hsmmc_set_ios,
1859 .get_cd = omap_hsmmc_get_cd,
1860 .get_ro = omap_hsmmc_get_ro,
1861 /* NYET -- enable_sdio_irq */
1864 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1865 .enable = omap_hsmmc_enable,
1866 .disable = omap_hsmmc_disable,
1867 .request = omap_hsmmc_request,
1868 .set_ios = omap_hsmmc_set_ios,
1869 .get_cd = omap_hsmmc_get_cd,
1870 .get_ro = omap_hsmmc_get_ro,
1871 /* NYET -- enable_sdio_irq */
1874 #ifdef CONFIG_DEBUG_FS
1876 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1878 struct mmc_host *mmc = s->private;
1879 struct omap_hsmmc_host *host = mmc_priv(mmc);
1880 int context_loss = 0;
1882 if (host->pdata->get_context_loss_count)
1883 context_loss = host->pdata->get_context_loss_count(host->dev);
1885 seq_printf(s, "mmc%d:\n"
1888 " nesting_cnt:\t%d\n"
1889 " ctx_loss:\t%d:%d\n"
1891 mmc->index, mmc->enabled ? 1 : 0,
1892 host->dpm_state, mmc->nesting_cnt,
1893 host->context_loss, context_loss);
1895 if (host->suspended || host->dpm_state == OFF) {
1896 seq_printf(s, "host suspended, can't read registers\n");
1900 if (clk_enable(host->fclk) != 0) {
1901 seq_printf(s, "can't read the regs\n");
1905 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1906 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1907 seq_printf(s, "CON:\t\t0x%08x\n",
1908 OMAP_HSMMC_READ(host->base, CON));
1909 seq_printf(s, "HCTL:\t\t0x%08x\n",
1910 OMAP_HSMMC_READ(host->base, HCTL));
1911 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1912 OMAP_HSMMC_READ(host->base, SYSCTL));
1913 seq_printf(s, "IE:\t\t0x%08x\n",
1914 OMAP_HSMMC_READ(host->base, IE));
1915 seq_printf(s, "ISE:\t\t0x%08x\n",
1916 OMAP_HSMMC_READ(host->base, ISE));
1917 seq_printf(s, "CAPA:\t\t0x%08x\n",
1918 OMAP_HSMMC_READ(host->base, CAPA));
1920 clk_disable(host->fclk);
1925 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1927 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1930 static const struct file_operations mmc_regs_fops = {
1931 .open = omap_hsmmc_regs_open,
1933 .llseek = seq_lseek,
1934 .release = single_release,
1937 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1939 if (mmc->debugfs_root)
1940 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1941 mmc, &mmc_regs_fops);
1946 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1952 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1954 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1955 struct mmc_host *mmc;
1956 struct omap_hsmmc_host *host = NULL;
1957 struct resource *res;
1960 if (pdata == NULL) {
1961 dev_err(&pdev->dev, "Platform Data is missing\n");
1965 if (pdata->nr_slots == 0) {
1966 dev_err(&pdev->dev, "No Slots\n");
1970 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1971 irq = platform_get_irq(pdev, 0);
1972 if (res == NULL || irq < 0)
1975 res = request_mem_region(res->start, res->end - res->start + 1,
1980 ret = omap_hsmmc_gpio_init(pdata);
1984 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1990 host = mmc_priv(mmc);
1992 host->pdata = pdata;
1993 host->dev = &pdev->dev;
1995 host->dev->dma_mask = &pdata->dma_mask;
1998 host->id = pdev->id;
2000 host->mapbase = res->start;
2001 host->base = ioremap(host->mapbase, SZ_4K);
2002 host->power_mode = MMC_POWER_OFF;
2004 platform_set_drvdata(pdev, host);
2005 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2007 if (mmc_slot(host).power_saving)
2008 mmc->ops = &omap_hsmmc_ps_ops;
2010 mmc->ops = &omap_hsmmc_ops;
2013 * If regulator_disable can only put vcc_aux to sleep then there is
2016 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2017 mmc_slot(host).no_off = 1;
2019 mmc->f_min = 400000;
2020 mmc->f_max = 52000000;
2022 sema_init(&host->sem, 1);
2023 spin_lock_init(&host->irq_lock);
2025 host->iclk = clk_get(&pdev->dev, "ick");
2026 if (IS_ERR(host->iclk)) {
2027 ret = PTR_ERR(host->iclk);
2031 host->fclk = clk_get(&pdev->dev, "fck");
2032 if (IS_ERR(host->fclk)) {
2033 ret = PTR_ERR(host->fclk);
2035 clk_put(host->iclk);
2039 omap_hsmmc_context_save(host);
2041 mmc->caps |= MMC_CAP_DISABLE;
2042 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2043 /* we start off in DISABLED state */
2044 host->dpm_state = DISABLED;
2046 if (mmc_host_enable(host->mmc) != 0) {
2047 clk_put(host->iclk);
2048 clk_put(host->fclk);
2052 if (clk_enable(host->iclk) != 0) {
2053 mmc_host_disable(host->mmc);
2054 clk_put(host->iclk);
2055 clk_put(host->fclk);
2059 if (cpu_is_omap2430()) {
2060 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2062 * MMC can still work without debounce clock.
2064 if (IS_ERR(host->dbclk))
2065 dev_warn(mmc_dev(host->mmc),
2066 "Failed to get debounce clock\n");
2068 host->got_dbclk = 1;
2070 if (host->got_dbclk)
2071 if (clk_enable(host->dbclk) != 0)
2072 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2076 /* Since we do only SG emulation, we can have as many segs
2078 mmc->max_phys_segs = 1024;
2079 mmc->max_hw_segs = 1024;
2081 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2082 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2083 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2084 mmc->max_seg_size = mmc->max_req_size;
2086 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2087 MMC_CAP_WAIT_WHILE_BUSY;
2089 if (mmc_slot(host).wires >= 8)
2090 mmc->caps |= MMC_CAP_8_BIT_DATA;
2091 else if (mmc_slot(host).wires >= 4)
2092 mmc->caps |= MMC_CAP_4_BIT_DATA;
2094 if (mmc_slot(host).nonremovable)
2095 mmc->caps |= MMC_CAP_NONREMOVABLE;
2097 omap_hsmmc_conf_bus_power(host);
2099 /* Select DMA lines */
2101 case OMAP_MMC1_DEVID:
2102 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2103 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2105 case OMAP_MMC2_DEVID:
2106 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2107 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2109 case OMAP_MMC3_DEVID:
2110 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2111 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2113 case OMAP_MMC4_DEVID:
2114 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2115 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2117 case OMAP_MMC5_DEVID:
2118 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2119 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2122 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2126 /* Request IRQ for MMC operations */
2127 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2128 mmc_hostname(mmc), host);
2130 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2134 if (pdata->init != NULL) {
2135 if (pdata->init(&pdev->dev) != 0) {
2136 dev_dbg(mmc_dev(host->mmc),
2137 "Unable to configure MMC IRQs\n");
2138 goto err_irq_cd_init;
2142 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2143 ret = omap_hsmmc_reg_get(host);
2149 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2151 /* Request IRQ for card detect */
2152 if ((mmc_slot(host).card_detect_irq)) {
2153 ret = request_irq(mmc_slot(host).card_detect_irq,
2154 omap_hsmmc_cd_handler,
2155 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2157 mmc_hostname(mmc), host);
2159 dev_dbg(mmc_dev(host->mmc),
2160 "Unable to grab MMC CD IRQ\n");
2165 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
2166 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
2168 mmc_host_lazy_disable(host->mmc);
2170 omap_hsmmc_protect_card(host);
2174 if (mmc_slot(host).name != NULL) {
2175 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2179 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2180 ret = device_create_file(&mmc->class_dev,
2181 &dev_attr_cover_switch);
2186 omap_hsmmc_debugfs(mmc);
2191 mmc_remove_host(mmc);
2192 free_irq(mmc_slot(host).card_detect_irq, host);
2195 omap_hsmmc_reg_put(host);
2197 if (host->pdata->cleanup)
2198 host->pdata->cleanup(&pdev->dev);
2200 free_irq(host->irq, host);
2202 mmc_host_disable(host->mmc);
2203 clk_disable(host->iclk);
2204 clk_put(host->fclk);
2205 clk_put(host->iclk);
2206 if (host->got_dbclk) {
2207 clk_disable(host->dbclk);
2208 clk_put(host->dbclk);
2211 iounmap(host->base);
2212 platform_set_drvdata(pdev, NULL);
2215 omap_hsmmc_gpio_free(pdata);
2217 release_mem_region(res->start, res->end - res->start + 1);
2221 static int omap_hsmmc_remove(struct platform_device *pdev)
2223 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2224 struct resource *res;
2227 mmc_host_enable(host->mmc);
2228 mmc_remove_host(host->mmc);
2230 omap_hsmmc_reg_put(host);
2231 if (host->pdata->cleanup)
2232 host->pdata->cleanup(&pdev->dev);
2233 free_irq(host->irq, host);
2234 if (mmc_slot(host).card_detect_irq)
2235 free_irq(mmc_slot(host).card_detect_irq, host);
2236 flush_scheduled_work();
2238 mmc_host_disable(host->mmc);
2239 clk_disable(host->iclk);
2240 clk_put(host->fclk);
2241 clk_put(host->iclk);
2242 if (host->got_dbclk) {
2243 clk_disable(host->dbclk);
2244 clk_put(host->dbclk);
2247 mmc_free_host(host->mmc);
2248 iounmap(host->base);
2249 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2252 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2254 release_mem_region(res->start, res->end - res->start + 1);
2255 platform_set_drvdata(pdev, NULL);
2261 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
2264 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2266 if (host && host->suspended)
2270 host->suspended = 1;
2271 if (host->pdata->suspend) {
2272 ret = host->pdata->suspend(&pdev->dev,
2275 dev_dbg(mmc_dev(host->mmc),
2276 "Unable to handle MMC board"
2277 " level suspend\n");
2278 host->suspended = 0;
2282 cancel_work_sync(&host->mmc_carddetect_work);
2283 mmc_host_enable(host->mmc);
2284 ret = mmc_suspend_host(host->mmc, state);
2286 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2287 OMAP_HSMMC_WRITE(host->base, IE, 0);
2290 OMAP_HSMMC_WRITE(host->base, HCTL,
2291 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2292 mmc_host_disable(host->mmc);
2293 clk_disable(host->iclk);
2294 if (host->got_dbclk)
2295 clk_disable(host->dbclk);
2297 host->suspended = 0;
2298 if (host->pdata->resume) {
2299 ret = host->pdata->resume(&pdev->dev,
2302 dev_dbg(mmc_dev(host->mmc),
2303 "Unmask interrupt failed\n");
2305 mmc_host_disable(host->mmc);
2312 /* Routine to resume the MMC device */
2313 static int omap_hsmmc_resume(struct platform_device *pdev)
2316 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2318 if (host && !host->suspended)
2322 ret = clk_enable(host->iclk);
2326 if (mmc_host_enable(host->mmc) != 0) {
2327 clk_disable(host->iclk);
2331 if (host->got_dbclk)
2332 clk_enable(host->dbclk);
2334 omap_hsmmc_conf_bus_power(host);
2336 if (host->pdata->resume) {
2337 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2339 dev_dbg(mmc_dev(host->mmc),
2340 "Unmask interrupt failed\n");
2343 omap_hsmmc_protect_card(host);
2345 /* Notify the core to resume the host */
2346 ret = mmc_resume_host(host->mmc);
2348 host->suspended = 0;
2350 mmc_host_lazy_disable(host->mmc);
2356 dev_dbg(mmc_dev(host->mmc),
2357 "Failed to enable MMC clocks during resume\n");
2362 #define omap_hsmmc_suspend NULL
2363 #define omap_hsmmc_resume NULL
2366 static struct platform_driver omap_hsmmc_driver = {
2367 .remove = omap_hsmmc_remove,
2368 .suspend = omap_hsmmc_suspend,
2369 .resume = omap_hsmmc_resume,
2371 .name = DRIVER_NAME,
2372 .owner = THIS_MODULE,
2376 static int __init omap_hsmmc_init(void)
2378 /* Register the MMC driver */
2379 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2382 static void __exit omap_hsmmc_cleanup(void)
2384 /* Unregister MMC driver */
2385 platform_driver_unregister(&omap_hsmmc_driver);
2388 module_init(omap_hsmmc_init);
2389 module_exit(omap_hsmmc_cleanup);
2391 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2392 MODULE_LICENSE("GPL");
2393 MODULE_ALIAS("platform:" DRIVER_NAME);
2394 MODULE_AUTHOR("Texas Instruments Inc");