2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
37 #include <mach/hardware.h>
38 #include <plat/board.h>
42 /* OMAP HSMMC Host Controller Registers */
43 #define OMAP_HSMMC_SYSCONFIG 0x0010
44 #define OMAP_HSMMC_SYSSTATUS 0x0014
45 #define OMAP_HSMMC_CON 0x002C
46 #define OMAP_HSMMC_BLK 0x0104
47 #define OMAP_HSMMC_ARG 0x0108
48 #define OMAP_HSMMC_CMD 0x010C
49 #define OMAP_HSMMC_RSP10 0x0110
50 #define OMAP_HSMMC_RSP32 0x0114
51 #define OMAP_HSMMC_RSP54 0x0118
52 #define OMAP_HSMMC_RSP76 0x011C
53 #define OMAP_HSMMC_DATA 0x0120
54 #define OMAP_HSMMC_HCTL 0x0128
55 #define OMAP_HSMMC_SYSCTL 0x012C
56 #define OMAP_HSMMC_STAT 0x0130
57 #define OMAP_HSMMC_IE 0x0134
58 #define OMAP_HSMMC_ISE 0x0138
59 #define OMAP_HSMMC_CAPA 0x0140
61 #define VS18 (1 << 26)
62 #define VS30 (1 << 25)
63 #define SDVS18 (0x5 << 9)
64 #define SDVS30 (0x6 << 9)
65 #define SDVS33 (0x7 << 9)
66 #define SDVS_MASK 0x00000E00
67 #define SDVSCLR 0xFFFFF1FF
68 #define SDVSDET 0x00000400
75 #define CLKD_MASK 0x0000FFC0
77 #define DTO_MASK 0x000F0000
79 #define INT_EN_MASK 0x307F0033
80 #define BWR_ENABLE (1 << 4)
81 #define BRR_ENABLE (1 << 5)
82 #define DTO_ENABLE (1 << 20)
83 #define INIT_STREAM (1 << 1)
84 #define DP_SELECT (1 << 21)
89 #define FOUR_BIT (1 << 1)
95 #define CMD_TIMEOUT (1 << 16)
96 #define DATA_TIMEOUT (1 << 20)
97 #define CMD_CRC (1 << 17)
98 #define DATA_CRC (1 << 21)
99 #define CARD_ERR (1 << 28)
100 #define STAT_CLEAR 0xFFFFFFFF
101 #define INIT_STREAM_CMD 0x00000000
102 #define DUAL_VOLT_OCR_BIT 7
103 #define SRC (1 << 25)
104 #define SRD (1 << 26)
105 #define SOFTRESET (1 << 1)
106 #define RESETDONE (1 << 0)
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
113 #define OMAP_MMC1_DEVID 0
114 #define OMAP_MMC2_DEVID 1
115 #define OMAP_MMC3_DEVID 2
116 #define OMAP_MMC4_DEVID 3
117 #define OMAP_MMC5_DEVID 4
119 #define MMC_TIMEOUT_MS 20
120 #define OMAP_MMC_MASTER_CLOCK 96000000
121 #define DRIVER_NAME "mmci-omap-hs"
123 /* Timeouts for entering power saving states on inactivity, msec */
124 #define OMAP_MMC_DISABLED_TIMEOUT 100
125 #define OMAP_MMC_SLEEP_TIMEOUT 1000
126 #define OMAP_MMC_OFF_TIMEOUT 8000
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
136 * MMC Host controller read/write API's
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144 struct omap_hsmmc_host {
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
162 struct work_struct mmc_carddetect_work;
164 resource_size_t mapbase;
165 spinlock_t irq_lock; /* Prevent races with irq handler */
167 unsigned int dma_len;
168 unsigned int dma_sg_idx;
169 unsigned char bus_mode;
170 unsigned char power_mode;
176 int dma_line_tx, dma_line_rx;
188 struct omap_mmc_platform_data *pdata;
191 static int omap_hsmmc_card_detect(struct device *dev, int slot)
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
199 static int omap_hsmmc_get_wp(struct device *dev, int slot)
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
221 disable_irq(mmc->slots[0].card_detect_irq);
225 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
229 enable_irq(mmc->slots[0].card_detect_irq);
235 #define omap_hsmmc_suspend_cdirq NULL
236 #define omap_hsmmc_resume_cdirq NULL
240 #ifdef CONFIG_REGULATOR
242 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
253 ret = mmc_regulator_set_ocr(host->vcc, vdd);
255 ret = mmc_regulator_set_ocr(host->vcc, 0);
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
263 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
294 ret = mmc_regulator_set_ocr(host->vcc, vdd);
295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
299 ret = mmc_regulator_set_ocr(host->vcc, 0);
303 ret = regulator_disable(host->vcc_aux);
305 ret = mmc_regulator_set_ocr(host->vcc, 0);
308 if (mmc_slot(host).after_set_reg)
309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
314 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
315 int vdd, int cardsleep)
317 struct omap_hsmmc_host *host =
318 platform_get_drvdata(to_platform_device(dev));
319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
321 return regulator_set_mode(host->vcc, mode);
324 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
325 int vdd, int cardsleep)
327 struct omap_hsmmc_host *host =
328 platform_get_drvdata(to_platform_device(dev));
332 * If we don't see a Vcc regulator, assume it's a fixed
333 * voltage always-on regulator.
338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
341 return regulator_set_mode(host->vcc, mode);
344 /* VCC can be turned off if card is asleep */
346 err = mmc_regulator_set_ocr(host->vcc, 0);
348 err = mmc_regulator_set_ocr(host->vcc, vdd);
350 err = regulator_set_mode(host->vcc, mode);
354 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
355 return regulator_set_mode(host->vcc_aux, mode);
358 return regulator_disable(host->vcc_aux);
360 return regulator_enable(host->vcc_aux);
363 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
365 struct regulator *reg;
369 case OMAP_MMC1_DEVID:
370 /* On-chip level shifting via PBIAS0/PBIAS1 */
371 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
372 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
374 case OMAP_MMC2_DEVID:
375 case OMAP_MMC3_DEVID:
376 /* Off-chip level shifting, or none */
377 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
378 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
381 pr_err("MMC%d configuration not supported!\n", host->id);
385 reg = regulator_get(host->dev, "vmmc");
387 dev_dbg(host->dev, "vmmc regulator missing\n");
389 * HACK: until fixed.c regulator is usable,
390 * we don't require a main regulator
393 if (host->id == OMAP_MMC1_DEVID) {
399 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
401 /* Allow an aux regulator */
402 reg = regulator_get(host->dev, "vmmc_aux");
403 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
406 * UGLY HACK: workaround regulator framework bugs.
407 * When the bootloader leaves a supply active, it's
408 * initialized with zero usecount ... and we can't
409 * disable it without first enabling it. Until the
410 * framework is fixed, we need a workaround like this
411 * (which is safe for MMC, but not in general).
413 if (regulator_is_enabled(host->vcc) > 0) {
414 regulator_enable(host->vcc);
415 regulator_disable(host->vcc);
418 if (regulator_is_enabled(reg) > 0) {
419 regulator_enable(reg);
420 regulator_disable(reg);
428 mmc_slot(host).set_power = NULL;
429 mmc_slot(host).set_sleep = NULL;
433 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
435 regulator_put(host->vcc);
436 regulator_put(host->vcc_aux);
437 mmc_slot(host).set_power = NULL;
438 mmc_slot(host).set_sleep = NULL;
441 static inline int omap_hsmmc_have_reg(void)
448 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
453 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
457 static inline int omap_hsmmc_have_reg(void)
464 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
468 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
469 pdata->suspend = omap_hsmmc_suspend_cdirq;
470 pdata->resume = omap_hsmmc_resume_cdirq;
471 if (pdata->slots[0].cover)
472 pdata->slots[0].get_cover_state =
473 omap_hsmmc_get_cover_state;
475 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
476 pdata->slots[0].card_detect_irq =
477 gpio_to_irq(pdata->slots[0].switch_pin);
478 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
481 ret = gpio_direction_input(pdata->slots[0].switch_pin);
485 pdata->slots[0].switch_pin = -EINVAL;
487 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
488 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
489 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
492 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
496 pdata->slots[0].gpio_wp = -EINVAL;
501 gpio_free(pdata->slots[0].gpio_wp);
503 if (gpio_is_valid(pdata->slots[0].switch_pin))
505 gpio_free(pdata->slots[0].switch_pin);
509 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
511 if (gpio_is_valid(pdata->slots[0].gpio_wp))
512 gpio_free(pdata->slots[0].gpio_wp);
513 if (gpio_is_valid(pdata->slots[0].switch_pin))
514 gpio_free(pdata->slots[0].switch_pin);
518 * Stop clock to the card
520 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
522 OMAP_HSMMC_WRITE(host->base, SYSCTL,
523 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
524 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
525 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
528 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
529 struct mmc_command *cmd)
531 unsigned int irq_mask;
534 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
536 irq_mask = INT_EN_MASK;
538 /* Disable timeout for erases */
539 if (cmd->opcode == MMC_ERASE)
540 irq_mask &= ~DTO_ENABLE;
542 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
543 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
544 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
547 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
549 OMAP_HSMMC_WRITE(host->base, ISE, 0);
550 OMAP_HSMMC_WRITE(host->base, IE, 0);
551 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
557 * Restore the MMC host context, if it was lost as result of a
558 * power state change.
560 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
562 struct mmc_ios *ios = &host->mmc->ios;
563 struct omap_mmc_platform_data *pdata = host->pdata;
564 int context_loss = 0;
567 unsigned long timeout;
569 if (pdata->get_context_loss_count) {
570 context_loss = pdata->get_context_loss_count(host->dev);
571 if (context_loss < 0)
575 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
576 context_loss == host->context_loss ? "not " : "");
577 if (host->context_loss == context_loss)
580 /* Wait for hardware reset */
581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
583 && time_before(jiffies, timeout))
586 /* Do software reset */
587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
588 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
589 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
590 && time_before(jiffies, timeout))
593 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
594 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
596 if (host->id == OMAP_MMC1_DEVID) {
597 if (host->power_mode != MMC_POWER_OFF &&
598 (1 << ios->vdd) <= MMC_VDD_23_24)
608 OMAP_HSMMC_WRITE(host->base, HCTL,
609 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
611 OMAP_HSMMC_WRITE(host->base, CAPA,
612 OMAP_HSMMC_READ(host->base, CAPA) | capa);
614 OMAP_HSMMC_WRITE(host->base, HCTL,
615 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
617 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
618 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
619 && time_before(jiffies, timeout))
622 omap_hsmmc_disable_irq(host);
624 /* Do not initialize card-specific things if the power is off */
625 if (host->power_mode == MMC_POWER_OFF)
628 con = OMAP_HSMMC_READ(host->base, CON);
629 switch (ios->bus_width) {
630 case MMC_BUS_WIDTH_8:
631 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
633 case MMC_BUS_WIDTH_4:
634 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
635 OMAP_HSMMC_WRITE(host->base, HCTL,
636 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
638 case MMC_BUS_WIDTH_1:
639 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
640 OMAP_HSMMC_WRITE(host->base, HCTL,
641 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
646 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
650 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
657 OMAP_HSMMC_WRITE(host->base, SYSCTL,
658 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
659 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
660 OMAP_HSMMC_WRITE(host->base, SYSCTL,
661 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
663 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
664 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
665 && time_before(jiffies, timeout))
668 OMAP_HSMMC_WRITE(host->base, SYSCTL,
669 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
671 con = OMAP_HSMMC_READ(host->base, CON);
672 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
673 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
675 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
677 host->context_loss = context_loss;
679 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
684 * Save the MMC host context (store the number of power state changes so far).
686 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
688 struct omap_mmc_platform_data *pdata = host->pdata;
691 if (pdata->get_context_loss_count) {
692 context_loss = pdata->get_context_loss_count(host->dev);
693 if (context_loss < 0)
695 host->context_loss = context_loss;
701 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
706 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
713 * Send init stream sequence to card
714 * before sending IDLE command
716 static void send_init_stream(struct omap_hsmmc_host *host)
719 unsigned long timeout;
721 if (host->protect_card)
724 disable_irq(host->irq);
726 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
727 OMAP_HSMMC_WRITE(host->base, CON,
728 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
729 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
731 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
732 while ((reg != CC) && time_before(jiffies, timeout))
733 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
735 OMAP_HSMMC_WRITE(host->base, CON,
736 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
738 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
739 OMAP_HSMMC_READ(host->base, STAT);
741 enable_irq(host->irq);
745 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
749 if (mmc_slot(host).get_cover_state)
750 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
755 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
758 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
759 struct omap_hsmmc_host *host = mmc_priv(mmc);
761 return sprintf(buf, "%s\n",
762 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
765 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
768 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
771 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
772 struct omap_hsmmc_host *host = mmc_priv(mmc);
774 return sprintf(buf, "%s\n", mmc_slot(host).name);
777 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
780 * Configure the response type and send the cmd.
783 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
784 struct mmc_data *data)
786 int cmdreg = 0, resptype = 0, cmdtype = 0;
788 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
789 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
792 omap_hsmmc_enable_irq(host, cmd);
794 host->response_busy = 0;
795 if (cmd->flags & MMC_RSP_PRESENT) {
796 if (cmd->flags & MMC_RSP_136)
798 else if (cmd->flags & MMC_RSP_BUSY) {
800 host->response_busy = 1;
806 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
807 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
808 * a val of 0x3, rest 0x0.
810 if (cmd == host->mrq->stop)
813 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
816 cmdreg |= DP_SELECT | MSBS | BCE;
817 if (data->flags & MMC_DATA_READ)
826 host->req_in_progress = 1;
828 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
829 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
833 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
835 if (data->flags & MMC_DATA_WRITE)
836 return DMA_TO_DEVICE;
838 return DMA_FROM_DEVICE;
841 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
845 spin_lock(&host->irq_lock);
846 host->req_in_progress = 0;
847 dma_ch = host->dma_ch;
848 spin_unlock(&host->irq_lock);
850 omap_hsmmc_disable_irq(host);
851 /* Do not complete the request if DMA is still in progress */
852 if (mrq->data && host->use_dma && dma_ch != -1)
855 mmc_request_done(host->mmc, mrq);
859 * Notify the transfer complete to MMC core
862 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
865 struct mmc_request *mrq = host->mrq;
867 /* TC before CC from CMD6 - don't know why, but it happens */
868 if (host->cmd && host->cmd->opcode == 6 &&
869 host->response_busy) {
870 host->response_busy = 0;
874 omap_hsmmc_request_done(host, mrq);
881 data->bytes_xfered += data->blocks * (data->blksz);
883 data->bytes_xfered = 0;
886 omap_hsmmc_request_done(host, data->mrq);
889 omap_hsmmc_start_command(host, data->stop, NULL);
893 * Notify the core about command completion
896 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
900 if (cmd->flags & MMC_RSP_PRESENT) {
901 if (cmd->flags & MMC_RSP_136) {
902 /* response type 2 */
903 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
904 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
905 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
906 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
908 /* response types 1, 1b, 3, 4, 5, 6 */
909 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
912 if ((host->data == NULL && !host->response_busy) || cmd->error)
913 omap_hsmmc_request_done(host, cmd->mrq);
917 * DMA clean up for command errors
919 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
923 host->data->error = errno;
925 spin_lock(&host->irq_lock);
926 dma_ch = host->dma_ch;
928 spin_unlock(&host->irq_lock);
930 if (host->use_dma && dma_ch != -1) {
931 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
932 omap_hsmmc_get_dma_dir(host, host->data));
933 omap_free_dma(dma_ch);
939 * Readable error output
941 #ifdef CONFIG_MMC_DEBUG
942 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
944 /* --- means reserved bit without definition at documentation */
945 static const char *omap_hsmmc_status_bits[] = {
946 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
947 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
948 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
949 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
955 len = sprintf(buf, "MMC IRQ 0x%x :", status);
958 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
959 if (status & (1 << i)) {
960 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
964 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
966 #endif /* CONFIG_MMC_DEBUG */
969 * MMC controller internal state machines reset
971 * Used to reset command or data internal state machines, using respectively
972 * SRC or SRD bit of SYSCTL register
973 * Can be called from interrupt context
975 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
979 unsigned long limit = (loops_per_jiffy *
980 msecs_to_jiffies(MMC_TIMEOUT_MS));
982 OMAP_HSMMC_WRITE(host->base, SYSCTL,
983 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
985 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
989 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
990 dev_err(mmc_dev(host->mmc),
991 "Timeout waiting on controller reset in %s\n",
995 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
997 struct mmc_data *data;
998 int end_cmd = 0, end_trans = 0;
1000 if (!host->req_in_progress) {
1002 OMAP_HSMMC_WRITE(host->base, STAT, status);
1003 /* Flush posted write */
1004 status = OMAP_HSMMC_READ(host->base, STAT);
1005 } while (status & INT_EN_MASK);
1010 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1013 #ifdef CONFIG_MMC_DEBUG
1014 omap_hsmmc_report_irq(host, status);
1016 if ((status & CMD_TIMEOUT) ||
1017 (status & CMD_CRC)) {
1019 if (status & CMD_TIMEOUT) {
1020 omap_hsmmc_reset_controller_fsm(host,
1022 host->cmd->error = -ETIMEDOUT;
1024 host->cmd->error = -EILSEQ;
1028 if (host->data || host->response_busy) {
1030 omap_hsmmc_dma_cleanup(host,
1032 host->response_busy = 0;
1033 omap_hsmmc_reset_controller_fsm(host, SRD);
1036 if ((status & DATA_TIMEOUT) ||
1037 (status & DATA_CRC)) {
1038 if (host->data || host->response_busy) {
1039 int err = (status & DATA_TIMEOUT) ?
1040 -ETIMEDOUT : -EILSEQ;
1043 omap_hsmmc_dma_cleanup(host, err);
1045 host->mrq->cmd->error = err;
1046 host->response_busy = 0;
1047 omap_hsmmc_reset_controller_fsm(host, SRD);
1051 if (status & CARD_ERR) {
1052 dev_dbg(mmc_dev(host->mmc),
1053 "Ignoring card err CMD%d\n", host->cmd->opcode);
1061 OMAP_HSMMC_WRITE(host->base, STAT, status);
1063 if (end_cmd || ((status & CC) && host->cmd))
1064 omap_hsmmc_cmd_done(host, host->cmd);
1065 if ((end_trans || (status & TC)) && host->mrq)
1066 omap_hsmmc_xfer_done(host, data);
1070 * MMC controller IRQ handler
1072 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1074 struct omap_hsmmc_host *host = dev_id;
1077 status = OMAP_HSMMC_READ(host->base, STAT);
1079 omap_hsmmc_do_irq(host, status);
1080 /* Flush posted write */
1081 status = OMAP_HSMMC_READ(host->base, STAT);
1082 } while (status & INT_EN_MASK);
1087 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1091 OMAP_HSMMC_WRITE(host->base, HCTL,
1092 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1093 for (i = 0; i < loops_per_jiffy; i++) {
1094 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1101 * Switch MMC interface voltage ... only relevant for MMC1.
1103 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1104 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1105 * Some chips, like eMMC ones, use internal transceivers.
1107 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1112 /* Disable the clocks */
1113 clk_disable(host->fclk);
1114 clk_disable(host->iclk);
1115 if (host->got_dbclk)
1116 clk_disable(host->dbclk);
1118 /* Turn the power off */
1119 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1121 /* Turn the power ON with given VDD 1.8 or 3.0v */
1123 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1125 clk_enable(host->iclk);
1126 clk_enable(host->fclk);
1127 if (host->got_dbclk)
1128 clk_enable(host->dbclk);
1133 OMAP_HSMMC_WRITE(host->base, HCTL,
1134 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1135 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1138 * If a MMC dual voltage card is detected, the set_ios fn calls
1139 * this fn with VDD bit set for 1.8V. Upon card removal from the
1140 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1142 * Cope with a bit of slop in the range ... per data sheets:
1143 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1144 * but recommended values are 1.71V to 1.89V
1145 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1146 * but recommended values are 2.7V to 3.3V
1148 * Board setup code shouldn't permit anything very out-of-range.
1149 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1150 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1152 if ((1 << vdd) <= MMC_VDD_23_24)
1157 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1158 set_sd_bus_power(host);
1162 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1166 /* Protect the card while the cover is open */
1167 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1169 if (!mmc_slot(host).get_cover_state)
1172 host->reqs_blocked = 0;
1173 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1174 if (host->protect_card) {
1175 printk(KERN_INFO "%s: cover is closed, "
1176 "card is now accessible\n",
1177 mmc_hostname(host->mmc));
1178 host->protect_card = 0;
1181 if (!host->protect_card) {
1182 printk(KERN_INFO "%s: cover is open, "
1183 "card is now inaccessible\n",
1184 mmc_hostname(host->mmc));
1185 host->protect_card = 1;
1191 * Work Item to notify the core about card insertion/removal
1193 static void omap_hsmmc_detect(struct work_struct *work)
1195 struct omap_hsmmc_host *host =
1196 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1197 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1200 if (host->suspended)
1203 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1205 if (slot->card_detect)
1206 carddetect = slot->card_detect(host->dev, host->slot_id);
1208 omap_hsmmc_protect_card(host);
1209 carddetect = -ENOSYS;
1213 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1215 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1219 * ISR for handling card insertion and removal
1221 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1223 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1225 if (host->suspended)
1227 schedule_work(&host->mmc_carddetect_work);
1232 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1233 struct mmc_data *data)
1237 if (data->flags & MMC_DATA_WRITE)
1238 sync_dev = host->dma_line_tx;
1240 sync_dev = host->dma_line_rx;
1244 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1245 struct mmc_data *data,
1246 struct scatterlist *sgl)
1248 int blksz, nblk, dma_ch;
1250 dma_ch = host->dma_ch;
1251 if (data->flags & MMC_DATA_WRITE) {
1252 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1253 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1254 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1255 sg_dma_address(sgl), 0, 0);
1257 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1258 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1259 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1260 sg_dma_address(sgl), 0, 0);
1263 blksz = host->data->blksz;
1264 nblk = sg_dma_len(sgl) / blksz;
1266 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1267 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1268 omap_hsmmc_get_dma_sync_dev(host, data),
1269 !(data->flags & MMC_DATA_WRITE));
1271 omap_start_dma(dma_ch);
1275 * DMA call back function
1277 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1279 struct omap_hsmmc_host *host = cb_data;
1280 struct mmc_data *data = host->mrq->data;
1281 int dma_ch, req_in_progress;
1283 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1284 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1289 spin_lock(&host->irq_lock);
1290 if (host->dma_ch < 0) {
1291 spin_unlock(&host->irq_lock);
1296 if (host->dma_sg_idx < host->dma_len) {
1297 /* Fire up the next transfer. */
1298 omap_hsmmc_config_dma_params(host, data,
1299 data->sg + host->dma_sg_idx);
1300 spin_unlock(&host->irq_lock);
1304 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1305 omap_hsmmc_get_dma_dir(host, data));
1307 req_in_progress = host->req_in_progress;
1308 dma_ch = host->dma_ch;
1310 spin_unlock(&host->irq_lock);
1312 omap_free_dma(dma_ch);
1314 /* If DMA has finished after TC, complete the request */
1315 if (!req_in_progress) {
1316 struct mmc_request *mrq = host->mrq;
1319 mmc_request_done(host->mmc, mrq);
1324 * Routine to configure and start DMA for the MMC card
1326 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1327 struct mmc_request *req)
1329 int dma_ch = 0, ret = 0, i;
1330 struct mmc_data *data = req->data;
1332 /* Sanity check: all the SG entries must be aligned by block size. */
1333 for (i = 0; i < data->sg_len; i++) {
1334 struct scatterlist *sgl;
1337 if (sgl->length % data->blksz)
1340 if ((data->blksz % 4) != 0)
1341 /* REVISIT: The MMC buffer increments only when MSB is written.
1342 * Return error for blksz which is non multiple of four.
1346 BUG_ON(host->dma_ch != -1);
1348 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1349 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1351 dev_err(mmc_dev(host->mmc),
1352 "%s: omap_request_dma() failed with %d\n",
1353 mmc_hostname(host->mmc), ret);
1357 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1358 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1359 host->dma_ch = dma_ch;
1360 host->dma_sg_idx = 0;
1362 omap_hsmmc_config_dma_params(host, data, data->sg);
1367 static void set_data_timeout(struct omap_hsmmc_host *host,
1368 unsigned int timeout_ns,
1369 unsigned int timeout_clks)
1371 unsigned int timeout, cycle_ns;
1372 uint32_t reg, clkd, dto = 0;
1374 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1375 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1379 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1380 timeout = timeout_ns / cycle_ns;
1381 timeout += timeout_clks;
1383 while ((timeout & 0x80000000) == 0) {
1400 reg |= dto << DTO_SHIFT;
1401 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1405 * Configure block length for MMC/SD cards and initiate the transfer.
1408 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1411 host->data = req->data;
1413 if (req->data == NULL) {
1414 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1416 * Set an arbitrary 100ms data timeout for commands with
1419 if (req->cmd->flags & MMC_RSP_BUSY)
1420 set_data_timeout(host, 100000000U, 0);
1424 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1425 | (req->data->blocks << 16));
1426 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1428 if (host->use_dma) {
1429 ret = omap_hsmmc_start_dma_transfer(host, req);
1431 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1439 * Request function. for read/write operation
1441 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1443 struct omap_hsmmc_host *host = mmc_priv(mmc);
1446 BUG_ON(host->req_in_progress);
1447 BUG_ON(host->dma_ch != -1);
1448 if (host->protect_card) {
1449 if (host->reqs_blocked < 3) {
1451 * Ensure the controller is left in a consistent
1452 * state by resetting the command and data state
1455 omap_hsmmc_reset_controller_fsm(host, SRD);
1456 omap_hsmmc_reset_controller_fsm(host, SRC);
1457 host->reqs_blocked += 1;
1459 req->cmd->error = -EBADF;
1461 req->data->error = -EBADF;
1462 req->cmd->retries = 0;
1463 mmc_request_done(mmc, req);
1465 } else if (host->reqs_blocked)
1466 host->reqs_blocked = 0;
1467 WARN_ON(host->mrq != NULL);
1469 err = omap_hsmmc_prepare_data(host, req);
1471 req->cmd->error = err;
1473 req->data->error = err;
1475 mmc_request_done(mmc, req);
1479 omap_hsmmc_start_command(host, req->cmd, req->data);
1482 /* Routine to configure clock values. Exposed API to core */
1483 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1485 struct omap_hsmmc_host *host = mmc_priv(mmc);
1487 unsigned long regval;
1488 unsigned long timeout;
1490 int do_send_init_stream = 0;
1492 mmc_host_enable(host->mmc);
1494 if (ios->power_mode != host->power_mode) {
1495 switch (ios->power_mode) {
1497 mmc_slot(host).set_power(host->dev, host->slot_id,
1502 mmc_slot(host).set_power(host->dev, host->slot_id,
1504 host->vdd = ios->vdd;
1507 do_send_init_stream = 1;
1510 host->power_mode = ios->power_mode;
1513 /* FIXME: set registers based only on changes to ios */
1515 con = OMAP_HSMMC_READ(host->base, CON);
1516 switch (mmc->ios.bus_width) {
1517 case MMC_BUS_WIDTH_8:
1518 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1520 case MMC_BUS_WIDTH_4:
1521 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1522 OMAP_HSMMC_WRITE(host->base, HCTL,
1523 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1525 case MMC_BUS_WIDTH_1:
1526 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1527 OMAP_HSMMC_WRITE(host->base, HCTL,
1528 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1532 if (host->id == OMAP_MMC1_DEVID) {
1533 /* Only MMC1 can interface at 3V without some flavor
1534 * of external transceiver; but they all handle 1.8V.
1536 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1537 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1539 * The mmc_select_voltage fn of the core does
1540 * not seem to set the power_mode to
1541 * MMC_POWER_UP upon recalculating the voltage.
1544 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1545 dev_dbg(mmc_dev(host->mmc),
1546 "Switch operation failed\n");
1551 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1555 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1561 omap_hsmmc_stop_clock(host);
1562 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1563 regval = regval & ~(CLKD_MASK);
1564 regval = regval | (dsor << 6) | (DTO << 16);
1565 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1566 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1567 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1569 /* Wait till the ICS bit is set */
1570 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1571 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1572 && time_before(jiffies, timeout))
1575 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1576 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1578 if (do_send_init_stream)
1579 send_init_stream(host);
1581 con = OMAP_HSMMC_READ(host->base, CON);
1582 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1583 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1585 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1587 if (host->power_mode == MMC_POWER_OFF)
1588 mmc_host_disable(host->mmc);
1590 mmc_host_lazy_disable(host->mmc);
1593 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1595 struct omap_hsmmc_host *host = mmc_priv(mmc);
1597 if (!mmc_slot(host).card_detect)
1599 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1602 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1604 struct omap_hsmmc_host *host = mmc_priv(mmc);
1606 if (!mmc_slot(host).get_ro)
1608 return mmc_slot(host).get_ro(host->dev, 0);
1611 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1613 struct omap_hsmmc_host *host = mmc_priv(mmc);
1615 if (mmc_slot(host).init_card)
1616 mmc_slot(host).init_card(card);
1619 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1621 u32 hctl, capa, value;
1623 /* Only MMC1 supports 3.0V */
1624 if (host->id == OMAP_MMC1_DEVID) {
1632 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1633 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1635 value = OMAP_HSMMC_READ(host->base, CAPA);
1636 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1638 /* Set the controller to AUTO IDLE mode */
1639 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1640 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1642 /* Set SD bus power bit */
1643 set_sd_bus_power(host);
1647 * Dynamic power saving handling, FSM:
1648 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1650 * |______________________|______________________|
1652 * ENABLED: mmc host is fully functional
1653 * DISABLED: fclk is off
1654 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1655 * REGSLEEP: fclk is off, voltage regulator is asleep
1656 * OFF: fclk is off, voltage regulator is off
1658 * Transition handlers return the timeout for the next state transition
1659 * or negative error.
1662 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1664 /* Handler for [ENABLED -> DISABLED] transition */
1665 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1667 omap_hsmmc_context_save(host);
1668 clk_disable(host->fclk);
1669 host->dpm_state = DISABLED;
1671 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1673 if (host->power_mode == MMC_POWER_OFF)
1676 return OMAP_MMC_SLEEP_TIMEOUT;
1679 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1680 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1684 if (!mmc_try_claim_host(host->mmc))
1687 clk_enable(host->fclk);
1688 omap_hsmmc_context_restore(host);
1689 if (mmc_card_can_sleep(host->mmc)) {
1690 err = mmc_card_sleep(host->mmc);
1692 clk_disable(host->fclk);
1693 mmc_release_host(host->mmc);
1696 new_state = CARDSLEEP;
1698 new_state = REGSLEEP;
1700 if (mmc_slot(host).set_sleep)
1701 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1702 new_state == CARDSLEEP);
1703 /* FIXME: turn off bus power and perhaps interrupts too */
1704 clk_disable(host->fclk);
1705 host->dpm_state = new_state;
1707 mmc_release_host(host->mmc);
1709 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1710 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1712 if (mmc_slot(host).no_off)
1715 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1716 mmc_slot(host).card_detect ||
1717 (mmc_slot(host).get_cover_state &&
1718 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1719 return OMAP_MMC_OFF_TIMEOUT;
1724 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1725 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1727 if (!mmc_try_claim_host(host->mmc))
1730 if (mmc_slot(host).no_off)
1733 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1734 mmc_slot(host).card_detect ||
1735 (mmc_slot(host).get_cover_state &&
1736 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1737 mmc_release_host(host->mmc);
1741 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1743 host->power_mode = MMC_POWER_OFF;
1745 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1746 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1748 host->dpm_state = OFF;
1750 mmc_release_host(host->mmc);
1755 /* Handler for [DISABLED -> ENABLED] transition */
1756 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1760 err = clk_enable(host->fclk);
1764 omap_hsmmc_context_restore(host);
1765 host->dpm_state = ENABLED;
1767 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1772 /* Handler for [SLEEP -> ENABLED] transition */
1773 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1775 if (!mmc_try_claim_host(host->mmc))
1778 clk_enable(host->fclk);
1779 omap_hsmmc_context_restore(host);
1780 if (mmc_slot(host).set_sleep)
1781 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1782 host->vdd, host->dpm_state == CARDSLEEP);
1783 if (mmc_card_can_sleep(host->mmc))
1784 mmc_card_awake(host->mmc);
1786 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1787 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1789 host->dpm_state = ENABLED;
1791 mmc_release_host(host->mmc);
1796 /* Handler for [OFF -> ENABLED] transition */
1797 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1799 clk_enable(host->fclk);
1801 omap_hsmmc_context_restore(host);
1802 omap_hsmmc_conf_bus_power(host);
1803 mmc_power_restore_host(host->mmc);
1805 host->dpm_state = ENABLED;
1807 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1813 * Bring MMC host to ENABLED from any other PM state.
1815 static int omap_hsmmc_enable(struct mmc_host *mmc)
1817 struct omap_hsmmc_host *host = mmc_priv(mmc);
1819 switch (host->dpm_state) {
1821 return omap_hsmmc_disabled_to_enabled(host);
1824 return omap_hsmmc_sleep_to_enabled(host);
1826 return omap_hsmmc_off_to_enabled(host);
1828 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1834 * Bring MMC host in PM state (one level deeper).
1836 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1838 struct omap_hsmmc_host *host = mmc_priv(mmc);
1840 switch (host->dpm_state) {
1844 delay = omap_hsmmc_enabled_to_disabled(host);
1845 if (lazy || delay < 0)
1850 return omap_hsmmc_disabled_to_sleep(host);
1853 return omap_hsmmc_sleep_to_off(host);
1855 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1860 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1862 struct omap_hsmmc_host *host = mmc_priv(mmc);
1865 err = clk_enable(host->fclk);
1868 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1869 omap_hsmmc_context_restore(host);
1873 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1875 struct omap_hsmmc_host *host = mmc_priv(mmc);
1877 omap_hsmmc_context_save(host);
1878 clk_disable(host->fclk);
1879 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1883 static const struct mmc_host_ops omap_hsmmc_ops = {
1884 .enable = omap_hsmmc_enable_fclk,
1885 .disable = omap_hsmmc_disable_fclk,
1886 .request = omap_hsmmc_request,
1887 .set_ios = omap_hsmmc_set_ios,
1888 .get_cd = omap_hsmmc_get_cd,
1889 .get_ro = omap_hsmmc_get_ro,
1890 .init_card = omap_hsmmc_init_card,
1891 /* NYET -- enable_sdio_irq */
1894 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1895 .enable = omap_hsmmc_enable,
1896 .disable = omap_hsmmc_disable,
1897 .request = omap_hsmmc_request,
1898 .set_ios = omap_hsmmc_set_ios,
1899 .get_cd = omap_hsmmc_get_cd,
1900 .get_ro = omap_hsmmc_get_ro,
1901 .init_card = omap_hsmmc_init_card,
1902 /* NYET -- enable_sdio_irq */
1905 #ifdef CONFIG_DEBUG_FS
1907 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1909 struct mmc_host *mmc = s->private;
1910 struct omap_hsmmc_host *host = mmc_priv(mmc);
1911 int context_loss = 0;
1913 if (host->pdata->get_context_loss_count)
1914 context_loss = host->pdata->get_context_loss_count(host->dev);
1916 seq_printf(s, "mmc%d:\n"
1919 " nesting_cnt:\t%d\n"
1920 " ctx_loss:\t%d:%d\n"
1922 mmc->index, mmc->enabled ? 1 : 0,
1923 host->dpm_state, mmc->nesting_cnt,
1924 host->context_loss, context_loss);
1926 if (host->suspended || host->dpm_state == OFF) {
1927 seq_printf(s, "host suspended, can't read registers\n");
1931 if (clk_enable(host->fclk) != 0) {
1932 seq_printf(s, "can't read the regs\n");
1936 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1937 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1938 seq_printf(s, "CON:\t\t0x%08x\n",
1939 OMAP_HSMMC_READ(host->base, CON));
1940 seq_printf(s, "HCTL:\t\t0x%08x\n",
1941 OMAP_HSMMC_READ(host->base, HCTL));
1942 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1943 OMAP_HSMMC_READ(host->base, SYSCTL));
1944 seq_printf(s, "IE:\t\t0x%08x\n",
1945 OMAP_HSMMC_READ(host->base, IE));
1946 seq_printf(s, "ISE:\t\t0x%08x\n",
1947 OMAP_HSMMC_READ(host->base, ISE));
1948 seq_printf(s, "CAPA:\t\t0x%08x\n",
1949 OMAP_HSMMC_READ(host->base, CAPA));
1951 clk_disable(host->fclk);
1956 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1958 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1961 static const struct file_operations mmc_regs_fops = {
1962 .open = omap_hsmmc_regs_open,
1964 .llseek = seq_lseek,
1965 .release = single_release,
1968 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1970 if (mmc->debugfs_root)
1971 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1972 mmc, &mmc_regs_fops);
1977 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1983 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1985 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1986 struct mmc_host *mmc;
1987 struct omap_hsmmc_host *host = NULL;
1988 struct resource *res;
1991 if (pdata == NULL) {
1992 dev_err(&pdev->dev, "Platform Data is missing\n");
1996 if (pdata->nr_slots == 0) {
1997 dev_err(&pdev->dev, "No Slots\n");
2001 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2002 irq = platform_get_irq(pdev, 0);
2003 if (res == NULL || irq < 0)
2006 res = request_mem_region(res->start, res->end - res->start + 1,
2011 ret = omap_hsmmc_gpio_init(pdata);
2015 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2021 host = mmc_priv(mmc);
2023 host->pdata = pdata;
2024 host->dev = &pdev->dev;
2026 host->dev->dma_mask = &pdata->dma_mask;
2029 host->id = pdev->id;
2031 host->mapbase = res->start;
2032 host->base = ioremap(host->mapbase, SZ_4K);
2033 host->power_mode = MMC_POWER_OFF;
2035 platform_set_drvdata(pdev, host);
2036 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2038 if (mmc_slot(host).power_saving)
2039 mmc->ops = &omap_hsmmc_ps_ops;
2041 mmc->ops = &omap_hsmmc_ops;
2044 * If regulator_disable can only put vcc_aux to sleep then there is
2047 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2048 mmc_slot(host).no_off = 1;
2050 mmc->f_min = 400000;
2051 mmc->f_max = 52000000;
2053 spin_lock_init(&host->irq_lock);
2055 host->iclk = clk_get(&pdev->dev, "ick");
2056 if (IS_ERR(host->iclk)) {
2057 ret = PTR_ERR(host->iclk);
2061 host->fclk = clk_get(&pdev->dev, "fck");
2062 if (IS_ERR(host->fclk)) {
2063 ret = PTR_ERR(host->fclk);
2065 clk_put(host->iclk);
2069 omap_hsmmc_context_save(host);
2071 mmc->caps |= MMC_CAP_DISABLE;
2072 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2073 /* we start off in DISABLED state */
2074 host->dpm_state = DISABLED;
2076 if (mmc_host_enable(host->mmc) != 0) {
2077 clk_put(host->iclk);
2078 clk_put(host->fclk);
2082 if (clk_enable(host->iclk) != 0) {
2083 mmc_host_disable(host->mmc);
2084 clk_put(host->iclk);
2085 clk_put(host->fclk);
2089 if (cpu_is_omap2430()) {
2090 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2092 * MMC can still work without debounce clock.
2094 if (IS_ERR(host->dbclk))
2095 dev_warn(mmc_dev(host->mmc),
2096 "Failed to get debounce clock\n");
2098 host->got_dbclk = 1;
2100 if (host->got_dbclk)
2101 if (clk_enable(host->dbclk) != 0)
2102 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2106 /* Since we do only SG emulation, we can have as many segs
2108 mmc->max_phys_segs = 1024;
2109 mmc->max_hw_segs = 1024;
2111 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2112 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2113 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2114 mmc->max_seg_size = mmc->max_req_size;
2116 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2117 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2119 switch (mmc_slot(host).wires) {
2121 mmc->caps |= MMC_CAP_8_BIT_DATA;
2124 mmc->caps |= MMC_CAP_4_BIT_DATA;
2127 /* Nothing to crib here */
2129 /* Assuming nothing was given by board, Core use's 1-Bit */
2132 /* Completely unexpected.. Core goes with 1-Bit Width */
2133 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!"
2134 "using 1 instead\n", mmc_slot(host).wires);
2137 if (mmc_slot(host).nonremovable)
2138 mmc->caps |= MMC_CAP_NONREMOVABLE;
2140 omap_hsmmc_conf_bus_power(host);
2142 /* Select DMA lines */
2144 case OMAP_MMC1_DEVID:
2145 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2146 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2148 case OMAP_MMC2_DEVID:
2149 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2150 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2152 case OMAP_MMC3_DEVID:
2153 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2154 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2156 case OMAP_MMC4_DEVID:
2157 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2158 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2160 case OMAP_MMC5_DEVID:
2161 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2162 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2165 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2169 /* Request IRQ for MMC operations */
2170 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2171 mmc_hostname(mmc), host);
2173 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2177 if (pdata->init != NULL) {
2178 if (pdata->init(&pdev->dev) != 0) {
2179 dev_dbg(mmc_dev(host->mmc),
2180 "Unable to configure MMC IRQs\n");
2181 goto err_irq_cd_init;
2185 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2186 ret = omap_hsmmc_reg_get(host);
2192 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2194 /* Request IRQ for card detect */
2195 if ((mmc_slot(host).card_detect_irq)) {
2196 ret = request_irq(mmc_slot(host).card_detect_irq,
2197 omap_hsmmc_cd_handler,
2198 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2200 mmc_hostname(mmc), host);
2202 dev_dbg(mmc_dev(host->mmc),
2203 "Unable to grab MMC CD IRQ\n");
2208 omap_hsmmc_disable_irq(host);
2210 mmc_host_lazy_disable(host->mmc);
2212 omap_hsmmc_protect_card(host);
2216 if (mmc_slot(host).name != NULL) {
2217 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2221 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2222 ret = device_create_file(&mmc->class_dev,
2223 &dev_attr_cover_switch);
2228 omap_hsmmc_debugfs(mmc);
2233 mmc_remove_host(mmc);
2234 free_irq(mmc_slot(host).card_detect_irq, host);
2237 omap_hsmmc_reg_put(host);
2239 if (host->pdata->cleanup)
2240 host->pdata->cleanup(&pdev->dev);
2242 free_irq(host->irq, host);
2244 mmc_host_disable(host->mmc);
2245 clk_disable(host->iclk);
2246 clk_put(host->fclk);
2247 clk_put(host->iclk);
2248 if (host->got_dbclk) {
2249 clk_disable(host->dbclk);
2250 clk_put(host->dbclk);
2253 iounmap(host->base);
2254 platform_set_drvdata(pdev, NULL);
2257 omap_hsmmc_gpio_free(pdata);
2259 release_mem_region(res->start, res->end - res->start + 1);
2263 static int omap_hsmmc_remove(struct platform_device *pdev)
2265 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2266 struct resource *res;
2269 mmc_host_enable(host->mmc);
2270 mmc_remove_host(host->mmc);
2272 omap_hsmmc_reg_put(host);
2273 if (host->pdata->cleanup)
2274 host->pdata->cleanup(&pdev->dev);
2275 free_irq(host->irq, host);
2276 if (mmc_slot(host).card_detect_irq)
2277 free_irq(mmc_slot(host).card_detect_irq, host);
2278 flush_scheduled_work();
2280 mmc_host_disable(host->mmc);
2281 clk_disable(host->iclk);
2282 clk_put(host->fclk);
2283 clk_put(host->iclk);
2284 if (host->got_dbclk) {
2285 clk_disable(host->dbclk);
2286 clk_put(host->dbclk);
2289 mmc_free_host(host->mmc);
2290 iounmap(host->base);
2291 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2294 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2296 release_mem_region(res->start, res->end - res->start + 1);
2297 platform_set_drvdata(pdev, NULL);
2303 static int omap_hsmmc_suspend(struct device *dev)
2306 struct platform_device *pdev = to_platform_device(dev);
2307 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2308 pm_message_t state = PMSG_SUSPEND; /* unused by MMC core */
2310 if (host && host->suspended)
2314 host->suspended = 1;
2315 if (host->pdata->suspend) {
2316 ret = host->pdata->suspend(&pdev->dev,
2319 dev_dbg(mmc_dev(host->mmc),
2320 "Unable to handle MMC board"
2321 " level suspend\n");
2322 host->suspended = 0;
2326 cancel_work_sync(&host->mmc_carddetect_work);
2327 mmc_host_enable(host->mmc);
2328 ret = mmc_suspend_host(host->mmc);
2330 omap_hsmmc_disable_irq(host);
2331 OMAP_HSMMC_WRITE(host->base, HCTL,
2332 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2333 mmc_host_disable(host->mmc);
2334 clk_disable(host->iclk);
2335 if (host->got_dbclk)
2336 clk_disable(host->dbclk);
2338 host->suspended = 0;
2339 if (host->pdata->resume) {
2340 ret = host->pdata->resume(&pdev->dev,
2343 dev_dbg(mmc_dev(host->mmc),
2344 "Unmask interrupt failed\n");
2346 mmc_host_disable(host->mmc);
2353 /* Routine to resume the MMC device */
2354 static int omap_hsmmc_resume(struct device *dev)
2357 struct platform_device *pdev = to_platform_device(dev);
2358 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2360 if (host && !host->suspended)
2364 ret = clk_enable(host->iclk);
2368 if (mmc_host_enable(host->mmc) != 0) {
2369 clk_disable(host->iclk);
2373 if (host->got_dbclk)
2374 clk_enable(host->dbclk);
2376 omap_hsmmc_conf_bus_power(host);
2378 if (host->pdata->resume) {
2379 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2381 dev_dbg(mmc_dev(host->mmc),
2382 "Unmask interrupt failed\n");
2385 omap_hsmmc_protect_card(host);
2387 /* Notify the core to resume the host */
2388 ret = mmc_resume_host(host->mmc);
2390 host->suspended = 0;
2392 mmc_host_lazy_disable(host->mmc);
2398 dev_dbg(mmc_dev(host->mmc),
2399 "Failed to enable MMC clocks during resume\n");
2404 #define omap_hsmmc_suspend NULL
2405 #define omap_hsmmc_resume NULL
2408 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2409 .suspend = omap_hsmmc_suspend,
2410 .resume = omap_hsmmc_resume,
2413 static struct platform_driver omap_hsmmc_driver = {
2414 .remove = omap_hsmmc_remove,
2416 .name = DRIVER_NAME,
2417 .owner = THIS_MODULE,
2418 .pm = &omap_hsmmc_dev_pm_ops,
2422 static int __init omap_hsmmc_init(void)
2424 /* Register the MMC driver */
2425 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2428 static void __exit omap_hsmmc_cleanup(void)
2430 /* Unregister MMC driver */
2431 platform_driver_unregister(&omap_hsmmc_driver);
2434 module_init(omap_hsmmc_init);
2435 module_exit(omap_hsmmc_cleanup);
2437 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2438 MODULE_LICENSE("GPL");
2439 MODULE_ALIAS("platform:" DRIVER_NAME);
2440 MODULE_AUTHOR("Texas Instruments Inc");