drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVSCLR                 0xFFFFF1FF
  60 #define SDVSDET                 0x00000400
  61 #define AUTOIDLE                0x1
  62 #define SDBP                    (1 << 8)
  63 #define DTO                     0xe
  64 #define ICE                     0x1
  65 #define ICS                     0x2
  66 #define CEN                     (1 << 2)
  67 #define CLKD_MASK               0x0000FFC0
  68 #define CLKD_SHIFT              6
  69 #define DTO_MASK                0x000F0000
  70 #define DTO_SHIFT               16
  71 #define INT_EN_MASK             0x307F0033
  72 #define INIT_STREAM             (1 << 1)
  73 #define DP_SELECT               (1 << 21)
  74 #define DDIR                    (1 << 4)
  75 #define DMA_EN                  0x1
  76 #define MSBS                    (1 << 5)
  77 #define BCE                     (1 << 1)
  78 #define FOUR_BIT                (1 << 1)
  79 #define CC                      0x1
  80 #define TC                      0x02
  81 #define OD                      0x1
  82 #define ERR                     (1 << 15)
  83 #define CMD_TIMEOUT             (1 << 16)
  84 #define DATA_TIMEOUT            (1 << 20)
  85 #define CMD_CRC                 (1 << 17)
  86 #define DATA_CRC                (1 << 21)
  87 #define CARD_ERR                (1 << 28)
  88 #define STAT_CLEAR              0xFFFFFFFF
  89 #define INIT_STREAM_CMD         0x00000000
  90 #define DUAL_VOLT_OCR_BIT       7
  91 #define SRC                     (1 << 25)
  92 #define SRD                     (1 << 26)
  93
  94 /*
  95  * FIXME: Most likely all the data using these _DEVID defines should come
  96  * from the platform_data, or implemented in controller and slot specific
  97  * functions.
  98  */
  99 #define OMAP_MMC1_DEVID         0
 100 #define OMAP_MMC2_DEVID         1
 101
 102 #define OMAP_MMC_DATADIR_NONE   0
 103 #define OMAP_MMC_DATADIR_READ   1
 104 #define OMAP_MMC_DATADIR_WRITE  2
 105 #define MMC_TIMEOUT_MS          20
 106 #define OMAP_MMC_MASTER_CLOCK   96000000
 107 #define DRIVER_NAME             "mmci-omap-hs"
 108
 109 /*
 110  * One controller can have multiple slots, like on some omap boards using
 111  * omap.c controller driver. Luckily this is not currently done on any known
 112  * omap_hsmmc.c device.
 113  */
 114 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 115
 116 /*
 117  * MMC Host controller read/write API's
 118  */
 119 #define OMAP_HSMMC_READ(base, reg)      \
 120         __raw_readl((base) + OMAP_HSMMC_##reg)
 121
 122 #define OMAP_HSMMC_WRITE(base, reg, val) \
 123         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 124
 125 struct mmc_omap_host {
 126         struct  device          *dev;
 127         struct  mmc_host        *mmc;
 128         struct  mmc_request     *mrq;
 129         struct  mmc_command     *cmd;
 130         struct  mmc_data        *data;
 131         struct  clk             *fclk;
 132         struct  clk             *iclk;
 133         struct  clk             *dbclk;
 134         struct  semaphore       sem;
 135         struct  work_struct     mmc_carddetect_work;
 136         void    __iomem         *base;
 137         resource_size_t         mapbase;
 138         unsigned int            id;
 139         unsigned int            dma_len;
 140         unsigned int            dma_dir;
 141         unsigned char           bus_mode;
 142         unsigned char           datadir;
 143         u32                     *buffer;
 144         u32                     bytesleft;
 145         int                     suspended;
 146         int                     irq;
 147         int                     carddetect;
 148         int                     use_dma, dma_ch;
 149         int                     initstr;
 150         int                     slot_id;
 151         int                     dbclk_enabled;
 152         struct  omap_mmc_platform_data  *pdata;
 153 };
 154
 155 /*
 156  * Stop clock to the card
 157  */
 158 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 159 {
 160         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 161                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 162         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 163                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 164 }
 165
 166 /*
 167  * Send init stream sequence to card
 168  * before sending IDLE command
 169  */
 170 static void send_init_stream(struct mmc_omap_host *host)
 171 {
 172         int reg = 0;
 173         unsigned long timeout;
 174
 175         disable_irq(host->irq);
 176         OMAP_HSMMC_WRITE(host->base, CON,
 177                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 178         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 179
 180         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 181         while ((reg != CC) && time_before(jiffies, timeout))
 182                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 183
 184         OMAP_HSMMC_WRITE(host->base, CON,
 185                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 186         enable_irq(host->irq);
 187 }
 188
 189 static inline
 190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 191 {
 192         int r = 1;
 193
 194         if (host->pdata->slots[host->slot_id].get_cover_state)
 195                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 196                         host->slot_id);
 197         return r;
 198 }
 199
 200 static ssize_t
 201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 202                            char *buf)
 203 {
 204         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 205         struct mmc_omap_host *host = mmc_priv(mmc);
 206
 207         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 208                        "open");
 209 }
 210
 211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 212
 213 static ssize_t
 214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 215                         char *buf)
 216 {
 217         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 218         struct mmc_omap_host *host = mmc_priv(mmc);
 219         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 220
 221         return sprintf(buf, "slot:%s\n", slot.name);
 222 }
 223
 224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 225
 226 /*
 227  * Configure the response type and send the cmd.
 228  */
 229 static void
 230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 231         struct mmc_data *data)
 232 {
 233         int cmdreg = 0, resptype = 0, cmdtype = 0;
 234
 235         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 236                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 237         host->cmd = cmd;
 238
 239         /*
 240          * Clear status bits and enable interrupts
 241          */
 242         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 243         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 244         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 if (cmd->flags & MMC_RSP_136)
 248                         resptype = 1;
 249                 else
 250                         resptype = 2;
 251         }
 252
 253         /*
 254          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 255          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 256          * a val of 0x3, rest 0x0.
 257          */
 258         if (cmd == host->mrq->stop)
 259                 cmdtype = 0x3;
 260
 261         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 262
 263         if (data) {
 264                 cmdreg |= DP_SELECT | MSBS | BCE;
 265                 if (data->flags & MMC_DATA_READ)
 266                         cmdreg |= DDIR;
 267                 else
 268                         cmdreg &= ~(DDIR);
 269         }
 270
 271         if (host->use_dma)
 272                 cmdreg |= DMA_EN;
 273
 274         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 275         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 276 }
 277
 278 /*
 279  * Notify the transfer complete to MMC core
 280  */
 281 static void
 282 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 283 {
 284         host->data = NULL;
 285
 286         if (host->use_dma && host->dma_ch != -1)
 287                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 288                         host->dma_dir);
 289
 290         host->datadir = OMAP_MMC_DATADIR_NONE;
 291
 292         if (!data->error)
 293                 data->bytes_xfered += data->blocks * (data->blksz);
 294         else
 295                 data->bytes_xfered = 0;
 296
 297         if (!data->stop) {
 298                 host->mrq = NULL;
 299                 mmc_request_done(host->mmc, data->mrq);
 300                 return;
 301         }
 302         mmc_omap_start_command(host, data->stop, NULL);
 303 }
 304
 305 /*
 306  * Notify the core about command completion
 307  */
 308 static void
 309 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 310 {
 311         host->cmd = NULL;
 312
 313         if (cmd->flags & MMC_RSP_PRESENT) {
 314                 if (cmd->flags & MMC_RSP_136) {
 315                         /* response type 2 */
 316                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 317                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 318                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 319                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 320                 } else {
 321                         /* response types 1, 1b, 3, 4, 5, 6 */
 322                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 323                 }
 324         }
 325         if (host->data == NULL || cmd->error) {
 326                 host->mrq = NULL;
 327                 mmc_request_done(host->mmc, cmd->mrq);
 328         }
 329 }
 330
 331 /*
 332  * DMA clean up for command errors
 333  */
 334 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 335 {
 336         host->data->error = -ETIMEDOUT;
 337
 338         if (host->use_dma && host->dma_ch != -1) {
 339                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 340                         host->dma_dir);
 341                 omap_free_dma(host->dma_ch);
 342                 host->dma_ch = -1;
 343                 up(&host->sem);
 344         }
 345         host->data = NULL;
 346         host->datadir = OMAP_MMC_DATADIR_NONE;
 347 }
 348
 349 /*
 350  * Readable error output
 351  */
 352 #ifdef CONFIG_MMC_DEBUG
 353 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 354 {
 355         /* --- means reserved bit without definition at documentation */
 356         static const char *mmc_omap_status_bits[] = {
 357                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 358                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 359                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 360                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 361         };
 362         char res[256];
 363         char *buf = res;
 364         int len, i;
 365
 366         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 367         buf += len;
 368
 369         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 370                 if (status & (1 << i)) {
 371                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 372                         buf += len;
 373                 }
 374
 375         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 376 }
 377 #endif  /* CONFIG_MMC_DEBUG */
 378
 379 /*
 380  * MMC controller internal state machines reset
 381  *
 382  * Used to reset command or data internal state machines, using respectively
 383  *  SRC or SRD bit of SYSCTL register
 384  * Can be called from interrupt context
 385  */
 386 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 387                 unsigned long bit)
 388 {
 389         unsigned long i = 0;
 390         unsigned long limit = (loops_per_jiffy *
 391                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 392
 393         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 394                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 395
 396         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 397                 (i++ < limit))
 398                 cpu_relax();
 399
 400         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 401                 dev_err(mmc_dev(host->mmc),
 402                         "Timeout waiting on controller reset in %s\n",
 403                         __func__);
 404 }
 405
 406 /*
 407  * MMC controller IRQ handler
 408  */
 409 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 410 {
 411         struct mmc_omap_host *host = dev_id;
 412         struct mmc_data *data;
 413         int end_cmd = 0, end_trans = 0, status;
 414
 415         if (host->cmd == NULL && host->data == NULL) {
 416                 OMAP_HSMMC_WRITE(host->base, STAT,
 417                         OMAP_HSMMC_READ(host->base, STAT));
 418                 return IRQ_HANDLED;
 419         }
 420
 421         data = host->data;
 422         status = OMAP_HSMMC_READ(host->base, STAT);
 423         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 424
 425         if (status & ERR) {
 426 #ifdef CONFIG_MMC_DEBUG
 427                 mmc_omap_report_irq(host, status);
 428 #endif
 429                 if ((status & CMD_TIMEOUT) ||
 430                         (status & CMD_CRC)) {
 431                         if (host->cmd) {
 432                                 if (status & CMD_TIMEOUT) {
 433                                         mmc_omap_reset_controller_fsm(host, SRC);
 434                                         host->cmd->error = -ETIMEDOUT;
 435                                 } else {
 436                                         host->cmd->error = -EILSEQ;
 437                                 }
 438                                 end_cmd = 1;
 439                         }
 440                         if (host->data) {
 441                                 mmc_dma_cleanup(host);
 442                                 mmc_omap_reset_controller_fsm(host, SRD);
 443                         }
 444                 }
 445                 if ((status & DATA_TIMEOUT) ||
 446                         (status & DATA_CRC)) {
 447                         if (host->data) {
 448                                 if (status & DATA_TIMEOUT)
 449                                         mmc_dma_cleanup(host);
 450                                 else
 451                                         host->data->error = -EILSEQ;
 452                                 mmc_omap_reset_controller_fsm(host, SRD);
 453                                 end_trans = 1;
 454                         }
 455                 }
 456                 if (status & CARD_ERR) {
 457                         dev_dbg(mmc_dev(host->mmc),
 458                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 459                         if (host->cmd)
 460                                 end_cmd = 1;
 461                         if (host->data)
 462                                 end_trans = 1;
 463                 }
 464         }
 465
 466         OMAP_HSMMC_WRITE(host->base, STAT, status);
 467
 468         if (end_cmd || (status & CC))
 469                 mmc_omap_cmd_done(host, host->cmd);
 470         if (end_trans || (status & TC))
 471                 mmc_omap_xfer_done(host, data);
 472
 473         return IRQ_HANDLED;
 474 }
 475
 476 /*
 477  * Switch MMC interface voltage ... only relevant for MMC1.
 478  *
 479  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 480  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 481  * Some chips, like eMMC ones, use internal transceivers.
 482  */
 483 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 484 {
 485         u32 reg_val = 0;
 486         int ret;
 487
 488         /* Disable the clocks */
 489         clk_disable(host->fclk);
 490         clk_disable(host->iclk);
 491         clk_disable(host->dbclk);
 492
 493         /* Turn the power off */
 494         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 495         if (ret != 0)
 496                 goto err;
 497
 498         /* Turn the power ON with given VDD 1.8 or 3.0v */
 499         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 500         if (ret != 0)
 501                 goto err;
 502
 503         clk_enable(host->fclk);
 504         clk_enable(host->iclk);
 505         clk_enable(host->dbclk);
 506
 507         OMAP_HSMMC_WRITE(host->base, HCTL,
 508                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 509         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 510
 511         /*
 512          * If a MMC dual voltage card is detected, the set_ios fn calls
 513          * this fn with VDD bit set for 1.8V. Upon card removal from the
 514          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 515          *
 516          * Cope with a bit of slop in the range ... per data sheets:
 517          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 518          *    but recommended values are 1.71V to 1.89V
 519          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 520          *    but recommended values are 2.7V to 3.3V
 521          *
 522          * Board setup code shouldn't permit anything very out-of-range.
 523          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 524          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 525          */
 526         if ((1 << vdd) <= MMC_VDD_23_24)
 527                 reg_val |= SDVS18;
 528         else
 529                 reg_val |= SDVS30;
 530
 531         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 532
 533         OMAP_HSMMC_WRITE(host->base, HCTL,
 534                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 535
 536         return 0;
 537 err:
 538         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 539         return ret;
 540 }
 541
 542 /*
 543  * Work Item to notify the core about card insertion/removal
 544  */
 545 static void mmc_omap_detect(struct work_struct *work)
 546 {
 547         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 548                                                 mmc_carddetect_work);
 549         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 550
 551         host->carddetect = slot->card_detect(slot->card_detect_irq);
 552
 553         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 554         if (host->carddetect) {
 555                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 556         } else {
 557                 mmc_omap_reset_controller_fsm(host, SRD);
 558                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 559         }
 560 }
 561
 562 /*
 563  * ISR for handling card insertion and removal
 564  */
 565 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 566 {
 567         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 568
 569         schedule_work(&host->mmc_carddetect_work);
 570
 571         return IRQ_HANDLED;
 572 }
 573
 574 /*
 575  * DMA call back function
 576  */
 577 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 578 {
 579         struct mmc_omap_host *host = data;
 580
 581         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 582                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 583
 584         if (host->dma_ch < 0)
 585                 return;
 586
 587         omap_free_dma(host->dma_ch);
 588         host->dma_ch = -1;
 589         /*
 590          * DMA Callback: run in interrupt context.
 591          * mutex_unlock will through a kernel warning if used.
 592          */
 593         up(&host->sem);
 594 }
 595
 596 /*
 597  * Configure dma src and destination parameters
 598  */
 599 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 600                                 struct mmc_data *data)
 601 {
 602         if (sync_dir == 0) {
 603                 omap_set_dma_dest_params(host->dma_ch, 0,
 604                         OMAP_DMA_AMODE_CONSTANT,
 605                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 606                 omap_set_dma_src_params(host->dma_ch, 0,
 607                         OMAP_DMA_AMODE_POST_INC,
 608                         sg_dma_address(&data->sg[0]), 0, 0);
 609         } else {
 610                 omap_set_dma_src_params(host->dma_ch, 0,
 611                         OMAP_DMA_AMODE_CONSTANT,
 612                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 613                 omap_set_dma_dest_params(host->dma_ch, 0,
 614                         OMAP_DMA_AMODE_POST_INC,
 615                         sg_dma_address(&data->sg[0]), 0, 0);
 616         }
 617         return 0;
 618 }
 619 /*
 620  * Routine to configure and start DMA for the MMC card
 621  */
 622 static int
 623 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 624 {
 625         int sync_dev, sync_dir = 0;
 626         int dma_ch = 0, ret = 0, err = 1;
 627         struct mmc_data *data = req->data;
 628
 629         /*
 630          * If for some reason the DMA transfer is still active,
 631          * we wait for timeout period and free the dma
 632          */
 633         if (host->dma_ch != -1) {
 634                 set_current_state(TASK_UNINTERRUPTIBLE);
 635                 schedule_timeout(100);
 636                 if (down_trylock(&host->sem)) {
 637                         omap_free_dma(host->dma_ch);
 638                         host->dma_ch = -1;
 639                         up(&host->sem);
 640                         return err;
 641                 }
 642         } else {
 643                 if (down_trylock(&host->sem))
 644                         return err;
 645         }
 646
 647         if (!(data->flags & MMC_DATA_WRITE)) {
 648                 host->dma_dir = DMA_FROM_DEVICE;
 649                 if (host->id == OMAP_MMC1_DEVID)
 650                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 651                 else
 652                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 653         } else {
 654                 host->dma_dir = DMA_TO_DEVICE;
 655                 if (host->id == OMAP_MMC1_DEVID)
 656                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 657                 else
 658                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 659         }
 660
 661         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 662                         host, &dma_ch);
 663         if (ret != 0) {
 664                 dev_dbg(mmc_dev(host->mmc),
 665                         "%s: omap_request_dma() failed with %d\n",
 666                         mmc_hostname(host->mmc), ret);
 667                 return ret;
 668         }
 669
 670         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 671                         data->sg_len, host->dma_dir);
 672         host->dma_ch = dma_ch;
 673
 674         if (!(data->flags & MMC_DATA_WRITE))
 675                 mmc_omap_config_dma_param(1, host, data);
 676         else
 677                 mmc_omap_config_dma_param(0, host, data);
 678
 679         if ((data->blksz % 4) == 0)
 680                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 681                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 682                         sync_dev, sync_dir);
 683         else
 684                 /* REVISIT: The MMC buffer increments only when MSB is written.
 685                  * Return error for blksz which is non multiple of four.
 686                  */
 687                 return -EINVAL;
 688
 689         omap_start_dma(dma_ch);
 690         return 0;
 691 }
 692
 693 static void set_data_timeout(struct mmc_omap_host *host,
 694                              struct mmc_request *req)
 695 {
 696         unsigned int timeout, cycle_ns;
 697         uint32_t reg, clkd, dto = 0;
 698
 699         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 700         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 701         if (clkd == 0)
 702                 clkd = 1;
 703
 704         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 705         timeout = req->data->timeout_ns / cycle_ns;
 706         timeout += req->data->timeout_clks;
 707         if (timeout) {
 708                 while ((timeout & 0x80000000) == 0) {
 709                         dto += 1;
 710                         timeout <<= 1;
 711                 }
 712                 dto = 31 - dto;
 713                 timeout <<= 1;
 714                 if (timeout && dto)
 715                         dto += 1;
 716                 if (dto >= 13)
 717                         dto -= 13;
 718                 else
 719                         dto = 0;
 720                 if (dto > 14)
 721                         dto = 14;
 722         }
 723
 724         reg &= ~DTO_MASK;
 725         reg |= dto << DTO_SHIFT;
 726         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 727 }
 728
 729 /*
 730  * Configure block length for MMC/SD cards and initiate the transfer.
 731  */
 732 static int
 733 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 734 {
 735         int ret;
 736         host->data = req->data;
 737
 738         if (req->data == NULL) {
 739                 host->datadir = OMAP_MMC_DATADIR_NONE;
 740                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 741                 return 0;
 742         }
 743
 744         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 745                                         | (req->data->blocks << 16));
 746         set_data_timeout(host, req);
 747
 748         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 749                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 750
 751         if (host->use_dma) {
 752                 ret = mmc_omap_start_dma_transfer(host, req);
 753                 if (ret != 0) {
 754                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 755                         return ret;
 756                 }
 757         }
 758         return 0;
 759 }
 760
 761 /*
 762  * Request function. for read/write operation
 763  */
 764 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 765 {
 766         struct mmc_omap_host *host = mmc_priv(mmc);
 767
 768         WARN_ON(host->mrq != NULL);
 769         host->mrq = req;
 770         mmc_omap_prepare_data(host, req);
 771         mmc_omap_start_command(host, req->cmd, req->data);
 772 }
 773
 774
 775 /* Routine to configure clock values. Exposed API to core */
 776 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 777 {
 778         struct mmc_omap_host *host = mmc_priv(mmc);
 779         u16 dsor = 0;
 780         unsigned long regval;
 781         unsigned long timeout;
 782
 783         switch (ios->power_mode) {
 784         case MMC_POWER_OFF:
 785                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 786                 break;
 787         case MMC_POWER_UP:
 788                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 789                 break;
 790         }
 791
 792         switch (mmc->ios.bus_width) {
 793         case MMC_BUS_WIDTH_4:
 794                 OMAP_HSMMC_WRITE(host->base, HCTL,
 795                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 796                 break;
 797         case MMC_BUS_WIDTH_1:
 798                 OMAP_HSMMC_WRITE(host->base, HCTL,
 799                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 800                 break;
 801         }
 802
 803         if (host->id == OMAP_MMC1_DEVID) {
 804                 /* Only MMC1 can interface at 3V without some flavor
 805                  * of external transceiver; but they all handle 1.8V.
 806                  */
 807                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 808                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 809                                 /*
 810                                  * The mmc_select_voltage fn of the core does
 811                                  * not seem to set the power_mode to
 812                                  * MMC_POWER_UP upon recalculating the voltage.
 813                                  * vdd 1.8v.
 814                                  */
 815                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 816                                         dev_dbg(mmc_dev(host->mmc),
 817                                                 "Switch operation failed\n");
 818                 }
 819         }
 820
 821         if (ios->clock) {
 822                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 823                 if (dsor < 1)
 824                         dsor = 1;
 825
 826                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 827                         dsor++;
 828
 829                 if (dsor > 250)
 830                         dsor = 250;
 831         }
 832         omap_mmc_stop_clock(host);
 833         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 834         regval = regval & ~(CLKD_MASK);
 835         regval = regval | (dsor << 6) | (DTO << 16);
 836         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 837         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 838                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 839
 840         /* Wait till the ICS bit is set */
 841         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 842         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 843                 && time_before(jiffies, timeout))
 844                 msleep(1);
 845
 846         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 847                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 848
 849         if (ios->power_mode == MMC_POWER_ON)
 850                 send_init_stream(host);
 851
 852         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 853                 OMAP_HSMMC_WRITE(host->base, CON,
 854                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 855 }
 856
 857 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 858 {
 859         struct mmc_omap_host *host = mmc_priv(mmc);
 860         struct omap_mmc_platform_data *pdata = host->pdata;
 861
 862         if (!pdata->slots[0].card_detect)
 863                 return -ENOSYS;
 864         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 865 }
 866
 867 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 868 {
 869         struct mmc_omap_host *host = mmc_priv(mmc);
 870         struct omap_mmc_platform_data *pdata = host->pdata;
 871
 872         if (!pdata->slots[0].get_ro)
 873                 return -ENOSYS;
 874         return pdata->slots[0].get_ro(host->dev, 0);
 875 }
 876
 877 static struct mmc_host_ops mmc_omap_ops = {
 878         .request = omap_mmc_request,
 879         .set_ios = omap_mmc_set_ios,
 880         .get_cd = omap_hsmmc_get_cd,
 881         .get_ro = omap_hsmmc_get_ro,
 882         /* NYET -- enable_sdio_irq */
 883 };
 884
 885 static int __init omap_mmc_probe(struct platform_device *pdev)
 886 {
 887         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 888         struct mmc_host *mmc;
 889         struct mmc_omap_host *host = NULL;
 890         struct resource *res;
 891         int ret = 0, irq;
 892         u32 hctl, capa;
 893
 894         if (pdata == NULL) {
 895                 dev_err(&pdev->dev, "Platform Data is missing\n");
 896                 return -ENXIO;
 897         }
 898
 899         if (pdata->nr_slots == 0) {
 900                 dev_err(&pdev->dev, "No Slots\n");
 901                 return -ENXIO;
 902         }
 903
 904         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 905         irq = platform_get_irq(pdev, 0);
 906         if (res == NULL || irq < 0)
 907                 return -ENXIO;
 908
 909         res = request_mem_region(res->start, res->end - res->start + 1,
 910                                                         pdev->name);
 911         if (res == NULL)
 912                 return -EBUSY;
 913
 914         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 915         if (!mmc) {
 916                 ret = -ENOMEM;
 917                 goto err;
 918         }
 919
 920         host            = mmc_priv(mmc);
 921         host->mmc       = mmc;
 922         host->pdata     = pdata;
 923         host->dev       = &pdev->dev;
 924         host->use_dma   = 1;
 925         host->dev->dma_mask = &pdata->dma_mask;
 926         host->dma_ch    = -1;
 927         host->irq       = irq;
 928         host->id        = pdev->id;
 929         host->slot_id   = 0;
 930         host->mapbase   = res->start;
 931         host->base      = ioremap(host->mapbase, SZ_4K);
 932
 933         platform_set_drvdata(pdev, host);
 934         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 935
 936         mmc->ops        = &mmc_omap_ops;
 937         mmc->f_min      = 400000;
 938         mmc->f_max      = 52000000;
 939
 940         sema_init(&host->sem, 1);
 941
 942         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 943         if (IS_ERR(host->iclk)) {
 944                 ret = PTR_ERR(host->iclk);
 945                 host->iclk = NULL;
 946                 goto err1;
 947         }
 948         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 949         if (IS_ERR(host->fclk)) {
 950                 ret = PTR_ERR(host->fclk);
 951                 host->fclk = NULL;
 952                 clk_put(host->iclk);
 953                 goto err1;
 954         }
 955
 956         if (clk_enable(host->fclk) != 0) {
 957                 clk_put(host->iclk);
 958                 clk_put(host->fclk);
 959                 goto err1;
 960         }
 961
 962         if (clk_enable(host->iclk) != 0) {
 963                 clk_disable(host->fclk);
 964                 clk_put(host->iclk);
 965                 clk_put(host->fclk);
 966                 goto err1;
 967         }
 968
 969         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 970         /*
 971          * MMC can still work without debounce clock.
 972          */
 973         if (IS_ERR(host->dbclk))
 974                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 975         else
 976                 if (clk_enable(host->dbclk) != 0)
 977                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 978                                                         " clk failed\n");
 979                 else
 980                         host->dbclk_enabled = 1;
 981
 982 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 983         mmc->max_phys_segs = 1;
 984         mmc->max_hw_segs = 1;
 985 #endif
 986         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 987         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 988         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 989         mmc->max_seg_size = mmc->max_req_size;
 990
 991         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 992         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 993
 994         if (pdata->slots[host->slot_id].wires >= 4)
 995                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 996
 997         /* Only MMC1 supports 3.0V */
 998         if (host->id == OMAP_MMC1_DEVID) {
 999                 hctl = SDVS30;
1000                 capa = VS30 | VS18;
1001         } else {
1002                 hctl = SDVS18;
1003                 capa = VS18;
1004         }
1005
1006         OMAP_HSMMC_WRITE(host->base, HCTL,
1007                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
1008
1009         OMAP_HSMMC_WRITE(host->base, CAPA,
1010                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
1011
1012         /* Set the controller to AUTO IDLE mode */
1013         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
1014                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
1015
1016         /* Set SD bus power bit */
1017         OMAP_HSMMC_WRITE(host->base, HCTL,
1018                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1019
1020         /* Request IRQ for MMC operations */
1021         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1022                         mmc_hostname(mmc), host);
1023         if (ret) {
1024                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1025                 goto err_irq;
1026         }
1027
1028         if (pdata->init != NULL) {
1029                 if (pdata->init(&pdev->dev) != 0) {
1030                         dev_dbg(mmc_dev(host->mmc),
1031                                 "Unable to configure MMC IRQs\n");
1032                         goto err_irq_cd_init;
1033                 }
1034         }
1035
1036         /* Request IRQ for card detect */
1037         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1038                 ret = request_irq(mmc_slot(host).card_detect_irq,
1039                                   omap_mmc_cd_handler,
1040                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1041                                           | IRQF_DISABLED,
1042                                   mmc_hostname(mmc), host);
1043                 if (ret) {
1044                         dev_dbg(mmc_dev(host->mmc),
1045                                 "Unable to grab MMC CD IRQ\n");
1046                         goto err_irq_cd;
1047                 }
1048         }
1049
1050         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1051         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1052
1053         mmc_add_host(mmc);
1054
1055         if (host->pdata->slots[host->slot_id].name != NULL) {
1056                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1057                 if (ret < 0)
1058                         goto err_slot_name;
1059         }
1060         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1061                         host->pdata->slots[host->slot_id].get_cover_state) {
1062                 ret = device_create_file(&mmc->class_dev,
1063                                         &dev_attr_cover_switch);
1064                 if (ret < 0)
1065                         goto err_cover_switch;
1066         }
1067
1068         return 0;
1069
1070 err_cover_switch:
1071         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1072 err_slot_name:
1073         mmc_remove_host(mmc);
1074 err_irq_cd:
1075         free_irq(mmc_slot(host).card_detect_irq, host);
1076 err_irq_cd_init:
1077         free_irq(host->irq, host);
1078 err_irq:
1079         clk_disable(host->fclk);
1080         clk_disable(host->iclk);
1081         clk_put(host->fclk);
1082         clk_put(host->iclk);
1083         if (host->dbclk_enabled) {
1084                 clk_disable(host->dbclk);
1085                 clk_put(host->dbclk);
1086         }
1087
1088 err1:
1089         iounmap(host->base);
1090 err:
1091         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1092         release_mem_region(res->start, res->end - res->start + 1);
1093         if (host)
1094                 mmc_free_host(mmc);
1095         return ret;
1096 }
1097
1098 static int omap_mmc_remove(struct platform_device *pdev)
1099 {
1100         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1101         struct resource *res;
1102
1103         if (host) {
1104                 mmc_remove_host(host->mmc);
1105                 if (host->pdata->cleanup)
1106                         host->pdata->cleanup(&pdev->dev);
1107                 free_irq(host->irq, host);
1108                 if (mmc_slot(host).card_detect_irq)
1109                         free_irq(mmc_slot(host).card_detect_irq, host);
1110                 flush_scheduled_work();
1111
1112                 clk_disable(host->fclk);
1113                 clk_disable(host->iclk);
1114                 clk_put(host->fclk);
1115                 clk_put(host->iclk);
1116                 if (host->dbclk_enabled) {
1117                         clk_disable(host->dbclk);
1118                         clk_put(host->dbclk);
1119                 }
1120
1121                 mmc_free_host(host->mmc);
1122                 iounmap(host->base);
1123         }
1124
1125         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1126         if (res)
1127                 release_mem_region(res->start, res->end - res->start + 1);
1128         platform_set_drvdata(pdev, NULL);
1129
1130         return 0;
1131 }
1132
1133 #ifdef CONFIG_PM
1134 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1135 {
1136         int ret = 0;
1137         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1138
1139         if (host && host->suspended)
1140                 return 0;
1141
1142         if (host) {
1143                 ret = mmc_suspend_host(host->mmc, state);
1144                 if (ret == 0) {
1145                         host->suspended = 1;
1146
1147                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1148                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1149
1150                         if (host->pdata->suspend) {
1151                                 ret = host->pdata->suspend(&pdev->dev,
1152                                                                 host->slot_id);
1153                                 if (ret)
1154                                         dev_dbg(mmc_dev(host->mmc),
1155                                                 "Unable to handle MMC board"
1156                                                 " level suspend\n");
1157                         }
1158
1159                         if (host->id == OMAP_MMC1_DEVID
1160                                         && !(OMAP_HSMMC_READ(host->base, HCTL)
1161                                                         & SDVSDET)) {
1162                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1163                                         OMAP_HSMMC_READ(host->base, HCTL)
1164                                         & SDVSCLR);
1165                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1166                                         OMAP_HSMMC_READ(host->base, HCTL)
1167                                         | SDVS30);
1168                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1169                                         OMAP_HSMMC_READ(host->base, HCTL)
1170                                         | SDBP);
1171                         }
1172
1173                         clk_disable(host->fclk);
1174                         clk_disable(host->iclk);
1175                         clk_disable(host->dbclk);
1176                 }
1177
1178         }
1179         return ret;
1180 }
1181
1182 /* Routine to resume the MMC device */
1183 static int omap_mmc_resume(struct platform_device *pdev)
1184 {
1185         int ret = 0;
1186         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1187
1188         if (host && !host->suspended)
1189                 return 0;
1190
1191         if (host) {
1192
1193                 ret = clk_enable(host->fclk);
1194                 if (ret)
1195                         goto clk_en_err;
1196
1197                 ret = clk_enable(host->iclk);
1198                 if (ret) {
1199                         clk_disable(host->fclk);
1200                         clk_put(host->fclk);
1201                         goto clk_en_err;
1202                 }
1203
1204                 if (clk_enable(host->dbclk) != 0)
1205                         dev_dbg(mmc_dev(host->mmc),
1206                                         "Enabling debounce clk failed\n");
1207
1208                 if (host->pdata->resume) {
1209                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1210                         if (ret)
1211                                 dev_dbg(mmc_dev(host->mmc),
1212                                         "Unmask interrupt failed\n");
1213                 }
1214
1215                 /* Notify the core to resume the host */
1216                 ret = mmc_resume_host(host->mmc);
1217                 if (ret == 0)
1218                         host->suspended = 0;
1219         }
1220
1221         return ret;
1222
1223 clk_en_err:
1224         dev_dbg(mmc_dev(host->mmc),
1225                 "Failed to enable MMC clocks during resume\n");
1226         return ret;
1227 }
1228
1229 #else
1230 #define omap_mmc_suspend        NULL
1231 #define omap_mmc_resume         NULL
1232 #endif
1233
1234 static struct platform_driver omap_mmc_driver = {
1235         .probe          = omap_mmc_probe,
1236         .remove         = omap_mmc_remove,
1237         .suspend        = omap_mmc_suspend,
1238         .resume         = omap_mmc_resume,
1239         .driver         = {
1240                 .name = DRIVER_NAME,
1241                 .owner = THIS_MODULE,
1242         },
1243 };
1244
1245 static int __init omap_mmc_init(void)
1246 {
1247         /* Register the MMC driver */
1248         return platform_driver_register(&omap_mmc_driver);
1249 }
1250
1251 static void __exit omap_mmc_cleanup(void)
1252 {
1253         /* Unregister MMC driver */
1254         platform_driver_unregister(&omap_mmc_driver);
1255 }
1256
1257 module_init(omap_mmc_init);
1258 module_exit(omap_mmc_cleanup);
1259
1260 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1261 MODULE_LICENSE("GPL");
1262 MODULE_ALIAS("platform:" DRIVER_NAME);
1263 MODULE_AUTHOR("Texas Instruments Inc");