drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/io.h>
  31 #include <linux/semaphore.h>
  32 #include <mach/dma.h>
  33 #include <mach/hardware.h>
  34 #include <mach/board.h>
  35 #include <mach/mmc.h>
  36 #include <mach/cpu.h>
  37
  38 /* OMAP HSMMC Host Controller Registers */
  39 #define OMAP_HSMMC_SYSCONFIG    0x0010
  40 #define OMAP_HSMMC_SYSSTATUS    0x0014
  41 #define OMAP_HSMMC_CON          0x002C
  42 #define OMAP_HSMMC_BLK          0x0104
  43 #define OMAP_HSMMC_ARG          0x0108
  44 #define OMAP_HSMMC_CMD          0x010C
  45 #define OMAP_HSMMC_RSP10        0x0110
  46 #define OMAP_HSMMC_RSP32        0x0114
  47 #define OMAP_HSMMC_RSP54        0x0118
  48 #define OMAP_HSMMC_RSP76        0x011C
  49 #define OMAP_HSMMC_DATA         0x0120
  50 #define OMAP_HSMMC_HCTL         0x0128
  51 #define OMAP_HSMMC_SYSCTL       0x012C
  52 #define OMAP_HSMMC_STAT         0x0130
  53 #define OMAP_HSMMC_IE           0x0134
  54 #define OMAP_HSMMC_ISE          0x0138
  55 #define OMAP_HSMMC_CAPA         0x0140
  56
  57 #define VS18                    (1 << 26)
  58 #define VS30                    (1 << 25)
  59 #define SDVS18                  (0x5 << 9)
  60 #define SDVS30                  (0x6 << 9)
  61 #define SDVS33                  (0x7 << 9)
  62 #define SDVS_MASK               0x00000E00
  63 #define SDVSCLR                 0xFFFFF1FF
  64 #define SDVSDET                 0x00000400
  65 #define AUTOIDLE                0x1
  66 #define SDBP                    (1 << 8)
  67 #define DTO                     0xe
  68 #define ICE                     0x1
  69 #define ICS                     0x2
  70 #define CEN                     (1 << 2)
  71 #define CLKD_MASK               0x0000FFC0
  72 #define CLKD_SHIFT              6
  73 #define DTO_MASK                0x000F0000
  74 #define DTO_SHIFT               16
  75 #define INT_EN_MASK             0x307F0033
  76 #define BWR_ENABLE              (1 << 4)
  77 #define BRR_ENABLE              (1 << 5)
  78 #define INIT_STREAM             (1 << 1)
  79 #define DP_SELECT               (1 << 21)
  80 #define DDIR                    (1 << 4)
  81 #define DMA_EN                  0x1
  82 #define MSBS                    (1 << 5)
  83 #define BCE                     (1 << 1)
  84 #define FOUR_BIT                (1 << 1)
  85 #define DW8                     (1 << 5)
  86 #define CC                      0x1
  87 #define TC                      0x02
  88 #define OD                      0x1
  89 #define ERR                     (1 << 15)
  90 #define CMD_TIMEOUT             (1 << 16)
  91 #define DATA_TIMEOUT            (1 << 20)
  92 #define CMD_CRC                 (1 << 17)
  93 #define DATA_CRC                (1 << 21)
  94 #define CARD_ERR                (1 << 28)
  95 #define STAT_CLEAR              0xFFFFFFFF
  96 #define INIT_STREAM_CMD         0x00000000
  97 #define DUAL_VOLT_OCR_BIT       7
  98 #define SRC                     (1 << 25)
  99 #define SRD                     (1 << 26)
 100 #define SOFTRESET               (1 << 1)
 101 #define RESETDONE               (1 << 0)
 102
 103 /*
 104  * FIXME: Most likely all the data using these _DEVID defines should come
 105  * from the platform_data, or implemented in controller and slot specific
 106  * functions.
 107  */
 108 #define OMAP_MMC1_DEVID         0
 109 #define OMAP_MMC2_DEVID         1
 110 #define OMAP_MMC3_DEVID         2
 111
 112 #define MMC_TIMEOUT_MS          20
 113 #define OMAP_MMC_MASTER_CLOCK   96000000
 114 #define DRIVER_NAME             "mmci-omap-hs"
 115
 116 /*
 117  * One controller can have multiple slots, like on some omap boards using
 118  * omap.c controller driver. Luckily this is not currently done on any known
 119  * omap_hsmmc.c device.
 120  */
 121 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 122
 123 /*
 124  * MMC Host controller read/write API's
 125  */
 126 #define OMAP_HSMMC_READ(base, reg)      \
 127         __raw_readl((base) + OMAP_HSMMC_##reg)
 128
 129 #define OMAP_HSMMC_WRITE(base, reg, val) \
 130         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 131
 132 struct mmc_omap_host {
 133         struct  device          *dev;
 134         struct  mmc_host        *mmc;
 135         struct  mmc_request     *mrq;
 136         struct  mmc_command     *cmd;
 137         struct  mmc_data        *data;
 138         struct  clk             *fclk;
 139         struct  clk             *iclk;
 140         struct  clk             *dbclk;
 141         struct  semaphore       sem;
 142         struct  work_struct     mmc_carddetect_work;
 143         void    __iomem         *base;
 144         resource_size_t         mapbase;
 145         unsigned int            id;
 146         unsigned int            dma_len;
 147         unsigned int            dma_sg_idx;
 148         unsigned char           bus_mode;
 149         unsigned char           power_mode;
 150         u32                     *buffer;
 151         u32                     bytesleft;
 152         int                     suspended;
 153         int                     irq;
 154         int                     use_dma, dma_ch;
 155         int                     dma_line_tx, dma_line_rx;
 156         int                     slot_id;
 157         int                     dbclk_enabled;
 158         int                     response_busy;
 159         int                     context_loss;
 160
 161         struct  omap_mmc_platform_data  *pdata;
 162 };
 163
 164 /*
 165  * Stop clock to the card
 166  */
 167 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 168 {
 169         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 170                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 171         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 172                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 173 }
 174
 175 #ifdef CONFIG_PM
 176
 177 /*
 178  * Restore the MMC host context, if it was lost as result of a
 179  * power state change.
 180  */
 181 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 182 {
 183         struct mmc_ios *ios = &host->mmc->ios;
 184         struct omap_mmc_platform_data *pdata = host->pdata;
 185         int context_loss = 0;
 186         u32 hctl, capa, con;
 187         u16 dsor = 0;
 188         unsigned long timeout;
 189
 190         if (pdata->get_context_loss_count) {
 191                 context_loss = pdata->get_context_loss_count(host->dev);
 192                 if (context_loss < 0)
 193                         return 1;
 194         }
 195
 196         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 197                 context_loss == host->context_loss ? "not " : "");
 198         if (host->context_loss == context_loss)
 199                 return 1;
 200
 201         /* Wait for hardware reset */
 202         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 203         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 204                 && time_before(jiffies, timeout))
 205                 ;
 206
 207         /* Do software reset */
 208         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 209         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 210         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 211                 && time_before(jiffies, timeout))
 212                 ;
 213
 214         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 215                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 216
 217         if (host->id == OMAP_MMC1_DEVID) {
 218                 if (host->power_mode != MMC_POWER_OFF &&
 219                     (1 << ios->vdd) <= MMC_VDD_23_24)
 220                         hctl = SDVS18;
 221                 else
 222                         hctl = SDVS30;
 223                 capa = VS30 | VS18;
 224         } else {
 225                 hctl = SDVS18;
 226                 capa = VS18;
 227         }
 228
 229         OMAP_HSMMC_WRITE(host->base, HCTL,
 230                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 231
 232         OMAP_HSMMC_WRITE(host->base, CAPA,
 233                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 234
 235         OMAP_HSMMC_WRITE(host->base, HCTL,
 236                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 237
 238         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 239         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 240                 && time_before(jiffies, timeout))
 241                 ;
 242
 243         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 244         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 245         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 246
 247         /* Do not initialize card-specific things if the power is off */
 248         if (host->power_mode == MMC_POWER_OFF)
 249                 goto out;
 250
 251         con = OMAP_HSMMC_READ(host->base, CON);
 252         switch (ios->bus_width) {
 253         case MMC_BUS_WIDTH_8:
 254                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 255                 break;
 256         case MMC_BUS_WIDTH_4:
 257                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 258                 OMAP_HSMMC_WRITE(host->base, HCTL,
 259                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 260                 break;
 261         case MMC_BUS_WIDTH_1:
 262                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 263                 OMAP_HSMMC_WRITE(host->base, HCTL,
 264                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 265                 break;
 266         }
 267
 268         if (ios->clock) {
 269                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 270                 if (dsor < 1)
 271                         dsor = 1;
 272
 273                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 274                         dsor++;
 275
 276                 if (dsor > 250)
 277                         dsor = 250;
 278         }
 279
 280         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 281                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 282         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 283         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 284                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 285
 286         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 287         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 288                 && time_before(jiffies, timeout))
 289                 ;
 290
 291         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 292                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 293
 294         con = OMAP_HSMMC_READ(host->base, CON);
 295         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 296                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 297         else
 298                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 299 out:
 300         host->context_loss = context_loss;
 301
 302         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 303         return 0;
 304 }
 305
 306 /*
 307  * Save the MMC host context (store the number of power state changes so far).
 308  */
 309 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 310 {
 311         struct omap_mmc_platform_data *pdata = host->pdata;
 312         int context_loss;
 313
 314         if (pdata->get_context_loss_count) {
 315                 context_loss = pdata->get_context_loss_count(host->dev);
 316                 if (context_loss < 0)
 317                         return;
 318                 host->context_loss = context_loss;
 319         }
 320 }
 321
 322 #else
 323
 324 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 325 {
 326         return 0;
 327 }
 328
 329 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 330 {
 331 }
 332
 333 #endif
 334
 335 /*
 336  * Send init stream sequence to card
 337  * before sending IDLE command
 338  */
 339 static void send_init_stream(struct mmc_omap_host *host)
 340 {
 341         int reg = 0;
 342         unsigned long timeout;
 343
 344         disable_irq(host->irq);
 345         OMAP_HSMMC_WRITE(host->base, CON,
 346                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 347         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 348
 349         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 350         while ((reg != CC) && time_before(jiffies, timeout))
 351                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 352
 353         OMAP_HSMMC_WRITE(host->base, CON,
 354                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 355         enable_irq(host->irq);
 356 }
 357
 358 static inline
 359 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 360 {
 361         int r = 1;
 362
 363         if (host->pdata->slots[host->slot_id].get_cover_state)
 364                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 365                         host->slot_id);
 366         return r;
 367 }
 368
 369 static ssize_t
 370 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 371                            char *buf)
 372 {
 373         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 374         struct mmc_omap_host *host = mmc_priv(mmc);
 375
 376         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 377                        "open");
 378 }
 379
 380 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 381
 382 static ssize_t
 383 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 384                         char *buf)
 385 {
 386         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 387         struct mmc_omap_host *host = mmc_priv(mmc);
 388         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 389
 390         return sprintf(buf, "%s\n", slot.name);
 391 }
 392
 393 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 394
 395 /*
 396  * Configure the response type and send the cmd.
 397  */
 398 static void
 399 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 400         struct mmc_data *data)
 401 {
 402         int cmdreg = 0, resptype = 0, cmdtype = 0;
 403
 404         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 405                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 406         host->cmd = cmd;
 407
 408         /*
 409          * Clear status bits and enable interrupts
 410          */
 411         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 412         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 413
 414         if (host->use_dma)
 415                 OMAP_HSMMC_WRITE(host->base, IE,
 416                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 417         else
 418                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 419
 420         host->response_busy = 0;
 421         if (cmd->flags & MMC_RSP_PRESENT) {
 422                 if (cmd->flags & MMC_RSP_136)
 423                         resptype = 1;
 424                 else if (cmd->flags & MMC_RSP_BUSY) {
 425                         resptype = 3;
 426                         host->response_busy = 1;
 427                 } else
 428                         resptype = 2;
 429         }
 430
 431         /*
 432          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 433          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 434          * a val of 0x3, rest 0x0.
 435          */
 436         if (cmd == host->mrq->stop)
 437                 cmdtype = 0x3;
 438
 439         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 440
 441         if (data) {
 442                 cmdreg |= DP_SELECT | MSBS | BCE;
 443                 if (data->flags & MMC_DATA_READ)
 444                         cmdreg |= DDIR;
 445                 else
 446                         cmdreg &= ~(DDIR);
 447         }
 448
 449         if (host->use_dma)
 450                 cmdreg |= DMA_EN;
 451
 452         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 453         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 454 }
 455
 456 static int
 457 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 458 {
 459         if (data->flags & MMC_DATA_WRITE)
 460                 return DMA_TO_DEVICE;
 461         else
 462                 return DMA_FROM_DEVICE;
 463 }
 464
 465 /*
 466  * Notify the transfer complete to MMC core
 467  */
 468 static void
 469 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 470 {
 471         if (!data) {
 472                 struct mmc_request *mrq = host->mrq;
 473
 474                 host->mrq = NULL;
 475                 mmc_request_done(host->mmc, mrq);
 476                 return;
 477         }
 478
 479         host->data = NULL;
 480
 481         if (host->use_dma && host->dma_ch != -1)
 482                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 483                         mmc_omap_get_dma_dir(host, data));
 484
 485         if (!data->error)
 486                 data->bytes_xfered += data->blocks * (data->blksz);
 487         else
 488                 data->bytes_xfered = 0;
 489
 490         if (!data->stop) {
 491                 host->mrq = NULL;
 492                 mmc_request_done(host->mmc, data->mrq);
 493                 return;
 494         }
 495         mmc_omap_start_command(host, data->stop, NULL);
 496 }
 497
 498 /*
 499  * Notify the core about command completion
 500  */
 501 static void
 502 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 503 {
 504         host->cmd = NULL;
 505
 506         if (cmd->flags & MMC_RSP_PRESENT) {
 507                 if (cmd->flags & MMC_RSP_136) {
 508                         /* response type 2 */
 509                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 510                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 511                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 512                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 513                 } else {
 514                         /* response types 1, 1b, 3, 4, 5, 6 */
 515                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 516                 }
 517         }
 518         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 519                 host->mrq = NULL;
 520                 mmc_request_done(host->mmc, cmd->mrq);
 521         }
 522 }
 523
 524 /*
 525  * DMA clean up for command errors
 526  */
 527 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 528 {
 529         host->data->error = errno;
 530
 531         if (host->use_dma && host->dma_ch != -1) {
 532                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 533                         mmc_omap_get_dma_dir(host, host->data));
 534                 omap_free_dma(host->dma_ch);
 535                 host->dma_ch = -1;
 536                 up(&host->sem);
 537         }
 538         host->data = NULL;
 539 }
 540
 541 /*
 542  * Readable error output
 543  */
 544 #ifdef CONFIG_MMC_DEBUG
 545 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 546 {
 547         /* --- means reserved bit without definition at documentation */
 548         static const char *mmc_omap_status_bits[] = {
 549                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 550                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 551                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 552                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 553         };
 554         char res[256];
 555         char *buf = res;
 556         int len, i;
 557
 558         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 559         buf += len;
 560
 561         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 562                 if (status & (1 << i)) {
 563                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 564                         buf += len;
 565                 }
 566
 567         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 568 }
 569 #endif  /* CONFIG_MMC_DEBUG */
 570
 571 /*
 572  * MMC controller internal state machines reset
 573  *
 574  * Used to reset command or data internal state machines, using respectively
 575  *  SRC or SRD bit of SYSCTL register
 576  * Can be called from interrupt context
 577  */
 578 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 579                 unsigned long bit)
 580 {
 581         unsigned long i = 0;
 582         unsigned long limit = (loops_per_jiffy *
 583                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 584
 585         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 586                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 587
 588         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 589                 (i++ < limit))
 590                 cpu_relax();
 591
 592         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 593                 dev_err(mmc_dev(host->mmc),
 594                         "Timeout waiting on controller reset in %s\n",
 595                         __func__);
 596 }
 597
 598 /*
 599  * MMC controller IRQ handler
 600  */
 601 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 602 {
 603         struct mmc_omap_host *host = dev_id;
 604         struct mmc_data *data;
 605         int end_cmd = 0, end_trans = 0, status;
 606
 607         if (host->mrq == NULL) {
 608                 OMAP_HSMMC_WRITE(host->base, STAT,
 609                         OMAP_HSMMC_READ(host->base, STAT));
 610                 /* Flush posted write */
 611                 OMAP_HSMMC_READ(host->base, STAT);
 612                 return IRQ_HANDLED;
 613         }
 614
 615         data = host->data;
 616         status = OMAP_HSMMC_READ(host->base, STAT);
 617         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 618
 619         if (status & ERR) {
 620 #ifdef CONFIG_MMC_DEBUG
 621                 mmc_omap_report_irq(host, status);
 622 #endif
 623                 if ((status & CMD_TIMEOUT) ||
 624                         (status & CMD_CRC)) {
 625                         if (host->cmd) {
 626                                 if (status & CMD_TIMEOUT) {
 627                                         mmc_omap_reset_controller_fsm(host, SRC);
 628                                         host->cmd->error = -ETIMEDOUT;
 629                                 } else {
 630                                         host->cmd->error = -EILSEQ;
 631                                 }
 632                                 end_cmd = 1;
 633                         }
 634                         if (host->data || host->response_busy) {
 635                                 if (host->data)
 636                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 637                                 host->response_busy = 0;
 638                                 mmc_omap_reset_controller_fsm(host, SRD);
 639                         }
 640                 }
 641                 if ((status & DATA_TIMEOUT) ||
 642                         (status & DATA_CRC)) {
 643                         if (host->data || host->response_busy) {
 644                                 int err = (status & DATA_TIMEOUT) ?
 645                                                 -ETIMEDOUT : -EILSEQ;
 646
 647                                 if (host->data)
 648                                         mmc_dma_cleanup(host, err);
 649                                 else
 650                                         host->mrq->cmd->error = err;
 651                                 host->response_busy = 0;
 652                                 mmc_omap_reset_controller_fsm(host, SRD);
 653                                 end_trans = 1;
 654                         }
 655                 }
 656                 if (status & CARD_ERR) {
 657                         dev_dbg(mmc_dev(host->mmc),
 658                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 659                         if (host->cmd)
 660                                 end_cmd = 1;
 661                         if (host->data)
 662                                 end_trans = 1;
 663                 }
 664         }
 665
 666         OMAP_HSMMC_WRITE(host->base, STAT, status);
 667         /* Flush posted write */
 668         OMAP_HSMMC_READ(host->base, STAT);
 669
 670         if (end_cmd || ((status & CC) && host->cmd))
 671                 mmc_omap_cmd_done(host, host->cmd);
 672         if (end_trans || (status & TC))
 673                 mmc_omap_xfer_done(host, data);
 674
 675         return IRQ_HANDLED;
 676 }
 677
 678 static void set_sd_bus_power(struct mmc_omap_host *host)
 679 {
 680         unsigned long i;
 681
 682         OMAP_HSMMC_WRITE(host->base, HCTL,
 683                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 684         for (i = 0; i < loops_per_jiffy; i++) {
 685                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 686                         break;
 687                 cpu_relax();
 688         }
 689 }
 690
 691 /*
 692  * Switch MMC interface voltage ... only relevant for MMC1.
 693  *
 694  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 695  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 696  * Some chips, like eMMC ones, use internal transceivers.
 697  */
 698 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 699 {
 700         u32 reg_val = 0;
 701         int ret;
 702
 703         /* Disable the clocks */
 704         clk_disable(host->fclk);
 705         clk_disable(host->iclk);
 706         clk_disable(host->dbclk);
 707
 708         /* Turn the power off */
 709         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 710         if (ret != 0)
 711                 goto err;
 712
 713         /* Turn the power ON with given VDD 1.8 or 3.0v */
 714         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 715         if (ret != 0)
 716                 goto err;
 717
 718         clk_enable(host->fclk);
 719         clk_enable(host->iclk);
 720         clk_enable(host->dbclk);
 721
 722         OMAP_HSMMC_WRITE(host->base, HCTL,
 723                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 724         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 725
 726         /*
 727          * If a MMC dual voltage card is detected, the set_ios fn calls
 728          * this fn with VDD bit set for 1.8V. Upon card removal from the
 729          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 730          *
 731          * Cope with a bit of slop in the range ... per data sheets:
 732          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 733          *    but recommended values are 1.71V to 1.89V
 734          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 735          *    but recommended values are 2.7V to 3.3V
 736          *
 737          * Board setup code shouldn't permit anything very out-of-range.
 738          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 739          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 740          */
 741         if ((1 << vdd) <= MMC_VDD_23_24)
 742                 reg_val |= SDVS18;
 743         else
 744                 reg_val |= SDVS30;
 745
 746         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 747         set_sd_bus_power(host);
 748
 749         return 0;
 750 err:
 751         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 752         return ret;
 753 }
 754
 755 /*
 756  * Work Item to notify the core about card insertion/removal
 757  */
 758 static void mmc_omap_detect(struct work_struct *work)
 759 {
 760         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 761                                                 mmc_carddetect_work);
 762         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 763         int carddetect;
 764
 765         if (host->suspended)
 766                 return;
 767
 768         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 769
 770         if (mmc_slot(host).card_detect)
 771                 carddetect = slot->card_detect(slot->card_detect_irq);
 772         else
 773                 carddetect = -ENOSYS;
 774
 775         if (carddetect) {
 776                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 777         } else {
 778                 mmc_host_enable(host->mmc);
 779                 mmc_omap_reset_controller_fsm(host, SRD);
 780                 mmc_host_lazy_disable(host->mmc);
 781                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 782         }
 783 }
 784
 785 /*
 786  * ISR for handling card insertion and removal
 787  */
 788 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 789 {
 790         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 791
 792         if (host->suspended)
 793                 return IRQ_HANDLED;
 794         schedule_work(&host->mmc_carddetect_work);
 795
 796         return IRQ_HANDLED;
 797 }
 798
 799 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 800                                      struct mmc_data *data)
 801 {
 802         int sync_dev;
 803
 804         if (data->flags & MMC_DATA_WRITE)
 805                 sync_dev = host->dma_line_tx;
 806         else
 807                 sync_dev = host->dma_line_rx;
 808         return sync_dev;
 809 }
 810
 811 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 812                                        struct mmc_data *data,
 813                                        struct scatterlist *sgl)
 814 {
 815         int blksz, nblk, dma_ch;
 816
 817         dma_ch = host->dma_ch;
 818         if (data->flags & MMC_DATA_WRITE) {
 819                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 820                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 821                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 822                         sg_dma_address(sgl), 0, 0);
 823         } else {
 824                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 825                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 826                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 827                         sg_dma_address(sgl), 0, 0);
 828         }
 829
 830         blksz = host->data->blksz;
 831         nblk = sg_dma_len(sgl) / blksz;
 832
 833         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 834                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 835                         mmc_omap_get_dma_sync_dev(host, data),
 836                         !(data->flags & MMC_DATA_WRITE));
 837
 838         omap_start_dma(dma_ch);
 839 }
 840
 841 /*
 842  * DMA call back function
 843  */
 844 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 845 {
 846         struct mmc_omap_host *host = data;
 847
 848         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 849                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 850
 851         if (host->dma_ch < 0)
 852                 return;
 853
 854         host->dma_sg_idx++;
 855         if (host->dma_sg_idx < host->dma_len) {
 856                 /* Fire up the next transfer. */
 857                 mmc_omap_config_dma_params(host, host->data,
 858                                            host->data->sg + host->dma_sg_idx);
 859                 return;
 860         }
 861
 862         omap_free_dma(host->dma_ch);
 863         host->dma_ch = -1;
 864         /*
 865          * DMA Callback: run in interrupt context.
 866          * mutex_unlock will throw a kernel warning if used.
 867          */
 868         up(&host->sem);
 869 }
 870
 871 /*
 872  * Routine to configure and start DMA for the MMC card
 873  */
 874 static int
 875 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 876 {
 877         int dma_ch = 0, ret = 0, err = 1, i;
 878         struct mmc_data *data = req->data;
 879
 880         /* Sanity check: all the SG entries must be aligned by block size. */
 881         for (i = 0; i < data->sg_len; i++) {
 882                 struct scatterlist *sgl;
 883
 884                 sgl = data->sg + i;
 885                 if (sgl->length % data->blksz)
 886                         return -EINVAL;
 887         }
 888         if ((data->blksz % 4) != 0)
 889                 /* REVISIT: The MMC buffer increments only when MSB is written.
 890                  * Return error for blksz which is non multiple of four.
 891                  */
 892                 return -EINVAL;
 893
 894         /*
 895          * If for some reason the DMA transfer is still active,
 896          * we wait for timeout period and free the dma
 897          */
 898         if (host->dma_ch != -1) {
 899                 set_current_state(TASK_UNINTERRUPTIBLE);
 900                 schedule_timeout(100);
 901                 if (down_trylock(&host->sem)) {
 902                         omap_free_dma(host->dma_ch);
 903                         host->dma_ch = -1;
 904                         up(&host->sem);
 905                         return err;
 906                 }
 907         } else {
 908                 if (down_trylock(&host->sem))
 909                         return err;
 910         }
 911
 912         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 913                                mmc_omap_dma_cb,host, &dma_ch);
 914         if (ret != 0) {
 915                 dev_err(mmc_dev(host->mmc),
 916                         "%s: omap_request_dma() failed with %d\n",
 917                         mmc_hostname(host->mmc), ret);
 918                 return ret;
 919         }
 920
 921         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 922                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 923         host->dma_ch = dma_ch;
 924         host->dma_sg_idx = 0;
 925
 926         mmc_omap_config_dma_params(host, data, data->sg);
 927
 928         return 0;
 929 }
 930
 931 static void set_data_timeout(struct mmc_omap_host *host,
 932                              struct mmc_request *req)
 933 {
 934         unsigned int timeout, cycle_ns;
 935         uint32_t reg, clkd, dto = 0;
 936
 937         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 938         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 939         if (clkd == 0)
 940                 clkd = 1;
 941
 942         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 943         timeout = req->data->timeout_ns / cycle_ns;
 944         timeout += req->data->timeout_clks;
 945         if (timeout) {
 946                 while ((timeout & 0x80000000) == 0) {
 947                         dto += 1;
 948                         timeout <<= 1;
 949                 }
 950                 dto = 31 - dto;
 951                 timeout <<= 1;
 952                 if (timeout && dto)
 953                         dto += 1;
 954                 if (dto >= 13)
 955                         dto -= 13;
 956                 else
 957                         dto = 0;
 958                 if (dto > 14)
 959                         dto = 14;
 960         }
 961
 962         reg &= ~DTO_MASK;
 963         reg |= dto << DTO_SHIFT;
 964         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 965 }
 966
 967 /*
 968  * Configure block length for MMC/SD cards and initiate the transfer.
 969  */
 970 static int
 971 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 972 {
 973         int ret;
 974         host->data = req->data;
 975
 976         if (req->data == NULL) {
 977                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 978                 return 0;
 979         }
 980
 981         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 982                                         | (req->data->blocks << 16));
 983         set_data_timeout(host, req);
 984
 985         if (host->use_dma) {
 986                 ret = mmc_omap_start_dma_transfer(host, req);
 987                 if (ret != 0) {
 988                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 989                         return ret;
 990                 }
 991         }
 992         return 0;
 993 }
 994
 995 static int omap_mmc_enable(struct mmc_host *mmc)
 996 {
 997         struct mmc_omap_host *host = mmc_priv(mmc);
 998         int err;
 999
1000         err = clk_enable(host->fclk);
1001         if (err)
1002                 return err;
1003         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1004         omap_mmc_restore_ctx(host);
1005         return 0;
1006 }
1007
1008 static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1009 {
1010         struct mmc_omap_host *host = mmc_priv(mmc);
1011
1012         omap_mmc_save_ctx(host);
1013         clk_disable(host->fclk);
1014         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1015         return 0;
1016 }
1017
1018 /*
1019  * Request function. for read/write operation
1020  */
1021 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1022 {
1023         struct mmc_omap_host *host = mmc_priv(mmc);
1024         int err;
1025
1026         WARN_ON(host->mrq != NULL);
1027         host->mrq = req;
1028         err = mmc_omap_prepare_data(host, req);
1029         if (err) {
1030                 req->cmd->error = err;
1031                 if (req->data)
1032                         req->data->error = err;
1033                 host->mrq = NULL;
1034                 mmc_request_done(mmc, req);
1035                 return;
1036         }
1037
1038         mmc_omap_start_command(host, req->cmd, req->data);
1039 }
1040
1041
1042 /* Routine to configure clock values. Exposed API to core */
1043 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1044 {
1045         struct mmc_omap_host *host = mmc_priv(mmc);
1046         u16 dsor = 0;
1047         unsigned long regval;
1048         unsigned long timeout;
1049         u32 con;
1050         int do_send_init_stream = 0;
1051
1052         mmc_host_enable(host->mmc);
1053
1054         if (ios->power_mode != host->power_mode) {
1055                 switch (ios->power_mode) {
1056                 case MMC_POWER_OFF:
1057                         mmc_slot(host).set_power(host->dev, host->slot_id,
1058                                                  0, 0);
1059                         break;
1060                 case MMC_POWER_UP:
1061                         mmc_slot(host).set_power(host->dev, host->slot_id,
1062                                                  1, ios->vdd);
1063                         break;
1064                 case MMC_POWER_ON:
1065                         do_send_init_stream = 1;
1066                         break;
1067                 }
1068                 host->power_mode = ios->power_mode;
1069         }
1070
1071         con = OMAP_HSMMC_READ(host->base, CON);
1072         switch (mmc->ios.bus_width) {
1073         case MMC_BUS_WIDTH_8:
1074                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1075                 break;
1076         case MMC_BUS_WIDTH_4:
1077                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1078                 OMAP_HSMMC_WRITE(host->base, HCTL,
1079                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1080                 break;
1081         case MMC_BUS_WIDTH_1:
1082                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1083                 OMAP_HSMMC_WRITE(host->base, HCTL,
1084                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1085                 break;
1086         }
1087
1088         if (host->id == OMAP_MMC1_DEVID) {
1089                 /* Only MMC1 can interface at 3V without some flavor
1090                  * of external transceiver; but they all handle 1.8V.
1091                  */
1092                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1093                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1094                                 /*
1095                                  * The mmc_select_voltage fn of the core does
1096                                  * not seem to set the power_mode to
1097                                  * MMC_POWER_UP upon recalculating the voltage.
1098                                  * vdd 1.8v.
1099                                  */
1100                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1101                                         dev_dbg(mmc_dev(host->mmc),
1102                                                 "Switch operation failed\n");
1103                 }
1104         }
1105
1106         if (ios->clock) {
1107                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1108                 if (dsor < 1)
1109                         dsor = 1;
1110
1111                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1112                         dsor++;
1113
1114                 if (dsor > 250)
1115                         dsor = 250;
1116         }
1117         omap_mmc_stop_clock(host);
1118         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1119         regval = regval & ~(CLKD_MASK);
1120         regval = regval | (dsor << 6) | (DTO << 16);
1121         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1122         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1123                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1124
1125         /* Wait till the ICS bit is set */
1126         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1127         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1128                 && time_before(jiffies, timeout))
1129                 msleep(1);
1130
1131         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1132                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1133
1134         if (do_send_init_stream)
1135                 send_init_stream(host);
1136
1137         con = OMAP_HSMMC_READ(host->base, CON);
1138         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1139                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1140         else
1141                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1142
1143         mmc_host_lazy_disable(host->mmc);
1144 }
1145
1146 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1147 {
1148         struct mmc_omap_host *host = mmc_priv(mmc);
1149         struct omap_mmc_platform_data *pdata = host->pdata;
1150
1151         if (!pdata->slots[0].card_detect)
1152                 return -ENOSYS;
1153         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
1154 }
1155
1156 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1157 {
1158         struct mmc_omap_host *host = mmc_priv(mmc);
1159         struct omap_mmc_platform_data *pdata = host->pdata;
1160
1161         if (!pdata->slots[0].get_ro)
1162                 return -ENOSYS;
1163         return pdata->slots[0].get_ro(host->dev, 0);
1164 }
1165
1166 static void omap_hsmmc_init(struct mmc_omap_host *host)
1167 {
1168         u32 hctl, capa, value;
1169
1170         /* Only MMC1 supports 3.0V */
1171         if (host->id == OMAP_MMC1_DEVID) {
1172                 hctl = SDVS30;
1173                 capa = VS30 | VS18;
1174         } else {
1175                 hctl = SDVS18;
1176                 capa = VS18;
1177         }
1178
1179         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1180         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1181
1182         value = OMAP_HSMMC_READ(host->base, CAPA);
1183         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1184
1185         /* Set the controller to AUTO IDLE mode */
1186         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1187         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1188
1189         /* Set SD bus power bit */
1190         set_sd_bus_power(host);
1191 }
1192
1193 static struct mmc_host_ops mmc_omap_ops = {
1194         .enable = omap_mmc_enable,
1195         .disable = omap_mmc_disable,
1196         .request = omap_mmc_request,
1197         .set_ios = omap_mmc_set_ios,
1198         .get_cd = omap_hsmmc_get_cd,
1199         .get_ro = omap_hsmmc_get_ro,
1200         /* NYET -- enable_sdio_irq */
1201 };
1202
1203 #ifdef CONFIG_DEBUG_FS
1204
1205 static int mmc_regs_show(struct seq_file *s, void *data)
1206 {
1207         struct mmc_host *mmc = s->private;
1208         struct mmc_omap_host *host = mmc_priv(mmc);
1209         struct omap_mmc_platform_data *pdata = host->pdata;
1210         int context_loss = 0;
1211
1212         if (pdata->get_context_loss_count)
1213                 context_loss = pdata->get_context_loss_count(host->dev);
1214
1215         seq_printf(s, "mmc%d:\n"
1216                         " enabled:\t%d\n"
1217                         " nesting_cnt:\t%d\n"
1218                         " ctx_loss:\t%d:%d\n"
1219                         "\nregs:\n",
1220                         mmc->index, mmc->enabled ? 1 : 0, mmc->nesting_cnt,
1221                         host->context_loss, context_loss);
1222
1223         if (clk_enable(host->fclk) != 0) {
1224                 seq_printf(s, "can't read the regs\n");
1225                 goto err;
1226         }
1227
1228         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1229                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1230         seq_printf(s, "CON:\t\t0x%08x\n",
1231                         OMAP_HSMMC_READ(host->base, CON));
1232         seq_printf(s, "HCTL:\t\t0x%08x\n",
1233                         OMAP_HSMMC_READ(host->base, HCTL));
1234         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1235                         OMAP_HSMMC_READ(host->base, SYSCTL));
1236         seq_printf(s, "IE:\t\t0x%08x\n",
1237                         OMAP_HSMMC_READ(host->base, IE));
1238         seq_printf(s, "ISE:\t\t0x%08x\n",
1239                         OMAP_HSMMC_READ(host->base, ISE));
1240         seq_printf(s, "CAPA:\t\t0x%08x\n",
1241                         OMAP_HSMMC_READ(host->base, CAPA));
1242
1243         clk_disable(host->fclk);
1244 err:
1245         return 0;
1246 }
1247
1248 static int mmc_regs_open(struct inode *inode, struct file *file)
1249 {
1250         return single_open(file, mmc_regs_show, inode->i_private);
1251 }
1252
1253 static const struct file_operations mmc_regs_fops = {
1254         .open           = mmc_regs_open,
1255         .read           = seq_read,
1256         .llseek         = seq_lseek,
1257         .release        = single_release,
1258 };
1259
1260 static void omap_mmc_debugfs(struct mmc_host *mmc)
1261 {
1262         if (mmc->debugfs_root)
1263                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1264                         mmc, &mmc_regs_fops);
1265 }
1266
1267 #else
1268
1269 static void omap_mmc_debugfs(struct mmc_host *mmc)
1270 {
1271 }
1272
1273 #endif
1274
1275 static int __init omap_mmc_probe(struct platform_device *pdev)
1276 {
1277         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1278         struct mmc_host *mmc;
1279         struct mmc_omap_host *host = NULL;
1280         struct resource *res;
1281         int ret = 0, irq;
1282
1283         if (pdata == NULL) {
1284                 dev_err(&pdev->dev, "Platform Data is missing\n");
1285                 return -ENXIO;
1286         }
1287
1288         if (pdata->nr_slots == 0) {
1289                 dev_err(&pdev->dev, "No Slots\n");
1290                 return -ENXIO;
1291         }
1292
1293         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294         irq = platform_get_irq(pdev, 0);
1295         if (res == NULL || irq < 0)
1296                 return -ENXIO;
1297
1298         res = request_mem_region(res->start, res->end - res->start + 1,
1299                                                         pdev->name);
1300         if (res == NULL)
1301                 return -EBUSY;
1302
1303         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1304         if (!mmc) {
1305                 ret = -ENOMEM;
1306                 goto err;
1307         }
1308
1309         host            = mmc_priv(mmc);
1310         host->mmc       = mmc;
1311         host->pdata     = pdata;
1312         host->dev       = &pdev->dev;
1313         host->use_dma   = 1;
1314         host->dev->dma_mask = &pdata->dma_mask;
1315         host->dma_ch    = -1;
1316         host->irq       = irq;
1317         host->id        = pdev->id;
1318         host->slot_id   = 0;
1319         host->mapbase   = res->start;
1320         host->base      = ioremap(host->mapbase, SZ_4K);
1321         host->power_mode = -1;
1322
1323         platform_set_drvdata(pdev, host);
1324         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1325
1326         mmc->ops        = &mmc_omap_ops;
1327         mmc->f_min      = 400000;
1328         mmc->f_max      = 52000000;
1329
1330         sema_init(&host->sem, 1);
1331
1332         host->iclk = clk_get(&pdev->dev, "ick");
1333         if (IS_ERR(host->iclk)) {
1334                 ret = PTR_ERR(host->iclk);
1335                 host->iclk = NULL;
1336                 goto err1;
1337         }
1338         host->fclk = clk_get(&pdev->dev, "fck");
1339         if (IS_ERR(host->fclk)) {
1340                 ret = PTR_ERR(host->fclk);
1341                 host->fclk = NULL;
1342                 clk_put(host->iclk);
1343                 goto err1;
1344         }
1345
1346         omap_mmc_save_ctx(host);
1347
1348         mmc->caps |= MMC_CAP_DISABLE;
1349         mmc_set_disable_delay(mmc, 100);
1350         if (mmc_host_enable(host->mmc) != 0) {
1351                 clk_put(host->iclk);
1352                 clk_put(host->fclk);
1353                 goto err1;
1354         }
1355
1356         if (clk_enable(host->iclk) != 0) {
1357                 mmc_host_disable(host->mmc);
1358                 clk_put(host->iclk);
1359                 clk_put(host->fclk);
1360                 goto err1;
1361         }
1362
1363         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1364         /*
1365          * MMC can still work without debounce clock.
1366          */
1367         if (IS_ERR(host->dbclk))
1368                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1369         else
1370                 if (clk_enable(host->dbclk) != 0)
1371                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1372                                                         " clk failed\n");
1373                 else
1374                         host->dbclk_enabled = 1;
1375
1376         /* Since we do only SG emulation, we can have as many segs
1377          * as we want. */
1378         mmc->max_phys_segs = 1024;
1379         mmc->max_hw_segs = 1024;
1380
1381         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1382         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1383         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1384         mmc->max_seg_size = mmc->max_req_size;
1385
1386         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1387
1388         if (pdata->slots[host->slot_id].wires >= 8)
1389                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1390         else if (pdata->slots[host->slot_id].wires >= 4)
1391                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1392
1393         omap_hsmmc_init(host);
1394
1395         /* Select DMA lines */
1396         switch (host->id) {
1397         case OMAP_MMC1_DEVID:
1398                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1399                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1400                 break;
1401         case OMAP_MMC2_DEVID:
1402                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1403                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1404                 break;
1405         case OMAP_MMC3_DEVID:
1406                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1407                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1408                 break;
1409         default:
1410                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1411                 goto err_irq;
1412         }
1413
1414         /* Request IRQ for MMC operations */
1415         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1416                         mmc_hostname(mmc), host);
1417         if (ret) {
1418                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1419                 goto err_irq;
1420         }
1421
1422         /* initialize power supplies, gpios, etc */
1423         if (pdata->init != NULL) {
1424                 if (pdata->init(&pdev->dev) != 0) {
1425                         dev_dbg(mmc_dev(host->mmc), "late init error\n");
1426                         goto err_irq_cd_init;
1427                 }
1428         }
1429         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1430
1431         /* Request IRQ for card detect */
1432         if ((mmc_slot(host).card_detect_irq)) {
1433                 ret = request_irq(mmc_slot(host).card_detect_irq,
1434                                   omap_mmc_cd_handler,
1435                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1436                                           | IRQF_DISABLED,
1437                                   mmc_hostname(mmc), host);
1438                 if (ret) {
1439                         dev_dbg(mmc_dev(host->mmc),
1440                                 "Unable to grab MMC CD IRQ\n");
1441                         goto err_irq_cd;
1442                 }
1443         }
1444
1445         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1446         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1447
1448         mmc_host_lazy_disable(host->mmc);
1449
1450         mmc_add_host(mmc);
1451
1452         if (host->pdata->slots[host->slot_id].name != NULL) {
1453                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1454                 if (ret < 0)
1455                         goto err_slot_name;
1456         }
1457         if (mmc_slot(host).card_detect_irq &&
1458             host->pdata->slots[host->slot_id].get_cover_state) {
1459                 ret = device_create_file(&mmc->class_dev,
1460                                         &dev_attr_cover_switch);
1461                 if (ret < 0)
1462                         goto err_cover_switch;
1463         }
1464
1465         omap_mmc_debugfs(mmc);
1466
1467         return 0;
1468
1469 err_cover_switch:
1470         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1471 err_slot_name:
1472         mmc_remove_host(mmc);
1473 err_irq_cd:
1474         free_irq(mmc_slot(host).card_detect_irq, host);
1475 err_irq_cd_init:
1476         free_irq(host->irq, host);
1477 err_irq:
1478         mmc_host_disable(host->mmc);
1479         clk_disable(host->iclk);
1480         clk_put(host->fclk);
1481         clk_put(host->iclk);
1482         if (host->dbclk_enabled) {
1483                 clk_disable(host->dbclk);
1484                 clk_put(host->dbclk);
1485         }
1486
1487 err1:
1488         iounmap(host->base);
1489 err:
1490         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1491         release_mem_region(res->start, res->end - res->start + 1);
1492         if (host)
1493                 mmc_free_host(mmc);
1494         return ret;
1495 }
1496
1497 static int omap_mmc_remove(struct platform_device *pdev)
1498 {
1499         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1500         struct resource *res;
1501
1502         if (host) {
1503                 mmc_host_enable(host->mmc);
1504                 mmc_remove_host(host->mmc);
1505                 if (host->pdata->cleanup)
1506                         host->pdata->cleanup(&pdev->dev);
1507                 free_irq(host->irq, host);
1508                 if (mmc_slot(host).card_detect_irq)
1509                         free_irq(mmc_slot(host).card_detect_irq, host);
1510                 flush_scheduled_work();
1511
1512                 mmc_host_disable(host->mmc);
1513                 clk_disable(host->iclk);
1514                 clk_put(host->fclk);
1515                 clk_put(host->iclk);
1516                 if (host->dbclk_enabled) {
1517                         clk_disable(host->dbclk);
1518                         clk_put(host->dbclk);
1519                 }
1520
1521                 mmc_free_host(host->mmc);
1522                 iounmap(host->base);
1523         }
1524
1525         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1526         if (res)
1527                 release_mem_region(res->start, res->end - res->start + 1);
1528         platform_set_drvdata(pdev, NULL);
1529
1530         return 0;
1531 }
1532
1533 #ifdef CONFIG_PM
1534 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1535 {
1536         int ret = 0;
1537         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1538
1539         if (host && host->suspended)
1540                 return 0;
1541
1542         if (host) {
1543                 host->suspended = 1;
1544                 if (host->pdata->suspend) {
1545                         ret = host->pdata->suspend(&pdev->dev,
1546                                                         host->slot_id);
1547                         if (ret) {
1548                                 dev_dbg(mmc_dev(host->mmc),
1549                                         "Unable to handle MMC board"
1550                                         " level suspend\n");
1551                                 host->suspended = 0;
1552                                 return ret;
1553                         }
1554                 }
1555                 cancel_work_sync(&host->mmc_carddetect_work);
1556                 mmc_host_enable(host->mmc);
1557                 ret = mmc_suspend_host(host->mmc, state);
1558                 if (ret == 0) {
1559                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1560                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1561
1562
1563                         OMAP_HSMMC_WRITE(host->base, HCTL,
1564                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1565                         mmc_host_disable(host->mmc);
1566                         clk_disable(host->iclk);
1567                         clk_disable(host->dbclk);
1568                 } else {
1569                         host->suspended = 0;
1570                         if (host->pdata->resume) {
1571                                 ret = host->pdata->resume(&pdev->dev,
1572                                                           host->slot_id);
1573                                 if (ret)
1574                                         dev_dbg(mmc_dev(host->mmc),
1575                                                 "Unmask interrupt failed\n");
1576                         }
1577                         mmc_host_disable(host->mmc);
1578                 }
1579
1580         }
1581         return ret;
1582 }
1583
1584 /* Routine to resume the MMC device */
1585 static int omap_mmc_resume(struct platform_device *pdev)
1586 {
1587         int ret = 0;
1588         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1589
1590         if (host && !host->suspended)
1591                 return 0;
1592
1593         if (host) {
1594                 ret = clk_enable(host->iclk);
1595                 if (ret)
1596                         goto clk_en_err;
1597
1598                 if (clk_enable(host->dbclk) != 0)
1599                         dev_dbg(mmc_dev(host->mmc),
1600                                         "Enabling debounce clk failed\n");
1601
1602                 if (mmc_host_enable(host->mmc) != 0) {
1603                         clk_disable(host->iclk);
1604                         goto clk_en_err;
1605                 }
1606
1607                 omap_hsmmc_init(host);
1608
1609                 if (host->pdata->resume) {
1610                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1611                         if (ret)
1612                                 dev_dbg(mmc_dev(host->mmc),
1613                                         "Unmask interrupt failed\n");
1614                 }
1615
1616                 /* Notify the core to resume the host */
1617                 ret = mmc_resume_host(host->mmc);
1618                 if (ret == 0)
1619                         host->suspended = 0;
1620                 mmc_host_lazy_disable(host->mmc);
1621         }
1622
1623         return ret;
1624
1625 clk_en_err:
1626         dev_dbg(mmc_dev(host->mmc),
1627                 "Failed to enable MMC clocks during resume\n");
1628         return ret;
1629 }
1630
1631 #else
1632 #define omap_mmc_suspend        NULL
1633 #define omap_mmc_resume         NULL
1634 #endif
1635
1636 static struct platform_driver omap_mmc_driver = {
1637         .remove         = omap_mmc_remove,
1638         .suspend        = omap_mmc_suspend,
1639         .resume         = omap_mmc_resume,
1640         .driver         = {
1641                 .name = DRIVER_NAME,
1642                 .owner = THIS_MODULE,
1643         },
1644 };
1645
1646 static int __init omap_mmc_init(void)
1647 {
1648         /* Register the MMC driver */
1649         return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
1650 }
1651
1652 static void __exit omap_mmc_cleanup(void)
1653 {
1654         /* Unregister MMC driver */
1655         platform_driver_unregister(&omap_mmc_driver);
1656 }
1657
1658 module_init(omap_mmc_init);
1659 module_exit(omap_mmc_cleanup);
1660
1661 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1662 MODULE_LICENSE("GPL");
1663 MODULE_ALIAS("platform:" DRIVER_NAME);
1664 MODULE_AUTHOR("Texas Instruments Inc");