2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_device.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/mmc.h>
36 #include <linux/semaphore.h>
37 #include <linux/gpio.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSCONFIG 0x0010
48 #define OMAP_HSMMC_SYSSTATUS 0x0014
49 #define OMAP_HSMMC_CON 0x002C
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_HCTL 0x0128
59 #define OMAP_HSMMC_SYSCTL 0x012C
60 #define OMAP_HSMMC_STAT 0x0130
61 #define OMAP_HSMMC_IE 0x0134
62 #define OMAP_HSMMC_ISE 0x0138
63 #define OMAP_HSMMC_CAPA 0x0140
65 #define VS18 (1 << 26)
66 #define VS30 (1 << 25)
67 #define SDVS18 (0x5 << 9)
68 #define SDVS30 (0x6 << 9)
69 #define SDVS33 (0x7 << 9)
70 #define SDVS_MASK 0x00000E00
71 #define SDVSCLR 0xFFFFF1FF
72 #define SDVSDET 0x00000400
79 #define CLKD_MASK 0x0000FFC0
81 #define DTO_MASK 0x000F0000
83 #define INT_EN_MASK 0x307F0033
84 #define BWR_ENABLE (1 << 4)
85 #define BRR_ENABLE (1 << 5)
86 #define DTO_ENABLE (1 << 20)
87 #define INIT_STREAM (1 << 1)
88 #define DP_SELECT (1 << 21)
93 #define FOUR_BIT (1 << 1)
100 #define CMD_TIMEOUT (1 << 16)
101 #define DATA_TIMEOUT (1 << 20)
102 #define CMD_CRC (1 << 17)
103 #define DATA_CRC (1 << 21)
104 #define CARD_ERR (1 << 28)
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
111 #define RESETDONE (1 << 0)
113 #define MMC_AUTOSUSPEND_DELAY 100
114 #define MMC_TIMEOUT_MS 20
115 #define OMAP_MMC_MIN_CLOCK 400000
116 #define OMAP_MMC_MAX_CLOCK 52000000
117 #define DRIVER_NAME "omap_hsmmc"
120 * One controller can have multiple slots, like on some omap boards using
121 * omap.c controller driver. Luckily this is not currently done on any known
122 * omap_hsmmc.c device.
124 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
127 * MMC Host controller read/write API's
129 #define OMAP_HSMMC_READ(base, reg) \
130 __raw_readl((base) + OMAP_HSMMC_##reg)
132 #define OMAP_HSMMC_WRITE(base, reg, val) \
133 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135 struct omap_hsmmc_next {
136 unsigned int dma_len;
140 struct omap_hsmmc_host {
142 struct mmc_host *mmc;
143 struct mmc_request *mrq;
144 struct mmc_command *cmd;
145 struct mmc_data *data;
149 * vcc == configured supply
150 * vcc_aux == optional
151 * - MMC1, supply for DAT4..DAT7
152 * - MMC2/MMC2, external level shifter voltage supply, for
153 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
155 struct regulator *vcc;
156 struct regulator *vcc_aux;
158 resource_size_t mapbase;
159 spinlock_t irq_lock; /* Prevent races with irq handler */
160 unsigned int dma_len;
161 unsigned int dma_sg_idx;
162 unsigned char bus_mode;
163 unsigned char power_mode;
169 int dma_line_tx, dma_line_rx;
178 struct omap_hsmmc_next next_data;
180 struct omap_mmc_platform_data *pdata;
183 static int omap_hsmmc_card_detect(struct device *dev, int slot)
185 struct omap_mmc_platform_data *mmc = dev->platform_data;
187 /* NOTE: assumes card detect signal is active-low */
188 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
191 static int omap_hsmmc_get_wp(struct device *dev, int slot)
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
195 /* NOTE: assumes write protect signal is active-high */
196 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
199 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
203 /* NOTE: assumes card detect signal is active-low */
204 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
209 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
211 struct omap_mmc_platform_data *mmc = dev->platform_data;
213 disable_irq(mmc->slots[0].card_detect_irq);
217 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
221 enable_irq(mmc->slots[0].card_detect_irq);
227 #define omap_hsmmc_suspend_cdirq NULL
228 #define omap_hsmmc_resume_cdirq NULL
232 #ifdef CONFIG_REGULATOR
234 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
237 struct omap_hsmmc_host *host =
238 platform_get_drvdata(to_platform_device(dev));
242 * If we don't see a Vcc regulator, assume it's a fixed
243 * voltage always-on regulator.
248 * With DT, never turn OFF the regulator. This is because
249 * the pbias cell programming support is still missing when
250 * booting with Device tree
252 if (dev->of_node && !vdd)
255 if (mmc_slot(host).before_set_reg)
256 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
259 * Assume Vcc regulator is used only to power the card ... OMAP
260 * VDDS is used to power the pins, optionally with a transceiver to
261 * support cards using voltages other than VDDS (1.8V nominal). When a
262 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
264 * In some cases this regulator won't support enable/disable;
265 * e.g. it's a fixed rail for a WLAN chip.
267 * In other cases vcc_aux switches interface power. Example, for
268 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
269 * chips/cards need an interface voltage rail too.
272 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
273 /* Enable interface voltage rail, if needed */
274 if (ret == 0 && host->vcc_aux) {
275 ret = regulator_enable(host->vcc_aux);
277 ret = mmc_regulator_set_ocr(host->mmc,
281 /* Shut down the rail */
283 ret = regulator_disable(host->vcc_aux);
285 /* Then proceed to shut down the local regulator */
286 ret = mmc_regulator_set_ocr(host->mmc,
291 if (mmc_slot(host).after_set_reg)
292 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
297 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
299 struct regulator *reg;
302 mmc_slot(host).set_power = omap_hsmmc_set_power;
304 reg = regulator_get(host->dev, "vmmc");
306 dev_dbg(host->dev, "vmmc regulator missing\n");
309 ocr_value = mmc_regulator_get_ocrmask(reg);
310 if (!mmc_slot(host).ocr_mask) {
311 mmc_slot(host).ocr_mask = ocr_value;
313 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
314 dev_err(host->dev, "ocrmask %x is not supported\n",
315 mmc_slot(host).ocr_mask);
316 mmc_slot(host).ocr_mask = 0;
321 /* Allow an aux regulator */
322 reg = regulator_get(host->dev, "vmmc_aux");
323 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
325 /* For eMMC do not power off when not in sleep state */
326 if (mmc_slot(host).no_regulator_off_init)
329 * UGLY HACK: workaround regulator framework bugs.
330 * When the bootloader leaves a supply active, it's
331 * initialized with zero usecount ... and we can't
332 * disable it without first enabling it. Until the
333 * framework is fixed, we need a workaround like this
334 * (which is safe for MMC, but not in general).
336 if (regulator_is_enabled(host->vcc) > 0 ||
337 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
338 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
340 mmc_slot(host).set_power(host->dev, host->slot_id,
342 mmc_slot(host).set_power(host->dev, host->slot_id,
350 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
352 regulator_put(host->vcc);
353 regulator_put(host->vcc_aux);
354 mmc_slot(host).set_power = NULL;
357 static inline int omap_hsmmc_have_reg(void)
364 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373 static inline int omap_hsmmc_have_reg(void)
380 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
384 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
385 if (pdata->slots[0].cover)
386 pdata->slots[0].get_cover_state =
387 omap_hsmmc_get_cover_state;
389 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
390 pdata->slots[0].card_detect_irq =
391 gpio_to_irq(pdata->slots[0].switch_pin);
392 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
395 ret = gpio_direction_input(pdata->slots[0].switch_pin);
399 pdata->slots[0].switch_pin = -EINVAL;
401 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
402 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
403 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
406 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
410 pdata->slots[0].gpio_wp = -EINVAL;
415 gpio_free(pdata->slots[0].gpio_wp);
417 if (gpio_is_valid(pdata->slots[0].switch_pin))
419 gpio_free(pdata->slots[0].switch_pin);
423 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
425 if (gpio_is_valid(pdata->slots[0].gpio_wp))
426 gpio_free(pdata->slots[0].gpio_wp);
427 if (gpio_is_valid(pdata->slots[0].switch_pin))
428 gpio_free(pdata->slots[0].switch_pin);
432 * Start clock to the card
434 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
436 OMAP_HSMMC_WRITE(host->base, SYSCTL,
437 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
441 * Stop clock to the card
443 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
445 OMAP_HSMMC_WRITE(host->base, SYSCTL,
446 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
447 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
448 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
451 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
452 struct mmc_command *cmd)
454 unsigned int irq_mask;
457 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
459 irq_mask = INT_EN_MASK;
461 /* Disable timeout for erases */
462 if (cmd->opcode == MMC_ERASE)
463 irq_mask &= ~DTO_ENABLE;
465 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
466 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
467 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
470 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
472 OMAP_HSMMC_WRITE(host->base, ISE, 0);
473 OMAP_HSMMC_WRITE(host->base, IE, 0);
474 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
477 /* Calculate divisor for the given clock frequency */
478 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
483 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
491 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
493 struct mmc_ios *ios = &host->mmc->ios;
494 unsigned long regval;
495 unsigned long timeout;
497 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
499 omap_hsmmc_stop_clock(host);
501 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
502 regval = regval & ~(CLKD_MASK | DTO_MASK);
503 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
504 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
505 OMAP_HSMMC_WRITE(host->base, SYSCTL,
506 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
508 /* Wait till the ICS bit is set */
509 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
510 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
511 && time_before(jiffies, timeout))
514 omap_hsmmc_start_clock(host);
517 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
519 struct mmc_ios *ios = &host->mmc->ios;
522 con = OMAP_HSMMC_READ(host->base, CON);
523 if (ios->timing == MMC_TIMING_UHS_DDR50)
524 con |= DDR; /* configure in DDR mode */
527 switch (ios->bus_width) {
528 case MMC_BUS_WIDTH_8:
529 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
531 case MMC_BUS_WIDTH_4:
532 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
533 OMAP_HSMMC_WRITE(host->base, HCTL,
534 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
536 case MMC_BUS_WIDTH_1:
537 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
538 OMAP_HSMMC_WRITE(host->base, HCTL,
539 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
544 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
546 struct mmc_ios *ios = &host->mmc->ios;
549 con = OMAP_HSMMC_READ(host->base, CON);
550 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
551 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
553 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
559 * Restore the MMC host context, if it was lost as result of a
560 * power state change.
562 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
564 struct mmc_ios *ios = &host->mmc->ios;
565 struct omap_mmc_platform_data *pdata = host->pdata;
566 int context_loss = 0;
568 unsigned long timeout;
570 if (pdata->get_context_loss_count) {
571 context_loss = pdata->get_context_loss_count(host->dev);
572 if (context_loss < 0)
576 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
577 context_loss == host->context_loss ? "not " : "");
578 if (host->context_loss == context_loss)
581 /* Wait for hardware reset */
582 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
583 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
584 && time_before(jiffies, timeout))
587 /* Do software reset */
588 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
589 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
590 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
591 && time_before(jiffies, timeout))
594 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
595 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
597 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
598 if (host->power_mode != MMC_POWER_OFF &&
599 (1 << ios->vdd) <= MMC_VDD_23_24)
609 OMAP_HSMMC_WRITE(host->base, HCTL,
610 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
612 OMAP_HSMMC_WRITE(host->base, CAPA,
613 OMAP_HSMMC_READ(host->base, CAPA) | capa);
615 OMAP_HSMMC_WRITE(host->base, HCTL,
616 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
618 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
619 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
620 && time_before(jiffies, timeout))
623 omap_hsmmc_disable_irq(host);
625 /* Do not initialize card-specific things if the power is off */
626 if (host->power_mode == MMC_POWER_OFF)
629 omap_hsmmc_set_bus_width(host);
631 omap_hsmmc_set_clock(host);
633 omap_hsmmc_set_bus_mode(host);
636 host->context_loss = context_loss;
638 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
643 * Save the MMC host context (store the number of power state changes so far).
645 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
647 struct omap_mmc_platform_data *pdata = host->pdata;
650 if (pdata->get_context_loss_count) {
651 context_loss = pdata->get_context_loss_count(host->dev);
652 if (context_loss < 0)
654 host->context_loss = context_loss;
660 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
665 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
672 * Send init stream sequence to card
673 * before sending IDLE command
675 static void send_init_stream(struct omap_hsmmc_host *host)
678 unsigned long timeout;
680 if (host->protect_card)
683 disable_irq(host->irq);
685 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
686 OMAP_HSMMC_WRITE(host->base, CON,
687 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
688 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
690 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
691 while ((reg != CC) && time_before(jiffies, timeout))
692 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
694 OMAP_HSMMC_WRITE(host->base, CON,
695 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
697 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
698 OMAP_HSMMC_READ(host->base, STAT);
700 enable_irq(host->irq);
704 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
708 if (mmc_slot(host).get_cover_state)
709 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
714 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
717 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
718 struct omap_hsmmc_host *host = mmc_priv(mmc);
720 return sprintf(buf, "%s\n",
721 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
724 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
727 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
730 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
731 struct omap_hsmmc_host *host = mmc_priv(mmc);
733 return sprintf(buf, "%s\n", mmc_slot(host).name);
736 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
739 * Configure the response type and send the cmd.
742 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
743 struct mmc_data *data)
745 int cmdreg = 0, resptype = 0, cmdtype = 0;
747 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
748 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
751 omap_hsmmc_enable_irq(host, cmd);
753 host->response_busy = 0;
754 if (cmd->flags & MMC_RSP_PRESENT) {
755 if (cmd->flags & MMC_RSP_136)
757 else if (cmd->flags & MMC_RSP_BUSY) {
759 host->response_busy = 1;
765 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
766 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
767 * a val of 0x3, rest 0x0.
769 if (cmd == host->mrq->stop)
772 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
775 cmdreg |= DP_SELECT | MSBS | BCE;
776 if (data->flags & MMC_DATA_READ)
785 host->req_in_progress = 1;
787 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
788 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
792 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
794 if (data->flags & MMC_DATA_WRITE)
795 return DMA_TO_DEVICE;
797 return DMA_FROM_DEVICE;
800 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
805 spin_lock_irqsave(&host->irq_lock, flags);
806 host->req_in_progress = 0;
807 dma_ch = host->dma_ch;
808 spin_unlock_irqrestore(&host->irq_lock, flags);
810 omap_hsmmc_disable_irq(host);
811 /* Do not complete the request if DMA is still in progress */
812 if (mrq->data && host->use_dma && dma_ch != -1)
815 mmc_request_done(host->mmc, mrq);
819 * Notify the transfer complete to MMC core
822 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
825 struct mmc_request *mrq = host->mrq;
827 /* TC before CC from CMD6 - don't know why, but it happens */
828 if (host->cmd && host->cmd->opcode == 6 &&
829 host->response_busy) {
830 host->response_busy = 0;
834 omap_hsmmc_request_done(host, mrq);
841 data->bytes_xfered += data->blocks * (data->blksz);
843 data->bytes_xfered = 0;
846 omap_hsmmc_request_done(host, data->mrq);
849 omap_hsmmc_start_command(host, data->stop, NULL);
853 * Notify the core about command completion
856 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
860 if (cmd->flags & MMC_RSP_PRESENT) {
861 if (cmd->flags & MMC_RSP_136) {
862 /* response type 2 */
863 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
864 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
865 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
866 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
868 /* response types 1, 1b, 3, 4, 5, 6 */
869 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
872 if ((host->data == NULL && !host->response_busy) || cmd->error)
873 omap_hsmmc_request_done(host, cmd->mrq);
877 * DMA clean up for command errors
879 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
884 host->data->error = errno;
886 spin_lock_irqsave(&host->irq_lock, flags);
887 dma_ch = host->dma_ch;
889 spin_unlock_irqrestore(&host->irq_lock, flags);
891 if (host->use_dma && dma_ch != -1) {
892 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
894 omap_hsmmc_get_dma_dir(host, host->data));
895 omap_free_dma(dma_ch);
896 host->data->host_cookie = 0;
902 * Readable error output
904 #ifdef CONFIG_MMC_DEBUG
905 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
907 /* --- means reserved bit without definition at documentation */
908 static const char *omap_hsmmc_status_bits[] = {
909 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
910 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
911 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
912 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
918 len = sprintf(buf, "MMC IRQ 0x%x :", status);
921 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
922 if (status & (1 << i)) {
923 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
927 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
930 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
934 #endif /* CONFIG_MMC_DEBUG */
937 * MMC controller internal state machines reset
939 * Used to reset command or data internal state machines, using respectively
940 * SRC or SRD bit of SYSCTL register
941 * Can be called from interrupt context
943 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
947 unsigned long limit = (loops_per_jiffy *
948 msecs_to_jiffies(MMC_TIMEOUT_MS));
950 OMAP_HSMMC_WRITE(host->base, SYSCTL,
951 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
954 * OMAP4 ES2 and greater has an updated reset logic.
955 * Monitor a 0->1 transition first
957 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
958 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
964 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
968 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
969 dev_err(mmc_dev(host->mmc),
970 "Timeout waiting on controller reset in %s\n",
974 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
976 struct mmc_data *data;
977 int end_cmd = 0, end_trans = 0;
979 if (!host->req_in_progress) {
981 OMAP_HSMMC_WRITE(host->base, STAT, status);
982 /* Flush posted write */
983 status = OMAP_HSMMC_READ(host->base, STAT);
984 } while (status & INT_EN_MASK);
989 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
992 omap_hsmmc_dbg_report_irq(host, status);
993 if ((status & CMD_TIMEOUT) ||
994 (status & CMD_CRC)) {
996 if (status & CMD_TIMEOUT) {
997 omap_hsmmc_reset_controller_fsm(host,
999 host->cmd->error = -ETIMEDOUT;
1001 host->cmd->error = -EILSEQ;
1005 if (host->data || host->response_busy) {
1007 omap_hsmmc_dma_cleanup(host,
1009 host->response_busy = 0;
1010 omap_hsmmc_reset_controller_fsm(host, SRD);
1013 if ((status & DATA_TIMEOUT) ||
1014 (status & DATA_CRC)) {
1015 if (host->data || host->response_busy) {
1016 int err = (status & DATA_TIMEOUT) ?
1017 -ETIMEDOUT : -EILSEQ;
1020 omap_hsmmc_dma_cleanup(host, err);
1022 host->mrq->cmd->error = err;
1023 host->response_busy = 0;
1024 omap_hsmmc_reset_controller_fsm(host, SRD);
1028 if (status & CARD_ERR) {
1029 dev_dbg(mmc_dev(host->mmc),
1030 "Ignoring card err CMD%d\n", host->cmd->opcode);
1038 OMAP_HSMMC_WRITE(host->base, STAT, status);
1040 if (end_cmd || ((status & CC) && host->cmd))
1041 omap_hsmmc_cmd_done(host, host->cmd);
1042 if ((end_trans || (status & TC)) && host->mrq)
1043 omap_hsmmc_xfer_done(host, data);
1047 * MMC controller IRQ handler
1049 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1051 struct omap_hsmmc_host *host = dev_id;
1054 status = OMAP_HSMMC_READ(host->base, STAT);
1056 omap_hsmmc_do_irq(host, status);
1057 /* Flush posted write */
1058 status = OMAP_HSMMC_READ(host->base, STAT);
1059 } while (status & INT_EN_MASK);
1064 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1068 OMAP_HSMMC_WRITE(host->base, HCTL,
1069 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1070 for (i = 0; i < loops_per_jiffy; i++) {
1071 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1078 * Switch MMC interface voltage ... only relevant for MMC1.
1080 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1081 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1082 * Some chips, like eMMC ones, use internal transceivers.
1084 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1089 /* Disable the clocks */
1090 pm_runtime_put_sync(host->dev);
1092 clk_disable_unprepare(host->dbclk);
1094 /* Turn the power off */
1095 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1097 /* Turn the power ON with given VDD 1.8 or 3.0v */
1099 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1101 pm_runtime_get_sync(host->dev);
1103 clk_prepare_enable(host->dbclk);
1108 OMAP_HSMMC_WRITE(host->base, HCTL,
1109 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1110 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1113 * If a MMC dual voltage card is detected, the set_ios fn calls
1114 * this fn with VDD bit set for 1.8V. Upon card removal from the
1115 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1117 * Cope with a bit of slop in the range ... per data sheets:
1118 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1119 * but recommended values are 1.71V to 1.89V
1120 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1121 * but recommended values are 2.7V to 3.3V
1123 * Board setup code shouldn't permit anything very out-of-range.
1124 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1125 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1127 if ((1 << vdd) <= MMC_VDD_23_24)
1132 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1133 set_sd_bus_power(host);
1137 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1141 /* Protect the card while the cover is open */
1142 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1144 if (!mmc_slot(host).get_cover_state)
1147 host->reqs_blocked = 0;
1148 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1149 if (host->protect_card) {
1150 dev_info(host->dev, "%s: cover is closed, "
1151 "card is now accessible\n",
1152 mmc_hostname(host->mmc));
1153 host->protect_card = 0;
1156 if (!host->protect_card) {
1157 dev_info(host->dev, "%s: cover is open, "
1158 "card is now inaccessible\n",
1159 mmc_hostname(host->mmc));
1160 host->protect_card = 1;
1166 * irq handler to notify the core about card insertion/removal
1168 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1170 struct omap_hsmmc_host *host = dev_id;
1171 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1174 if (host->suspended)
1177 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1179 if (slot->card_detect)
1180 carddetect = slot->card_detect(host->dev, host->slot_id);
1182 omap_hsmmc_protect_card(host);
1183 carddetect = -ENOSYS;
1187 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1189 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1193 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1194 struct mmc_data *data)
1198 if (data->flags & MMC_DATA_WRITE)
1199 sync_dev = host->dma_line_tx;
1201 sync_dev = host->dma_line_rx;
1205 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1206 struct mmc_data *data,
1207 struct scatterlist *sgl)
1209 int blksz, nblk, dma_ch;
1211 dma_ch = host->dma_ch;
1212 if (data->flags & MMC_DATA_WRITE) {
1213 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1214 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1215 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1216 sg_dma_address(sgl), 0, 0);
1218 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1219 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1220 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1221 sg_dma_address(sgl), 0, 0);
1224 blksz = host->data->blksz;
1225 nblk = sg_dma_len(sgl) / blksz;
1227 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1228 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1229 omap_hsmmc_get_dma_sync_dev(host, data),
1230 !(data->flags & MMC_DATA_WRITE));
1232 omap_start_dma(dma_ch);
1236 * DMA call back function
1238 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1240 struct omap_hsmmc_host *host = cb_data;
1241 struct mmc_data *data;
1242 int dma_ch, req_in_progress;
1243 unsigned long flags;
1245 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1246 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1251 spin_lock_irqsave(&host->irq_lock, flags);
1252 if (host->dma_ch < 0) {
1253 spin_unlock_irqrestore(&host->irq_lock, flags);
1257 data = host->mrq->data;
1259 if (host->dma_sg_idx < host->dma_len) {
1260 /* Fire up the next transfer. */
1261 omap_hsmmc_config_dma_params(host, data,
1262 data->sg + host->dma_sg_idx);
1263 spin_unlock_irqrestore(&host->irq_lock, flags);
1267 if (!data->host_cookie)
1268 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1269 omap_hsmmc_get_dma_dir(host, data));
1271 req_in_progress = host->req_in_progress;
1272 dma_ch = host->dma_ch;
1274 spin_unlock_irqrestore(&host->irq_lock, flags);
1276 omap_free_dma(dma_ch);
1278 /* If DMA has finished after TC, complete the request */
1279 if (!req_in_progress) {
1280 struct mmc_request *mrq = host->mrq;
1283 mmc_request_done(host->mmc, mrq);
1287 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1288 struct mmc_data *data,
1289 struct omap_hsmmc_next *next)
1293 if (!next && data->host_cookie &&
1294 data->host_cookie != host->next_data.cookie) {
1295 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1296 " host->next_data.cookie %d\n",
1297 __func__, data->host_cookie, host->next_data.cookie);
1298 data->host_cookie = 0;
1301 /* Check if next job is already prepared */
1303 (!next && data->host_cookie != host->next_data.cookie)) {
1304 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1306 omap_hsmmc_get_dma_dir(host, data));
1309 dma_len = host->next_data.dma_len;
1310 host->next_data.dma_len = 0;
1318 next->dma_len = dma_len;
1319 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1321 host->dma_len = dma_len;
1327 * Routine to configure and start DMA for the MMC card
1329 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1330 struct mmc_request *req)
1332 int dma_ch = 0, ret = 0, i;
1333 struct mmc_data *data = req->data;
1335 /* Sanity check: all the SG entries must be aligned by block size. */
1336 for (i = 0; i < data->sg_len; i++) {
1337 struct scatterlist *sgl;
1340 if (sgl->length % data->blksz)
1343 if ((data->blksz % 4) != 0)
1344 /* REVISIT: The MMC buffer increments only when MSB is written.
1345 * Return error for blksz which is non multiple of four.
1349 BUG_ON(host->dma_ch != -1);
1351 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1352 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1354 dev_err(mmc_dev(host->mmc),
1355 "%s: omap_request_dma() failed with %d\n",
1356 mmc_hostname(host->mmc), ret);
1359 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1363 host->dma_ch = dma_ch;
1364 host->dma_sg_idx = 0;
1366 omap_hsmmc_config_dma_params(host, data, data->sg);
1371 static void set_data_timeout(struct omap_hsmmc_host *host,
1372 unsigned int timeout_ns,
1373 unsigned int timeout_clks)
1375 unsigned int timeout, cycle_ns;
1376 uint32_t reg, clkd, dto = 0;
1378 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1379 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1383 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1384 timeout = timeout_ns / cycle_ns;
1385 timeout += timeout_clks;
1387 while ((timeout & 0x80000000) == 0) {
1404 reg |= dto << DTO_SHIFT;
1405 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1409 * Configure block length for MMC/SD cards and initiate the transfer.
1412 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1415 host->data = req->data;
1417 if (req->data == NULL) {
1418 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1420 * Set an arbitrary 100ms data timeout for commands with
1423 if (req->cmd->flags & MMC_RSP_BUSY)
1424 set_data_timeout(host, 100000000U, 0);
1428 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1429 | (req->data->blocks << 16));
1430 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1432 if (host->use_dma) {
1433 ret = omap_hsmmc_start_dma_transfer(host, req);
1435 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1442 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1445 struct omap_hsmmc_host *host = mmc_priv(mmc);
1446 struct mmc_data *data = mrq->data;
1448 if (host->use_dma) {
1449 if (data->host_cookie)
1450 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1452 omap_hsmmc_get_dma_dir(host, data));
1453 data->host_cookie = 0;
1457 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1460 struct omap_hsmmc_host *host = mmc_priv(mmc);
1462 if (mrq->data->host_cookie) {
1463 mrq->data->host_cookie = 0;
1468 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1470 mrq->data->host_cookie = 0;
1474 * Request function. for read/write operation
1476 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1478 struct omap_hsmmc_host *host = mmc_priv(mmc);
1481 BUG_ON(host->req_in_progress);
1482 BUG_ON(host->dma_ch != -1);
1483 if (host->protect_card) {
1484 if (host->reqs_blocked < 3) {
1486 * Ensure the controller is left in a consistent
1487 * state by resetting the command and data state
1490 omap_hsmmc_reset_controller_fsm(host, SRD);
1491 omap_hsmmc_reset_controller_fsm(host, SRC);
1492 host->reqs_blocked += 1;
1494 req->cmd->error = -EBADF;
1496 req->data->error = -EBADF;
1497 req->cmd->retries = 0;
1498 mmc_request_done(mmc, req);
1500 } else if (host->reqs_blocked)
1501 host->reqs_blocked = 0;
1502 WARN_ON(host->mrq != NULL);
1504 err = omap_hsmmc_prepare_data(host, req);
1506 req->cmd->error = err;
1508 req->data->error = err;
1510 mmc_request_done(mmc, req);
1514 omap_hsmmc_start_command(host, req->cmd, req->data);
1517 /* Routine to configure clock values. Exposed API to core */
1518 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1520 struct omap_hsmmc_host *host = mmc_priv(mmc);
1521 int do_send_init_stream = 0;
1523 pm_runtime_get_sync(host->dev);
1525 if (ios->power_mode != host->power_mode) {
1526 switch (ios->power_mode) {
1528 mmc_slot(host).set_power(host->dev, host->slot_id,
1533 mmc_slot(host).set_power(host->dev, host->slot_id,
1535 host->vdd = ios->vdd;
1538 do_send_init_stream = 1;
1541 host->power_mode = ios->power_mode;
1544 /* FIXME: set registers based only on changes to ios */
1546 omap_hsmmc_set_bus_width(host);
1548 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1549 /* Only MMC1 can interface at 3V without some flavor
1550 * of external transceiver; but they all handle 1.8V.
1552 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1553 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1555 * With pbias cell programming missing, this
1556 * can't be allowed when booting with device
1559 !host->dev->of_node) {
1561 * The mmc_select_voltage fn of the core does
1562 * not seem to set the power_mode to
1563 * MMC_POWER_UP upon recalculating the voltage.
1566 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1567 dev_dbg(mmc_dev(host->mmc),
1568 "Switch operation failed\n");
1572 omap_hsmmc_set_clock(host);
1574 if (do_send_init_stream)
1575 send_init_stream(host);
1577 omap_hsmmc_set_bus_mode(host);
1579 pm_runtime_put_autosuspend(host->dev);
1582 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1584 struct omap_hsmmc_host *host = mmc_priv(mmc);
1586 if (!mmc_slot(host).card_detect)
1588 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1591 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1593 struct omap_hsmmc_host *host = mmc_priv(mmc);
1595 if (!mmc_slot(host).get_ro)
1597 return mmc_slot(host).get_ro(host->dev, 0);
1600 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1602 struct omap_hsmmc_host *host = mmc_priv(mmc);
1604 if (mmc_slot(host).init_card)
1605 mmc_slot(host).init_card(card);
1608 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1610 u32 hctl, capa, value;
1612 /* Only MMC1 supports 3.0V */
1613 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1621 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1622 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1624 value = OMAP_HSMMC_READ(host->base, CAPA);
1625 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1627 /* Set the controller to AUTO IDLE mode */
1628 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1629 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1631 /* Set SD bus power bit */
1632 set_sd_bus_power(host);
1635 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1637 struct omap_hsmmc_host *host = mmc_priv(mmc);
1639 pm_runtime_get_sync(host->dev);
1644 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1646 struct omap_hsmmc_host *host = mmc_priv(mmc);
1648 pm_runtime_mark_last_busy(host->dev);
1649 pm_runtime_put_autosuspend(host->dev);
1654 static const struct mmc_host_ops omap_hsmmc_ops = {
1655 .enable = omap_hsmmc_enable_fclk,
1656 .disable = omap_hsmmc_disable_fclk,
1657 .post_req = omap_hsmmc_post_req,
1658 .pre_req = omap_hsmmc_pre_req,
1659 .request = omap_hsmmc_request,
1660 .set_ios = omap_hsmmc_set_ios,
1661 .get_cd = omap_hsmmc_get_cd,
1662 .get_ro = omap_hsmmc_get_ro,
1663 .init_card = omap_hsmmc_init_card,
1664 /* NYET -- enable_sdio_irq */
1667 #ifdef CONFIG_DEBUG_FS
1669 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1671 struct mmc_host *mmc = s->private;
1672 struct omap_hsmmc_host *host = mmc_priv(mmc);
1673 int context_loss = 0;
1675 if (host->pdata->get_context_loss_count)
1676 context_loss = host->pdata->get_context_loss_count(host->dev);
1678 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1679 mmc->index, host->context_loss, context_loss);
1681 if (host->suspended) {
1682 seq_printf(s, "host suspended, can't read registers\n");
1686 pm_runtime_get_sync(host->dev);
1688 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1689 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1690 seq_printf(s, "CON:\t\t0x%08x\n",
1691 OMAP_HSMMC_READ(host->base, CON));
1692 seq_printf(s, "HCTL:\t\t0x%08x\n",
1693 OMAP_HSMMC_READ(host->base, HCTL));
1694 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1695 OMAP_HSMMC_READ(host->base, SYSCTL));
1696 seq_printf(s, "IE:\t\t0x%08x\n",
1697 OMAP_HSMMC_READ(host->base, IE));
1698 seq_printf(s, "ISE:\t\t0x%08x\n",
1699 OMAP_HSMMC_READ(host->base, ISE));
1700 seq_printf(s, "CAPA:\t\t0x%08x\n",
1701 OMAP_HSMMC_READ(host->base, CAPA));
1703 pm_runtime_mark_last_busy(host->dev);
1704 pm_runtime_put_autosuspend(host->dev);
1709 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1711 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1714 static const struct file_operations mmc_regs_fops = {
1715 .open = omap_hsmmc_regs_open,
1717 .llseek = seq_lseek,
1718 .release = single_release,
1721 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1723 if (mmc->debugfs_root)
1724 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1725 mmc, &mmc_regs_fops);
1730 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1737 static u16 omap4_reg_offset = 0x100;
1739 static const struct of_device_id omap_mmc_of_match[] = {
1741 .compatible = "ti,omap2-hsmmc",
1744 .compatible = "ti,omap3-hsmmc",
1747 .compatible = "ti,omap4-hsmmc",
1748 .data = &omap4_reg_offset,
1752 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1754 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1756 struct omap_mmc_platform_data *pdata;
1757 struct device_node *np = dev->of_node;
1760 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1762 return NULL; /* out of memory */
1764 if (of_find_property(np, "ti,dual-volt", NULL))
1765 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1767 /* This driver only supports 1 slot */
1768 pdata->nr_slots = 1;
1769 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1770 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1772 if (of_find_property(np, "ti,non-removable", NULL)) {
1773 pdata->slots[0].nonremovable = true;
1774 pdata->slots[0].no_regulator_off_init = true;
1776 of_property_read_u32(np, "bus-width", &bus_width);
1778 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1779 else if (bus_width == 8)
1780 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1782 if (of_find_property(np, "ti,needs-special-reset", NULL))
1783 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1788 static inline struct omap_mmc_platform_data
1789 *of_get_hsmmc_pdata(struct device *dev)
1795 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1797 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1798 struct mmc_host *mmc;
1799 struct omap_hsmmc_host *host = NULL;
1800 struct resource *res;
1802 const struct of_device_id *match;
1804 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1806 pdata = of_get_hsmmc_pdata(&pdev->dev);
1808 u16 *offsetp = match->data;
1809 pdata->reg_offset = *offsetp;
1813 if (pdata == NULL) {
1814 dev_err(&pdev->dev, "Platform Data is missing\n");
1818 if (pdata->nr_slots == 0) {
1819 dev_err(&pdev->dev, "No Slots\n");
1823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1824 irq = platform_get_irq(pdev, 0);
1825 if (res == NULL || irq < 0)
1828 res = request_mem_region(res->start, resource_size(res), pdev->name);
1832 ret = omap_hsmmc_gpio_init(pdata);
1836 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1842 host = mmc_priv(mmc);
1844 host->pdata = pdata;
1845 host->dev = &pdev->dev;
1847 host->dev->dma_mask = &pdata->dma_mask;
1851 host->mapbase = res->start + pdata->reg_offset;
1852 host->base = ioremap(host->mapbase, SZ_4K);
1853 host->power_mode = MMC_POWER_OFF;
1854 host->next_data.cookie = 1;
1856 platform_set_drvdata(pdev, host);
1858 mmc->ops = &omap_hsmmc_ops;
1861 * If regulator_disable can only put vcc_aux to sleep then there is
1864 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1865 mmc_slot(host).no_off = 1;
1867 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1869 if (pdata->max_freq > 0)
1870 mmc->f_max = pdata->max_freq;
1872 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1874 spin_lock_init(&host->irq_lock);
1876 host->fclk = clk_get(&pdev->dev, "fck");
1877 if (IS_ERR(host->fclk)) {
1878 ret = PTR_ERR(host->fclk);
1883 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1884 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1885 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1888 pm_runtime_enable(host->dev);
1889 pm_runtime_get_sync(host->dev);
1890 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1891 pm_runtime_use_autosuspend(host->dev);
1893 omap_hsmmc_context_save(host);
1895 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1897 * MMC can still work without debounce clock.
1899 if (IS_ERR(host->dbclk)) {
1900 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1902 } else if (clk_prepare_enable(host->dbclk) != 0) {
1903 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1904 clk_put(host->dbclk);
1908 /* Since we do only SG emulation, we can have as many segs
1910 mmc->max_segs = 1024;
1912 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1913 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1914 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1915 mmc->max_seg_size = mmc->max_req_size;
1917 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1918 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1920 mmc->caps |= mmc_slot(host).caps;
1921 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1922 mmc->caps |= MMC_CAP_4_BIT_DATA;
1924 if (mmc_slot(host).nonremovable)
1925 mmc->caps |= MMC_CAP_NONREMOVABLE;
1927 mmc->pm_caps = mmc_slot(host).pm_caps;
1929 omap_hsmmc_conf_bus_power(host);
1931 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1933 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1937 host->dma_line_tx = res->start;
1939 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1941 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1945 host->dma_line_rx = res->start;
1947 /* Request IRQ for MMC operations */
1948 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1949 mmc_hostname(mmc), host);
1951 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1955 if (pdata->init != NULL) {
1956 if (pdata->init(&pdev->dev) != 0) {
1957 dev_dbg(mmc_dev(host->mmc),
1958 "Unable to configure MMC IRQs\n");
1959 goto err_irq_cd_init;
1963 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1964 ret = omap_hsmmc_reg_get(host);
1970 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1972 /* Request IRQ for card detect */
1973 if ((mmc_slot(host).card_detect_irq)) {
1974 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1977 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1978 mmc_hostname(mmc), host);
1980 dev_dbg(mmc_dev(host->mmc),
1981 "Unable to grab MMC CD IRQ\n");
1984 pdata->suspend = omap_hsmmc_suspend_cdirq;
1985 pdata->resume = omap_hsmmc_resume_cdirq;
1988 omap_hsmmc_disable_irq(host);
1990 omap_hsmmc_protect_card(host);
1994 if (mmc_slot(host).name != NULL) {
1995 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1999 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2000 ret = device_create_file(&mmc->class_dev,
2001 &dev_attr_cover_switch);
2006 omap_hsmmc_debugfs(mmc);
2007 pm_runtime_mark_last_busy(host->dev);
2008 pm_runtime_put_autosuspend(host->dev);
2013 mmc_remove_host(mmc);
2014 free_irq(mmc_slot(host).card_detect_irq, host);
2017 omap_hsmmc_reg_put(host);
2019 if (host->pdata->cleanup)
2020 host->pdata->cleanup(&pdev->dev);
2022 free_irq(host->irq, host);
2024 pm_runtime_put_sync(host->dev);
2025 pm_runtime_disable(host->dev);
2026 clk_put(host->fclk);
2028 clk_disable_unprepare(host->dbclk);
2029 clk_put(host->dbclk);
2032 iounmap(host->base);
2033 platform_set_drvdata(pdev, NULL);
2036 omap_hsmmc_gpio_free(pdata);
2038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2040 release_mem_region(res->start, resource_size(res));
2044 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2046 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2047 struct resource *res;
2049 pm_runtime_get_sync(host->dev);
2050 mmc_remove_host(host->mmc);
2052 omap_hsmmc_reg_put(host);
2053 if (host->pdata->cleanup)
2054 host->pdata->cleanup(&pdev->dev);
2055 free_irq(host->irq, host);
2056 if (mmc_slot(host).card_detect_irq)
2057 free_irq(mmc_slot(host).card_detect_irq, host);
2059 pm_runtime_put_sync(host->dev);
2060 pm_runtime_disable(host->dev);
2061 clk_put(host->fclk);
2063 clk_disable_unprepare(host->dbclk);
2064 clk_put(host->dbclk);
2067 mmc_free_host(host->mmc);
2068 iounmap(host->base);
2069 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2073 release_mem_region(res->start, resource_size(res));
2074 platform_set_drvdata(pdev, NULL);
2080 static int omap_hsmmc_suspend(struct device *dev)
2083 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2088 if (host && host->suspended)
2091 pm_runtime_get_sync(host->dev);
2092 host->suspended = 1;
2093 if (host->pdata->suspend) {
2094 ret = host->pdata->suspend(dev, host->slot_id);
2096 dev_dbg(dev, "Unable to handle MMC board"
2097 " level suspend\n");
2098 host->suspended = 0;
2102 ret = mmc_suspend_host(host->mmc);
2105 host->suspended = 0;
2106 if (host->pdata->resume) {
2107 ret = host->pdata->resume(dev, host->slot_id);
2109 dev_dbg(dev, "Unmask interrupt failed\n");
2114 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2115 omap_hsmmc_disable_irq(host);
2116 OMAP_HSMMC_WRITE(host->base, HCTL,
2117 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2121 clk_disable_unprepare(host->dbclk);
2123 pm_runtime_put_sync(host->dev);
2127 /* Routine to resume the MMC device */
2128 static int omap_hsmmc_resume(struct device *dev)
2131 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2136 if (host && !host->suspended)
2139 pm_runtime_get_sync(host->dev);
2142 clk_prepare_enable(host->dbclk);
2144 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2145 omap_hsmmc_conf_bus_power(host);
2147 if (host->pdata->resume) {
2148 ret = host->pdata->resume(dev, host->slot_id);
2150 dev_dbg(dev, "Unmask interrupt failed\n");
2153 omap_hsmmc_protect_card(host);
2155 /* Notify the core to resume the host */
2156 ret = mmc_resume_host(host->mmc);
2158 host->suspended = 0;
2160 pm_runtime_mark_last_busy(host->dev);
2161 pm_runtime_put_autosuspend(host->dev);
2168 #define omap_hsmmc_suspend NULL
2169 #define omap_hsmmc_resume NULL
2172 static int omap_hsmmc_runtime_suspend(struct device *dev)
2174 struct omap_hsmmc_host *host;
2176 host = platform_get_drvdata(to_platform_device(dev));
2177 omap_hsmmc_context_save(host);
2178 dev_dbg(dev, "disabled\n");
2183 static int omap_hsmmc_runtime_resume(struct device *dev)
2185 struct omap_hsmmc_host *host;
2187 host = platform_get_drvdata(to_platform_device(dev));
2188 omap_hsmmc_context_restore(host);
2189 dev_dbg(dev, "enabled\n");
2194 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2195 .suspend = omap_hsmmc_suspend,
2196 .resume = omap_hsmmc_resume,
2197 .runtime_suspend = omap_hsmmc_runtime_suspend,
2198 .runtime_resume = omap_hsmmc_runtime_resume,
2201 static struct platform_driver omap_hsmmc_driver = {
2202 .probe = omap_hsmmc_probe,
2203 .remove = __devexit_p(omap_hsmmc_remove),
2205 .name = DRIVER_NAME,
2206 .owner = THIS_MODULE,
2207 .pm = &omap_hsmmc_dev_pm_ops,
2208 .of_match_table = of_match_ptr(omap_mmc_of_match),
2212 module_platform_driver(omap_hsmmc_driver);
2213 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2214 MODULE_LICENSE("GPL");
2215 MODULE_ALIAS("platform:" DRIVER_NAME);
2216 MODULE_AUTHOR("Texas Instruments Inc");