2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/mmc/host.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/gpio.h>
32 #include <linux/gfp.h>
34 #include <asm/sizes.h>
36 #include <mach/hardware.h>
42 #define DRIVER_NAME "pxa2xx-mci"
45 #define CLKRT_OFF (~0)
47 #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
56 unsigned long clkrate;
62 unsigned int power_mode;
63 struct pxamci_platform_data *pdata;
65 struct mmc_request *mrq;
66 struct mmc_command *cmd;
67 struct mmc_data *data;
70 struct pxa_dma_desc *sg_cpu;
74 unsigned int dma_drcmrrx;
75 unsigned int dma_drcmrtx;
77 struct regulator *vcc;
80 static inline void pxamci_init_ocr(struct pxamci_host *host)
82 #ifdef CONFIG_REGULATOR
83 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
85 if (IS_ERR(host->vcc))
88 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
89 if (host->pdata && host->pdata->ocr_mask)
90 dev_warn(mmc_dev(host->mmc),
91 "ocr_mask/setpower will not be used\n");
94 if (host->vcc == NULL) {
95 /* fall-back to platform data */
96 host->mmc->ocr_avail = host->pdata ?
97 host->pdata->ocr_mask :
98 MMC_VDD_32_33 | MMC_VDD_33_34;
102 static inline int pxamci_set_power(struct pxamci_host *host,
103 unsigned char power_mode,
111 if (power_mode == MMC_POWER_UP) {
112 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
115 } else if (power_mode == MMC_POWER_OFF) {
116 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
121 if (!host->vcc && host->pdata &&
122 gpio_is_valid(host->pdata->gpio_power)) {
123 on = ((1 << vdd) & host->pdata->ocr_mask);
124 gpio_set_value(host->pdata->gpio_power,
125 !!on ^ host->pdata->gpio_power_invert);
127 if (!host->vcc && host->pdata && host->pdata->setpower)
128 host->pdata->setpower(mmc_dev(host->mmc), vdd);
133 static void pxamci_stop_clock(struct pxamci_host *host)
135 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
136 unsigned long timeout = 10000;
139 writel(STOP_CLOCK, host->base + MMC_STRPCL);
142 v = readl(host->base + MMC_STAT);
143 if (!(v & STAT_CLK_EN))
149 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
153 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
157 spin_lock_irqsave(&host->lock, flags);
158 host->imask &= ~mask;
159 writel(host->imask, host->base + MMC_I_MASK);
160 spin_unlock_irqrestore(&host->lock, flags);
163 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
167 spin_lock_irqsave(&host->lock, flags);
169 writel(host->imask, host->base + MMC_I_MASK);
170 spin_unlock_irqrestore(&host->lock, flags);
173 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
175 unsigned int nob = data->blocks;
176 unsigned long long clks;
177 unsigned int timeout;
184 if (data->flags & MMC_DATA_STREAM)
187 writel(nob, host->base + MMC_NOB);
188 writel(data->blksz, host->base + MMC_BLKLEN);
190 clks = (unsigned long long)data->timeout_ns * host->clkrate;
191 do_div(clks, 1000000000UL);
192 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
193 writel((timeout + 255) / 256, host->base + MMC_RDTO);
195 if (data->flags & MMC_DATA_READ) {
196 host->dma_dir = DMA_FROM_DEVICE;
197 dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
198 DRCMR(host->dma_drcmrtx) = 0;
199 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD;
201 host->dma_dir = DMA_TO_DEVICE;
202 dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
203 DRCMR(host->dma_drcmrrx) = 0;
204 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD;
207 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
209 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
212 for (i = 0; i < host->dma_len; i++) {
213 unsigned int length = sg_dma_len(&data->sg[i]);
214 host->sg_cpu[i].dcmd = dcmd | length;
215 if (length & 31 && !(data->flags & MMC_DATA_READ))
216 host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN;
217 /* Not aligned to 8-byte boundary? */
218 if (sg_dma_address(&data->sg[i]) & 0x7)
220 if (data->flags & MMC_DATA_READ) {
221 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
222 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
224 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
225 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
227 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
228 sizeof(struct pxa_dma_desc);
230 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
234 * The PXA27x DMA controller encounters overhead when working with
235 * unaligned (to 8-byte boundaries) data, so switch on byte alignment
236 * mode only if we have unaligned data.
239 DALGN |= (1 << host->dma);
241 DALGN &= ~(1 << host->dma);
242 DDADR(host->dma) = host->sg_dma;
245 * workaround for erratum #91:
246 * only start DMA now if we are doing a read,
247 * otherwise we wait until CMD/RESP has finished
248 * before starting DMA.
250 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
251 DCSR(host->dma) = DCSR_RUN;
254 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
256 WARN_ON(host->cmd != NULL);
259 if (cmd->flags & MMC_RSP_BUSY)
262 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
263 switch (RSP_TYPE(mmc_resp_type(cmd))) {
264 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
265 cmdat |= CMDAT_RESP_SHORT;
267 case RSP_TYPE(MMC_RSP_R3):
268 cmdat |= CMDAT_RESP_R3;
270 case RSP_TYPE(MMC_RSP_R2):
271 cmdat |= CMDAT_RESP_R2;
277 writel(cmd->opcode, host->base + MMC_CMD);
278 writel(cmd->arg >> 16, host->base + MMC_ARGH);
279 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
280 writel(cmdat, host->base + MMC_CMDAT);
281 writel(host->clkrt, host->base + MMC_CLKRT);
283 writel(START_CLOCK, host->base + MMC_STRPCL);
285 pxamci_enable_irq(host, END_CMD_RES);
288 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
293 mmc_request_done(host->mmc, mrq);
296 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
298 struct mmc_command *cmd = host->cmd;
308 * Did I mention this is Sick. We always need to
309 * discard the upper 8 bits of the first 16-bit word.
311 v = readl(host->base + MMC_RES) & 0xffff;
312 for (i = 0; i < 4; i++) {
313 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
314 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
315 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
319 if (stat & STAT_TIME_OUT_RESPONSE) {
320 cmd->error = -ETIMEDOUT;
321 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
323 * workaround for erratum #42:
324 * Intel PXA27x Family Processor Specification Update Rev 001
325 * A bogus CRC error can appear if the msb of a 136 bit
328 if (cpu_is_pxa27x() &&
329 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
330 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
332 cmd->error = -EILSEQ;
335 pxamci_disable_irq(host, END_CMD_RES);
336 if (host->data && !cmd->error) {
337 pxamci_enable_irq(host, DATA_TRAN_DONE);
339 * workaround for erratum #91, if doing write
342 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
343 DCSR(host->dma) = DCSR_RUN;
345 pxamci_finish_request(host, host->mrq);
351 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
353 struct mmc_data *data = host->data;
359 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
362 if (stat & STAT_READ_TIME_OUT)
363 data->error = -ETIMEDOUT;
364 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
365 data->error = -EILSEQ;
368 * There appears to be a hardware design bug here. There seems to
369 * be no way to find out how much data was transferred to the card.
370 * This means that if there was an error on any block, we mark all
371 * data blocks as being in error.
374 data->bytes_xfered = data->blocks * data->blksz;
376 data->bytes_xfered = 0;
378 pxamci_disable_irq(host, DATA_TRAN_DONE);
381 if (host->mrq->stop) {
382 pxamci_stop_clock(host);
383 pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
385 pxamci_finish_request(host, host->mrq);
391 static irqreturn_t pxamci_irq(int irq, void *devid)
393 struct pxamci_host *host = devid;
397 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
400 unsigned stat = readl(host->base + MMC_STAT);
402 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
404 if (ireg & END_CMD_RES)
405 handled |= pxamci_cmd_done(host, stat);
406 if (ireg & DATA_TRAN_DONE)
407 handled |= pxamci_data_done(host, stat);
408 if (ireg & SDIO_INT) {
409 mmc_signal_sdio_irq(host->mmc);
414 return IRQ_RETVAL(handled);
417 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
419 struct pxamci_host *host = mmc_priv(mmc);
422 WARN_ON(host->mrq != NULL);
426 pxamci_stop_clock(host);
429 host->cmdat &= ~CMDAT_INIT;
432 pxamci_setup_data(host, mrq->data);
434 cmdat &= ~CMDAT_BUSY;
435 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
436 if (mrq->data->flags & MMC_DATA_WRITE)
437 cmdat |= CMDAT_WRITE;
439 if (mrq->data->flags & MMC_DATA_STREAM)
440 cmdat |= CMDAT_STREAM;
443 pxamci_start_cmd(host, mrq->cmd, cmdat);
446 static int pxamci_get_ro(struct mmc_host *mmc)
448 struct pxamci_host *host = mmc_priv(mmc);
450 if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) {
451 if (host->pdata->gpio_card_ro_invert)
452 return !gpio_get_value(host->pdata->gpio_card_ro);
454 return gpio_get_value(host->pdata->gpio_card_ro);
456 if (host->pdata && host->pdata->get_ro)
457 return !!host->pdata->get_ro(mmc_dev(mmc));
459 * Board doesn't support read only detection; let the mmc core
465 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
467 struct pxamci_host *host = mmc_priv(mmc);
470 unsigned long rate = host->clkrate;
471 unsigned int clk = rate / ios->clock;
473 if (host->clkrt == CLKRT_OFF)
474 clk_enable(host->clk);
476 if (ios->clock == 26000000) {
477 /* to support 26MHz */
480 /* to handle (19.5MHz, 26MHz) */
485 * clk might result in a lower divisor than we
486 * desire. check for that condition and adjust
489 if (rate / clk > ios->clock)
491 host->clkrt = fls(clk) - 1;
495 * we write clkrt on the next command
498 pxamci_stop_clock(host);
499 if (host->clkrt != CLKRT_OFF) {
500 host->clkrt = CLKRT_OFF;
501 clk_disable(host->clk);
505 if (host->power_mode != ios->power_mode) {
508 host->power_mode = ios->power_mode;
510 ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
512 dev_err(mmc_dev(mmc), "unable to set power\n");
514 * The .set_ios() function in the mmc_host_ops
515 * struct return void, and failing to set the
516 * power should be rare so we print an error and
522 if (ios->power_mode == MMC_POWER_ON)
523 host->cmdat |= CMDAT_INIT;
526 if (ios->bus_width == MMC_BUS_WIDTH_4)
527 host->cmdat |= CMDAT_SD_4DAT;
529 host->cmdat &= ~CMDAT_SD_4DAT;
531 dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
532 host->clkrt, host->cmdat);
535 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
537 struct pxamci_host *pxa_host = mmc_priv(host);
540 pxamci_enable_irq(pxa_host, SDIO_INT);
542 pxamci_disable_irq(pxa_host, SDIO_INT);
545 static const struct mmc_host_ops pxamci_ops = {
546 .request = pxamci_request,
547 .get_ro = pxamci_get_ro,
548 .set_ios = pxamci_set_ios,
549 .enable_sdio_irq = pxamci_enable_sdio_irq,
552 static void pxamci_dma_irq(int dma, void *devid)
554 struct pxamci_host *host = devid;
555 int dcsr = DCSR(dma);
556 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN;
558 if (dcsr & DCSR_ENDINTR) {
559 writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
561 pr_err("%s: DMA error on channel %d (DCSR=%#x)\n",
562 mmc_hostname(host->mmc), dma, dcsr);
563 host->data->error = -EIO;
564 pxamci_data_done(host, 0);
568 static irqreturn_t pxamci_detect_irq(int irq, void *devid)
570 struct pxamci_host *host = mmc_priv(devid);
572 mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms));
576 static int pxamci_probe(struct platform_device *pdev)
578 struct mmc_host *mmc;
579 struct pxamci_host *host = NULL;
580 struct resource *r, *dmarx, *dmatx;
581 int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
583 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584 irq = platform_get_irq(pdev, 0);
588 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
592 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
598 mmc->ops = &pxamci_ops;
601 * We can do SG-DMA, but we don't because we never know how much
602 * data we successfully wrote to the card.
604 mmc->max_segs = NR_SG;
607 * Our hardware DMA can handle a maximum of one page per SG entry.
609 mmc->max_seg_size = PAGE_SIZE;
612 * Block length register is only 10 bits before PXA27x.
614 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
617 * Block count register is 16 bits.
619 mmc->max_blk_count = 65535;
621 host = mmc_priv(mmc);
624 host->pdata = pdev->dev.platform_data;
625 host->clkrt = CLKRT_OFF;
627 host->clk = clk_get(&pdev->dev, NULL);
628 if (IS_ERR(host->clk)) {
629 ret = PTR_ERR(host->clk);
634 host->clkrate = clk_get_rate(host->clk);
637 * Calculate minimum clock rate, rounding up.
639 mmc->f_min = (host->clkrate + 63) / 64;
640 mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
642 pxamci_init_ocr(host);
646 if (!cpu_is_pxa25x()) {
647 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
648 host->cmdat |= CMDAT_SDIO_INT_EN;
650 mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
651 MMC_CAP_SD_HIGHSPEED;
654 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
660 spin_lock_init(&host->lock);
663 host->imask = MMC_I_MASK_ALL;
665 host->base = ioremap(r->start, SZ_4K);
672 * Ensure that the host controller is shut down, and setup
675 pxamci_stop_clock(host);
676 writel(0, host->base + MMC_SPI);
677 writel(64, host->base + MMC_RESTO);
678 writel(host->imask, host->base + MMC_I_MASK);
680 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
681 pxamci_dma_irq, host);
687 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
691 platform_set_drvdata(pdev, mmc);
693 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
698 host->dma_drcmrrx = dmarx->start;
700 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
705 host->dma_drcmrtx = dmatx->start;
708 gpio_cd = host->pdata->gpio_card_detect;
709 gpio_ro = host->pdata->gpio_card_ro;
710 gpio_power = host->pdata->gpio_power;
712 if (gpio_is_valid(gpio_power)) {
713 ret = gpio_request(gpio_power, "mmc card power");
715 dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power);
718 gpio_direction_output(gpio_power,
719 host->pdata->gpio_power_invert);
721 if (gpio_is_valid(gpio_ro)) {
722 ret = gpio_request(gpio_ro, "mmc card read only");
724 dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro);
727 gpio_direction_input(gpio_ro);
729 if (gpio_is_valid(gpio_cd)) {
730 ret = gpio_request(gpio_cd, "mmc card detect");
732 dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd);
735 gpio_direction_input(gpio_cd);
737 ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq,
738 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
739 "mmc card detect", mmc);
741 dev_err(&pdev->dev, "failed to request card detect IRQ\n");
742 goto err_request_irq;
746 if (host->pdata && host->pdata->init)
747 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
749 if (gpio_is_valid(gpio_power) && host->pdata->setpower)
750 dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n");
751 if (gpio_is_valid(gpio_ro) && host->pdata->get_ro)
752 dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n");
763 gpio_free(gpio_power);
767 pxa_free_dma(host->dma);
771 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
781 static int pxamci_remove(struct platform_device *pdev)
783 struct mmc_host *mmc = platform_get_drvdata(pdev);
784 int gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
786 platform_set_drvdata(pdev, NULL);
789 struct pxamci_host *host = mmc_priv(mmc);
791 mmc_remove_host(mmc);
794 gpio_cd = host->pdata->gpio_card_detect;
795 gpio_ro = host->pdata->gpio_card_ro;
796 gpio_power = host->pdata->gpio_power;
798 if (gpio_is_valid(gpio_cd)) {
799 free_irq(gpio_to_irq(gpio_cd), mmc);
802 if (gpio_is_valid(gpio_ro))
804 if (gpio_is_valid(gpio_power))
805 gpio_free(gpio_power);
807 regulator_put(host->vcc);
809 if (host->pdata && host->pdata->exit)
810 host->pdata->exit(&pdev->dev, mmc);
812 pxamci_stop_clock(host);
813 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
814 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
815 host->base + MMC_I_MASK);
817 DRCMR(host->dma_drcmrrx) = 0;
818 DRCMR(host->dma_drcmrtx) = 0;
820 free_irq(host->irq, host);
821 pxa_free_dma(host->dma);
823 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
827 release_resource(host->res);
835 static int pxamci_suspend(struct device *dev)
837 struct mmc_host *mmc = dev_get_drvdata(dev);
841 ret = mmc_suspend_host(mmc);
846 static int pxamci_resume(struct device *dev)
848 struct mmc_host *mmc = dev_get_drvdata(dev);
852 ret = mmc_resume_host(mmc);
857 static const struct dev_pm_ops pxamci_pm_ops = {
858 .suspend = pxamci_suspend,
859 .resume = pxamci_resume,
863 static struct platform_driver pxamci_driver = {
864 .probe = pxamci_probe,
865 .remove = pxamci_remove,
868 .owner = THIS_MODULE,
870 .pm = &pxamci_pm_ops,
875 module_platform_driver(pxamci_driver);
877 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
878 MODULE_LICENSE("GPL");
879 MODULE_ALIAS("platform:pxa2xx-mci");