2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/clk.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/gpio.h>
23 #include <linux/irq.h>
28 #include <mach/regs-sdi.h>
29 #include <mach/regs-gpio.h>
35 #define DRIVER_NAME "s3c-mci"
49 static const int dbgmap_err = dbg_fail;
50 static const int dbgmap_info = dbg_info | dbg_conf;
51 static const int dbgmap_debug = dbg_err | dbg_debug;
53 #define dbg(host, channels, args...) \
55 if (dbgmap_err & channels) \
56 dev_err(&host->pdev->dev, args); \
57 else if (dbgmap_info & channels) \
58 dev_info(&host->pdev->dev, args); \
59 else if (dbgmap_debug & channels) \
60 dev_dbg(&host->pdev->dev, args); \
63 static struct s3c2410_dma_client s3cmci_dma_client = {
67 static void finalize_request(struct s3cmci_host *host);
68 static void s3cmci_send_request(struct mmc_host *mmc);
69 static void s3cmci_reset(struct s3cmci_host *host);
71 #ifdef CONFIG_MMC_DEBUG
73 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
75 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
76 u32 datcon, datcnt, datsta, fsta, imask;
78 con = readl(host->base + S3C2410_SDICON);
79 pre = readl(host->base + S3C2410_SDIPRE);
80 cmdarg = readl(host->base + S3C2410_SDICMDARG);
81 cmdcon = readl(host->base + S3C2410_SDICMDCON);
82 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
83 r0 = readl(host->base + S3C2410_SDIRSP0);
84 r1 = readl(host->base + S3C2410_SDIRSP1);
85 r2 = readl(host->base + S3C2410_SDIRSP2);
86 r3 = readl(host->base + S3C2410_SDIRSP3);
87 timer = readl(host->base + S3C2410_SDITIMER);
88 bsize = readl(host->base + S3C2410_SDIBSIZE);
89 datcon = readl(host->base + S3C2410_SDIDCON);
90 datcnt = readl(host->base + S3C2410_SDIDCNT);
91 datsta = readl(host->base + S3C2410_SDIDSTA);
92 fsta = readl(host->base + S3C2410_SDIFSTA);
93 imask = readl(host->base + host->sdiimsk);
95 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
96 prefix, con, pre, timer);
98 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
99 prefix, cmdcon, cmdarg, cmdsta);
101 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
102 " DSTA:[%08x] DCNT:[%08x]\n",
103 prefix, datcon, fsta, datsta, datcnt);
105 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
106 " R2:[%08x] R3:[%08x]\n",
107 prefix, r0, r1, r2, r3);
110 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
113 snprintf(host->dbgmsg_cmd, 300,
114 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
115 host->ccnt, (stop ? " (STOP)" : ""),
116 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
119 snprintf(host->dbgmsg_dat, 300,
120 "#%u bsize:%u blocks:%u bytes:%u",
121 host->dcnt, cmd->data->blksz,
123 cmd->data->blocks * cmd->data->blksz);
125 host->dbgmsg_dat[0] = '\0';
129 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
132 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
137 if (cmd->error == 0) {
138 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
139 host->dbgmsg_cmd, cmd->resp[0]);
141 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
142 cmd->error, host->dbgmsg_cmd, host->status);
148 if (cmd->data->error == 0) {
149 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
151 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
152 cmd->data->error, host->dbgmsg_dat,
153 readl(host->base + S3C2410_SDIDCNT));
157 static void dbg_dumpcmd(struct s3cmci_host *host,
158 struct mmc_command *cmd, int fail) { }
160 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
163 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
165 #endif /* CONFIG_MMC_DEBUG */
168 * s3cmci_host_usedma - return whether the host is using dma or pio
169 * @host: The host state
171 * Return true if the host is using DMA to transfer data, else false
172 * to use PIO mode. Will return static data depending on the driver
175 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
177 #ifdef CONFIG_MMC_S3C_PIO
179 #elif defined(CONFIG_MMC_S3C_DMA)
187 * s3cmci_host_canpio - return true if host has pio code available
189 * Return true if the driver has been compiled with the PIO support code
192 static inline bool s3cmci_host_canpio(void)
194 #ifdef CONFIG_MMC_S3C_PIO
201 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
205 newmask = readl(host->base + host->sdiimsk);
208 writel(newmask, host->base + host->sdiimsk);
213 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
217 newmask = readl(host->base + host->sdiimsk);
220 writel(newmask, host->base + host->sdiimsk);
225 static inline void clear_imask(struct s3cmci_host *host)
227 u32 mask = readl(host->base + host->sdiimsk);
229 /* preserve the SDIO IRQ mask state */
230 mask &= S3C2410_SDIIMSK_SDIOIRQ;
231 writel(mask, host->base + host->sdiimsk);
235 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
236 * @host: The host to check.
238 * Test to see if the SDIO interrupt is being signalled in case the
239 * controller has failed to re-detect a card interrupt. Read GPE8 and
240 * see if it is low and if so, signal a SDIO interrupt.
242 * This is currently called if a request is finished (we assume that the
243 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
244 * already being indicated.
246 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
248 if (host->sdio_irqen) {
249 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
250 printk(KERN_DEBUG "%s: signalling irq\n", __func__);
251 mmc_signal_sdio_irq(host->mmc);
256 static inline int get_data_buffer(struct s3cmci_host *host,
257 u32 *bytes, u32 **pointer)
259 struct scatterlist *sg;
261 if (host->pio_active == XFER_NONE)
264 if ((!host->mrq) || (!host->mrq->data))
267 if (host->pio_sgptr >= host->mrq->data->sg_len) {
268 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
269 host->pio_sgptr, host->mrq->data->sg_len);
272 sg = &host->mrq->data->sg[host->pio_sgptr];
275 *pointer = sg_virt(sg);
279 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
280 host->pio_sgptr, host->mrq->data->sg_len);
285 static inline u32 fifo_count(struct s3cmci_host *host)
287 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
289 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
293 static inline u32 fifo_free(struct s3cmci_host *host)
295 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
297 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
298 return 63 - fifostat;
302 * s3cmci_enable_irq - enable IRQ, after having disabled it.
303 * @host: The device state.
304 * @more: True if more IRQs are expected from transfer.
306 * Enable the main IRQ if needed after it has been disabled.
308 * The IRQ can be one of the following states:
309 * - disabled during IDLE
310 * - disabled whilst processing data
311 * - enabled during transfer
312 * - enabled whilst awaiting SDIO interrupt detection
314 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
319 local_irq_save(flags);
321 host->irq_enabled = more;
322 host->irq_disabled = false;
324 enable = more | host->sdio_irqen;
326 if (host->irq_state != enable) {
327 host->irq_state = enable;
330 enable_irq(host->irq);
332 disable_irq(host->irq);
335 local_irq_restore(flags);
341 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
345 local_irq_save(flags);
347 //printk(KERN_DEBUG "%s: transfer %d\n", __func__, transfer);
349 host->irq_disabled = transfer;
351 if (transfer && host->irq_state) {
352 host->irq_state = false;
353 disable_irq(host->irq);
356 local_irq_restore(flags);
359 static void do_pio_read(struct s3cmci_host *host)
365 void __iomem *from_ptr;
367 /* write real prescaler to host, it might be set slow to fix */
368 writel(host->prescaler, host->base + S3C2410_SDIPRE);
370 from_ptr = host->base + host->sdidata;
372 while ((fifo = fifo_count(host))) {
373 if (!host->pio_bytes) {
374 res = get_data_buffer(host, &host->pio_bytes,
377 host->pio_active = XFER_NONE;
378 host->complete_what = COMPLETION_FINALIZE;
380 dbg(host, dbg_pio, "pio_read(): "
381 "complete (no more data).\n");
386 "pio_read(): new target: [%i]@[%p]\n",
387 host->pio_bytes, host->pio_ptr);
391 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
392 fifo, host->pio_bytes,
393 readl(host->base + S3C2410_SDIDCNT));
395 /* If we have reached the end of the block, we can
396 * read a word and get 1 to 3 bytes. If we in the
397 * middle of the block, we have to read full words,
398 * otherwise we will write garbage, so round down to
399 * an even multiple of 4. */
400 if (fifo >= host->pio_bytes)
401 fifo = host->pio_bytes;
405 host->pio_bytes -= fifo;
406 host->pio_count += fifo;
408 fifo_words = fifo >> 2;
411 *ptr++ = readl(from_ptr);
416 u32 data = readl(from_ptr);
417 u8 *p = (u8 *)host->pio_ptr;
426 if (!host->pio_bytes) {
427 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
430 "pio_read(): complete (no more buffers).\n");
431 host->pio_active = XFER_NONE;
432 host->complete_what = COMPLETION_FINALIZE;
439 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
442 static void do_pio_write(struct s3cmci_host *host)
444 void __iomem *to_ptr;
449 to_ptr = host->base + host->sdidata;
451 while ((fifo = fifo_free(host)) > 3) {
452 if (!host->pio_bytes) {
453 res = get_data_buffer(host, &host->pio_bytes,
457 "pio_write(): complete (no more data).\n");
458 host->pio_active = XFER_NONE;
464 "pio_write(): new source: [%i]@[%p]\n",
465 host->pio_bytes, host->pio_ptr);
469 /* If we have reached the end of the block, we have to
470 * write exactly the remaining number of bytes. If we
471 * in the middle of the block, we have to write full
472 * words, so round down to an even multiple of 4. */
473 if (fifo >= host->pio_bytes)
474 fifo = host->pio_bytes;
478 host->pio_bytes -= fifo;
479 host->pio_count += fifo;
481 fifo = (fifo + 3) >> 2;
484 writel(*ptr++, to_ptr);
488 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
491 static void pio_tasklet(unsigned long data)
493 struct s3cmci_host *host = (struct s3cmci_host *) data;
495 s3cmci_disable_irq(host, true);
497 if (host->pio_active == XFER_WRITE)
500 if (host->pio_active == XFER_READ)
503 if (host->complete_what == COMPLETION_FINALIZE) {
505 if (host->pio_active != XFER_NONE) {
506 dbg(host, dbg_err, "unfinished %s "
507 "- pio_count:[%u] pio_bytes:[%u]\n",
508 (host->pio_active == XFER_READ) ? "read" : "write",
509 host->pio_count, host->pio_bytes);
512 host->mrq->data->error = -EINVAL;
515 s3cmci_enable_irq(host, false);
516 finalize_request(host);
518 s3cmci_enable_irq(host, true);
522 * ISR for SDI Interface IRQ
523 * Communication between driver and ISR works as follows:
524 * host->mrq points to current request
525 * host->complete_what Indicates when the request is considered done
526 * COMPLETION_CMDSENT when the command was sent
527 * COMPLETION_RSPFIN when a response was received
528 * COMPLETION_XFERFINISH when the data transfer is finished
529 * COMPLETION_XFERFINISH_RSPFIN both of the above.
530 * host->complete_request is the completion-object the driver waits for
532 * 1) Driver sets up host->mrq and host->complete_what
533 * 2) Driver prepares the transfer
534 * 3) Driver enables interrupts
535 * 4) Driver starts transfer
536 * 5) Driver waits for host->complete_rquest
537 * 6) ISR checks for request status (errors and success)
538 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
539 * 7) ISR completes host->complete_request
540 * 8) ISR disables interrupts
541 * 9) Driver wakes up and takes care of the request
543 * Note: "->error"-fields are expected to be set to 0 before the request
544 * was issued by mmc.c - therefore they are only set, when an error
548 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
550 struct s3cmci_host *host = dev_id;
551 struct mmc_command *cmd;
552 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
553 u32 mci_cclear = 0, mci_dclear;
554 unsigned long iflags;
556 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
557 mci_imsk = readl(host->base + host->sdiimsk);
559 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
560 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
561 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
562 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
564 mmc_signal_sdio_irq(host->mmc);
569 spin_lock_irqsave(&host->complete_lock, iflags);
571 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
572 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
573 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
576 if ((host->complete_what == COMPLETION_NONE) ||
577 (host->complete_what == COMPLETION_FINALIZE)) {
578 host->status = "nothing to complete";
584 host->status = "no active mrq";
589 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
592 host->status = "no active cmd";
597 if (!s3cmci_host_usedma(host)) {
598 if ((host->pio_active == XFER_WRITE) &&
599 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
601 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
602 tasklet_schedule(&host->pio_tasklet);
603 host->status = "pio tx";
606 if ((host->pio_active == XFER_READ) &&
607 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
610 S3C2410_SDIIMSK_RXFIFOHALF |
611 S3C2410_SDIIMSK_RXFIFOLAST);
613 tasklet_schedule(&host->pio_tasklet);
614 host->status = "pio rx";
618 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
619 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
620 cmd->error = -ETIMEDOUT;
621 host->status = "error: command timeout";
625 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
626 if (host->complete_what == COMPLETION_CMDSENT) {
627 host->status = "ok: command sent";
631 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
634 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
635 if (cmd->flags & MMC_RSP_CRC) {
636 if (host->mrq->cmd->flags & MMC_RSP_136) {
638 "fixup: ignore CRC fail with long rsp\n");
640 /* note, we used to fail the transfer
641 * here, but it seems that this is just
642 * the hardware getting it wrong.
644 * cmd->error = -EILSEQ;
645 * host->status = "error: bad command crc";
646 * goto fail_transfer;
651 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
654 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
655 if (host->complete_what == COMPLETION_RSPFIN) {
656 host->status = "ok: command response received";
660 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
661 host->complete_what = COMPLETION_XFERFINISH;
663 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
666 /* errors handled after this point are only relevant
667 when a data transfer is in progress */
670 goto clear_status_bits;
672 /* Check for FIFO failure */
674 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
675 dbg(host, dbg_err, "FIFO failure\n");
676 host->mrq->data->error = -EILSEQ;
677 host->status = "error: 2440 fifo failure";
681 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
682 dbg(host, dbg_err, "FIFO failure\n");
683 cmd->data->error = -EILSEQ;
684 host->status = "error: fifo failure";
689 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
690 dbg(host, dbg_err, "bad data crc (outgoing)\n");
691 cmd->data->error = -EILSEQ;
692 host->status = "error: bad data crc (outgoing)";
696 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
697 dbg(host, dbg_err, "bad data crc (incoming)\n");
698 cmd->data->error = -EILSEQ;
699 host->status = "error: bad data crc (incoming)";
703 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
704 dbg(host, dbg_err, "data timeout\n");
705 cmd->data->error = -ETIMEDOUT;
706 host->status = "error: data timeout";
710 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
711 if (host->complete_what == COMPLETION_XFERFINISH) {
712 host->status = "ok: data transfer completed";
716 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
717 host->complete_what = COMPLETION_RSPFIN;
719 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
723 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
724 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
729 host->pio_active = XFER_NONE;
732 host->complete_what = COMPLETION_FINALIZE;
735 tasklet_schedule(&host->pio_tasklet);
741 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
742 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
744 spin_unlock_irqrestore(&host->complete_lock, iflags);
750 * ISR for the CardDetect Pin
753 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
755 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
757 dbg(host, dbg_irq, "card detect\n");
759 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
764 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
765 void *buf_id, int size,
766 enum s3c2410_dma_buffresult result)
768 struct s3cmci_host *host = buf_id;
769 unsigned long iflags;
770 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
772 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
773 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
774 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
775 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
778 BUG_ON(!host->mrq->data);
779 BUG_ON(!host->dmatogo);
781 spin_lock_irqsave(&host->complete_lock, iflags);
783 if (result != S3C2410_RES_OK) {
784 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
785 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
786 mci_csta, mci_dsta, mci_fsta,
787 mci_dcnt, result, host->dmatogo);
794 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
795 "DCNT:[%08x] toGo:%u\n",
796 size, mci_dsta, mci_dcnt, host->dmatogo);
801 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
802 size, mci_dsta, mci_dcnt);
804 host->dma_complete = 1;
805 host->complete_what = COMPLETION_FINALIZE;
808 tasklet_schedule(&host->pio_tasklet);
809 spin_unlock_irqrestore(&host->complete_lock, iflags);
813 host->mrq->data->error = -EINVAL;
814 host->complete_what = COMPLETION_FINALIZE;
820 static void finalize_request(struct s3cmci_host *host)
822 struct mmc_request *mrq = host->mrq;
823 struct mmc_command *cmd;
824 int debug_as_failure = 0;
826 if (host->complete_what != COMPLETION_FINALIZE)
831 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
833 if (cmd->data && (cmd->error == 0) &&
834 (cmd->data->error == 0)) {
835 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
836 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
842 /* Read response from controller. */
843 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
844 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
845 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
846 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
848 writel(host->prescaler, host->base + S3C2410_SDIPRE);
851 debug_as_failure = 1;
853 if (cmd->data && cmd->data->error)
854 debug_as_failure = 1;
856 dbg_dumpcmd(host, cmd, debug_as_failure);
858 /* Cleanup controller */
859 writel(0, host->base + S3C2410_SDICMDARG);
860 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
861 writel(0, host->base + S3C2410_SDICMDCON);
864 if (cmd->data && cmd->error)
865 cmd->data->error = cmd->error;
867 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
868 host->cmd_is_stop = 1;
869 s3cmci_send_request(host->mmc);
873 /* If we have no data transfer we are finished here */
877 /* Calulate the amout of bytes transfer if there was no error */
878 if (mrq->data->error == 0) {
879 mrq->data->bytes_xfered =
880 (mrq->data->blocks * mrq->data->blksz);
882 mrq->data->bytes_xfered = 0;
885 /* If we had an error while transfering data we flush the
886 * DMA channel and the fifo to clear out any garbage. */
887 if (mrq->data->error != 0) {
888 if (s3cmci_host_usedma(host))
889 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
892 /* Clear failure register and reset fifo. */
893 writel(S3C2440_SDIFSTA_FIFORESET |
894 S3C2440_SDIFSTA_FIFOFAIL,
895 host->base + S3C2410_SDIFSTA);
900 mci_con = readl(host->base + S3C2410_SDICON);
901 mci_con |= S3C2410_SDICON_FIFORESET;
903 writel(mci_con, host->base + S3C2410_SDICON);
908 host->complete_what = COMPLETION_NONE;
911 s3cmci_check_sdio_irq(host);
912 mmc_request_done(host->mmc, mrq);
915 static void s3cmci_dma_setup(struct s3cmci_host *host,
916 enum s3c2410_dmasrc source)
918 static enum s3c2410_dmasrc last_source = -1;
921 if (last_source == source)
924 last_source = source;
926 s3c2410_dma_devconfig(host->dma, source,
927 host->mem->start + host->sdidata);
930 s3c2410_dma_config(host->dma, 4);
931 s3c2410_dma_set_buffdone_fn(host->dma,
932 s3cmci_dma_done_callback);
933 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
938 static void s3cmci_send_command(struct s3cmci_host *host,
939 struct mmc_command *cmd)
943 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
944 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
945 S3C2410_SDIIMSK_RESPONSECRC;
947 enable_imask(host, imsk);
950 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
951 else if (cmd->flags & MMC_RSP_PRESENT)
952 host->complete_what = COMPLETION_RSPFIN;
954 host->complete_what = COMPLETION_CMDSENT;
956 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
958 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
959 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
961 if (cmd->flags & MMC_RSP_PRESENT)
962 ccon |= S3C2410_SDICMDCON_WAITRSP;
964 if (cmd->flags & MMC_RSP_136)
965 ccon |= S3C2410_SDICMDCON_LONGRSP;
967 writel(ccon, host->base + S3C2410_SDICMDCON);
970 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
972 u32 dcon, imsk, stoptries = 3;
974 /* write DCON register */
977 writel(0, host->base + S3C2410_SDIDCON);
981 if ((data->blksz & 3) != 0) {
982 /* We cannot deal with unaligned blocks with more than
983 * one block being transfered. */
985 if (data->blocks > 1) {
986 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
991 while (readl(host->base + S3C2410_SDIDSTA) &
992 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
995 "mci_setup_data() transfer stillin progress.\n");
997 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1000 if ((stoptries--) == 0) {
1001 dbg_dumpregs(host, "DRF");
1006 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1008 if (s3cmci_host_usedma(host))
1009 dcon |= S3C2410_SDIDCON_DMAEN;
1011 if (host->bus_width == MMC_BUS_WIDTH_4)
1012 dcon |= S3C2410_SDIDCON_WIDEBUS;
1014 if (!(data->flags & MMC_DATA_STREAM))
1015 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1017 if (data->flags & MMC_DATA_WRITE) {
1018 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1019 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1022 if (data->flags & MMC_DATA_READ) {
1023 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1024 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1028 dcon |= S3C2440_SDIDCON_DS_WORD;
1029 dcon |= S3C2440_SDIDCON_DATSTART;
1032 writel(dcon, host->base + S3C2410_SDIDCON);
1034 /* write BSIZE register */
1036 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1038 /* add to IMASK register */
1039 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1040 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1042 enable_imask(host, imsk);
1044 /* write TIMER register */
1047 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1049 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1051 /* FIX: set slow clock to prevent timeouts on read */
1052 if (data->flags & MMC_DATA_READ)
1053 writel(0xFF, host->base + S3C2410_SDIPRE);
1059 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1061 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1063 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1065 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1067 host->pio_sgptr = 0;
1068 host->pio_bytes = 0;
1069 host->pio_count = 0;
1070 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1074 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1076 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1077 | S3C2410_SDIIMSK_RXFIFOLAST);
1083 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1086 int rw = data->flags & MMC_DATA_WRITE;
1088 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1090 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
1091 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1093 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1094 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1099 host->dma_complete = 0;
1100 host->dmatogo = dma_len;
1102 for (i = 0; i < dma_len; i++) {
1105 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1106 sg_dma_address(&data->sg[i]),
1107 sg_dma_len(&data->sg[i]));
1109 res = s3c2410_dma_enqueue(host->dma, host,
1110 sg_dma_address(&data->sg[i]),
1111 sg_dma_len(&data->sg[i]));
1114 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1119 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1124 static void s3cmci_send_request(struct mmc_host *mmc)
1126 struct s3cmci_host *host = mmc_priv(mmc);
1127 struct mmc_request *mrq = host->mrq;
1128 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1131 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1133 /* Clear command, data and fifo status registers
1134 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1136 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1137 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1138 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1141 int res = s3cmci_setup_data(host, cmd->data);
1146 dbg(host, dbg_err, "setup data error %d\n", res);
1148 cmd->data->error = res;
1150 mmc_request_done(mmc, mrq);
1154 if (s3cmci_host_usedma(host))
1155 res = s3cmci_prepare_dma(host, cmd->data);
1157 res = s3cmci_prepare_pio(host, cmd->data);
1160 dbg(host, dbg_err, "data prepare error %d\n", res);
1162 cmd->data->error = res;
1164 mmc_request_done(mmc, mrq);
1170 s3cmci_send_command(host, cmd);
1172 /* Enable Interrupt */
1173 s3cmci_enable_irq(host, true);
1176 static int s3cmci_card_present(struct mmc_host *mmc)
1178 struct s3cmci_host *host = mmc_priv(mmc);
1179 struct s3c24xx_mci_pdata *pdata = host->pdata;
1182 if (pdata->gpio_detect == 0)
1185 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1186 return ret ^ pdata->detect_invert;
1189 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1191 struct s3cmci_host *host = mmc_priv(mmc);
1193 host->status = "mmc request";
1194 host->cmd_is_stop = 0;
1197 if (s3cmci_card_present(mmc) == 0) {
1198 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1199 host->mrq->cmd->error = -ENOMEDIUM;
1200 mmc_request_done(mmc, mrq);
1202 s3cmci_send_request(mmc);
1205 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1210 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1211 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1213 if (host->real_rate <= ios->clock)
1220 host->prescaler = mci_psc;
1221 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1223 /* If requested clock is 0, real_rate will be 0, too */
1224 if (ios->clock == 0)
1225 host->real_rate = 0;
1228 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1230 struct s3cmci_host *host = mmc_priv(mmc);
1233 /* Set the power state */
1235 mci_con = readl(host->base + S3C2410_SDICON);
1237 switch (ios->power_mode) {
1240 s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK);
1241 s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD);
1242 s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0);
1243 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
1244 s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2);
1245 s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3);
1247 if (host->pdata->set_power)
1248 host->pdata->set_power(ios->power_mode, ios->vdd);
1251 mci_con |= S3C2410_SDICON_FIFORESET;
1257 gpio_direction_output(S3C2410_GPE(5), 0);
1260 mci_con |= S3C2440_SDICON_SDRESET;
1262 if (host->pdata->set_power)
1263 host->pdata->set_power(ios->power_mode, ios->vdd);
1268 s3cmci_set_clk(host, ios);
1270 /* Set CLOCK_ENABLE */
1272 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1274 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1276 writel(mci_con, host->base + S3C2410_SDICON);
1278 if ((ios->power_mode == MMC_POWER_ON) ||
1279 (ios->power_mode == MMC_POWER_UP)) {
1280 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1281 host->real_rate/1000, ios->clock/1000);
1283 dbg(host, dbg_conf, "powered down.\n");
1286 host->bus_width = ios->bus_width;
1289 static void s3cmci_reset(struct s3cmci_host *host)
1291 u32 con = readl(host->base + S3C2410_SDICON);
1293 con |= S3C2440_SDICON_SDRESET;
1294 writel(con, host->base + S3C2410_SDICON);
1297 static int s3cmci_get_ro(struct mmc_host *mmc)
1299 struct s3cmci_host *host = mmc_priv(mmc);
1300 struct s3c24xx_mci_pdata *pdata = host->pdata;
1303 if (pdata->no_wprotect)
1306 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1307 ret ^= pdata->wprotect_invert;
1312 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1314 struct s3cmci_host *host = mmc_priv(mmc);
1315 unsigned long flags;
1318 local_irq_save(flags);
1320 con = readl(host->base + S3C2410_SDICON);
1321 host->sdio_irqen = enable;
1323 if (enable == host->sdio_irqen)
1327 con |= S3C2410_SDICON_SDIOIRQ;
1328 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1330 if (!host->irq_state && !host->irq_disabled) {
1331 host->irq_state = true;
1332 enable_irq(host->irq);
1335 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1336 con &= ~S3C2410_SDICON_SDIOIRQ;
1338 if (!host->irq_enabled && host->irq_state) {
1339 disable_irq_nosync(host->irq);
1340 host->irq_state = false;
1344 writel(con, host->base + S3C2410_SDICON);
1347 local_irq_restore(flags);
1349 s3cmci_check_sdio_irq(host);
1352 static struct mmc_host_ops s3cmci_ops = {
1353 .request = s3cmci_request,
1354 .set_ios = s3cmci_set_ios,
1355 .get_ro = s3cmci_get_ro,
1356 .get_cd = s3cmci_card_present,
1357 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1360 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1361 /* This is currently here to avoid a number of if (host->pdata)
1362 * checks. Any zero fields to ensure reasonable defaults are picked. */
1365 #ifdef CONFIG_CPU_FREQ
1367 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1368 unsigned long val, void *data)
1370 struct s3cmci_host *host;
1371 struct mmc_host *mmc;
1372 unsigned long newclk;
1373 unsigned long flags;
1375 host = container_of(nb, struct s3cmci_host, freq_transition);
1376 newclk = clk_get_rate(host->clk);
1379 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1380 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1381 spin_lock_irqsave(&mmc->lock, flags);
1383 host->clk_rate = newclk;
1385 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1386 mmc->ios.clock != 0)
1387 s3cmci_set_clk(host, &mmc->ios);
1389 spin_unlock_irqrestore(&mmc->lock, flags);
1395 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1397 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1399 return cpufreq_register_notifier(&host->freq_transition,
1400 CPUFREQ_TRANSITION_NOTIFIER);
1403 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1405 cpufreq_unregister_notifier(&host->freq_transition,
1406 CPUFREQ_TRANSITION_NOTIFIER);
1410 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1415 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1421 #ifdef CONFIG_DEBUG_FS
1423 static int s3cmci_state_show(struct seq_file *seq, void *v)
1425 struct s3cmci_host *host = seq->private;
1427 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1428 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1429 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1430 seq_printf(seq, "is2440 = %d\n", host->is2440);
1431 seq_printf(seq, "IRQ = %d\n", host->irq);
1432 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1433 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1434 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1435 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1436 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1437 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1438 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1443 static int s3cmci_state_open(struct inode *inode, struct file *file)
1445 return single_open(file, s3cmci_state_show, inode->i_private);
1448 static const struct file_operations s3cmci_fops_state = {
1449 .owner = THIS_MODULE,
1450 .open = s3cmci_state_open,
1452 .llseek = seq_lseek,
1453 .release = single_release,
1456 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1459 unsigned short addr;
1460 unsigned char *name;
1480 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1482 struct s3cmci_host *host = seq->private;
1483 struct s3cmci_reg *rptr = debug_regs;
1485 for (; rptr->name; rptr++)
1486 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1487 readl(host->base + rptr->addr));
1489 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1494 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1496 return single_open(file, s3cmci_regs_show, inode->i_private);
1499 static const struct file_operations s3cmci_fops_regs = {
1500 .owner = THIS_MODULE,
1501 .open = s3cmci_regs_open,
1503 .llseek = seq_lseek,
1504 .release = single_release,
1507 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1509 struct device *dev = &host->pdev->dev;
1511 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1512 if (IS_ERR(host->debug_root)) {
1513 dev_err(dev, "failed to create debugfs root\n");
1517 host->debug_state = debugfs_create_file("state", 0444,
1518 host->debug_root, host,
1519 &s3cmci_fops_state);
1521 if (IS_ERR(host->debug_state))
1522 dev_err(dev, "failed to create debug state file\n");
1524 host->debug_regs = debugfs_create_file("regs", 0444,
1525 host->debug_root, host,
1528 if (IS_ERR(host->debug_regs))
1529 dev_err(dev, "failed to create debug regs file\n");
1532 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1534 debugfs_remove(host->debug_regs);
1535 debugfs_remove(host->debug_state);
1536 debugfs_remove(host->debug_root);
1540 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1541 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1543 #endif /* CONFIG_DEBUG_FS */
1545 static int __devinit s3cmci_probe(struct platform_device *pdev)
1547 struct s3cmci_host *host;
1548 struct mmc_host *mmc;
1553 is2440 = platform_get_device_id(pdev)->driver_data;
1555 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1561 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1562 ret = gpio_request(i, dev_name(&pdev->dev));
1564 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1566 for (i--; i >= S3C2410_GPE(5); i--)
1569 goto probe_free_host;
1573 host = mmc_priv(mmc);
1576 host->is2440 = is2440;
1578 host->pdata = pdev->dev.platform_data;
1580 pdev->dev.platform_data = &s3cmci_def_pdata;
1581 host->pdata = &s3cmci_def_pdata;
1584 spin_lock_init(&host->complete_lock);
1585 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1588 host->sdiimsk = S3C2440_SDIIMSK;
1589 host->sdidata = S3C2440_SDIDATA;
1592 host->sdiimsk = S3C2410_SDIIMSK;
1593 host->sdidata = S3C2410_SDIDATA;
1597 host->complete_what = COMPLETION_NONE;
1598 host->pio_active = XFER_NONE;
1600 #ifdef CONFIG_MMC_S3C_PIODMA
1601 host->dodma = host->pdata->dma;
1604 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 "failed to get io memory region resouce.\n");
1610 goto probe_free_gpio;
1613 host->mem = request_mem_region(host->mem->start,
1614 resource_size(host->mem), pdev->name);
1617 dev_err(&pdev->dev, "failed to request io memory region.\n");
1619 goto probe_free_gpio;
1622 host->base = ioremap(host->mem->start, resource_size(host->mem));
1624 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1626 goto probe_free_mem_region;
1629 host->irq = platform_get_irq(pdev, 0);
1630 if (host->irq == 0) {
1631 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1636 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1637 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1642 /* We get spurious interrupts even when we have set the IMSK
1643 * register to ignore everything, so use disable_irq() to make
1644 * ensure we don't lock the system with un-serviceable requests. */
1646 disable_irq(host->irq);
1647 host->irq_state = false;
1649 if (!host->pdata->no_detect) {
1650 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1652 dev_err(&pdev->dev, "failed to get detect gpio\n");
1653 goto probe_free_irq;
1656 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1658 if (host->irq_cd >= 0) {
1659 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1660 IRQF_TRIGGER_RISING |
1661 IRQF_TRIGGER_FALLING,
1662 DRIVER_NAME, host)) {
1664 "can't get card detect irq.\n");
1666 goto probe_free_gpio_cd;
1669 dev_warn(&pdev->dev,
1670 "host detect has no irq available\n");
1671 gpio_direction_input(host->pdata->gpio_detect);
1676 if (!host->pdata->no_wprotect) {
1677 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1679 dev_err(&pdev->dev, "failed to get writeprotect\n");
1680 goto probe_free_irq_cd;
1683 gpio_direction_input(host->pdata->gpio_wprotect);
1686 /* depending on the dma state, get a dma channel to use. */
1688 if (s3cmci_host_usedma(host)) {
1689 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1691 if (host->dma < 0) {
1692 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1693 if (!s3cmci_host_canpio()) {
1695 goto probe_free_gpio_wp;
1697 dev_warn(&pdev->dev, "falling back to PIO.\n");
1703 host->clk = clk_get(&pdev->dev, "sdi");
1704 if (IS_ERR(host->clk)) {
1705 dev_err(&pdev->dev, "failed to find clock source.\n");
1706 ret = PTR_ERR(host->clk);
1708 goto probe_free_dma;
1711 ret = clk_enable(host->clk);
1713 dev_err(&pdev->dev, "failed to enable clock source.\n");
1717 host->clk_rate = clk_get_rate(host->clk);
1719 mmc->ops = &s3cmci_ops;
1720 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1721 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1722 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1724 mmc->caps = MMC_CAP_4_BIT_DATA;
1726 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1727 mmc->f_max = host->clk_rate / host->clk_div;
1729 if (host->pdata->ocr_avail)
1730 mmc->ocr_avail = host->pdata->ocr_avail;
1732 mmc->max_blk_count = 4095;
1733 mmc->max_blk_size = 4095;
1734 mmc->max_req_size = 4095 * 512;
1735 mmc->max_seg_size = mmc->max_req_size;
1737 mmc->max_phys_segs = 128;
1738 mmc->max_hw_segs = 128;
1740 dbg(host, dbg_debug,
1741 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1742 (host->is2440?"2440":""),
1743 host->base, host->irq, host->irq_cd, host->dma);
1745 ret = s3cmci_cpufreq_register(host);
1747 dev_err(&pdev->dev, "failed to register cpufreq\n");
1751 ret = mmc_add_host(mmc);
1753 dev_err(&pdev->dev, "failed to add mmc host.\n");
1757 s3cmci_debugfs_attach(host);
1759 platform_set_drvdata(pdev, mmc);
1760 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1761 s3cmci_host_usedma(host) ? "dma" : "pio",
1762 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1767 s3cmci_cpufreq_deregister(host);
1770 clk_disable(host->clk);
1776 if (s3cmci_host_usedma(host))
1777 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1780 if (!host->pdata->no_wprotect)
1781 gpio_free(host->pdata->gpio_wprotect);
1784 if (!host->pdata->no_detect)
1785 gpio_free(host->pdata->gpio_detect);
1788 if (host->irq_cd >= 0)
1789 free_irq(host->irq_cd, host);
1792 free_irq(host->irq, host);
1795 iounmap(host->base);
1797 probe_free_mem_region:
1798 release_mem_region(host->mem->start, resource_size(host->mem));
1801 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1811 static void s3cmci_shutdown(struct platform_device *pdev)
1813 struct mmc_host *mmc = platform_get_drvdata(pdev);
1814 struct s3cmci_host *host = mmc_priv(mmc);
1816 if (host->irq_cd >= 0)
1817 free_irq(host->irq_cd, host);
1819 s3cmci_debugfs_remove(host);
1820 s3cmci_cpufreq_deregister(host);
1821 mmc_remove_host(mmc);
1822 clk_disable(host->clk);
1825 static int __devexit s3cmci_remove(struct platform_device *pdev)
1827 struct mmc_host *mmc = platform_get_drvdata(pdev);
1828 struct s3cmci_host *host = mmc_priv(mmc);
1829 struct s3c24xx_mci_pdata *pd = host->pdata;
1832 s3cmci_shutdown(pdev);
1836 tasklet_disable(&host->pio_tasklet);
1838 if (s3cmci_host_usedma(host))
1839 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1841 free_irq(host->irq, host);
1843 if (!pd->no_wprotect)
1844 gpio_free(pd->gpio_wprotect);
1847 gpio_free(pd->gpio_detect);
1849 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1853 iounmap(host->base);
1854 release_mem_region(host->mem->start, resource_size(host->mem));
1860 static struct platform_device_id s3cmci_driver_ids[] = {
1862 .name = "s3c2410-sdi",
1865 .name = "s3c2412-sdi",
1868 .name = "s3c2440-sdi",
1874 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1879 static int s3cmci_suspend(struct device *dev)
1881 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1882 struct pm_message event = { PM_EVENT_SUSPEND };
1884 return mmc_suspend_host(mmc, event);
1887 static int s3cmci_resume(struct device *dev)
1889 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1891 return mmc_resume_host(mmc);
1894 static const struct dev_pm_ops s3cmci_pm = {
1895 .suspend = s3cmci_suspend,
1896 .resume = s3cmci_resume,
1899 #define s3cmci_pm_ops &s3cmci_pm
1900 #else /* CONFIG_PM */
1901 #define s3cmci_pm_ops NULL
1902 #endif /* CONFIG_PM */
1905 static struct platform_driver s3cmci_driver = {
1908 .owner = THIS_MODULE,
1909 .pm = s3cmci_pm_ops,
1911 .id_table = s3cmci_driver_ids,
1912 .probe = s3cmci_probe,
1913 .remove = __devexit_p(s3cmci_remove),
1914 .shutdown = s3cmci_shutdown,
1917 static int __init s3cmci_init(void)
1919 return platform_driver_register(&s3cmci_driver);
1922 static void __exit s3cmci_exit(void)
1924 platform_driver_unregister(&s3cmci_driver);
1927 module_init(s3cmci_init);
1928 module_exit(s3cmci_exit);
1930 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1931 MODULE_LICENSE("GPL v2");
1932 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");