drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * Current driver maintained by Ben Dooks and Simtec Electronics
   7  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/clk.h>
  17 #include <linux/mmc/host.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/gpio.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/dma.h>
  27
  28 #include <mach/regs-sdi.h>
  29
  30 #include <linux/platform_data/mmc-s3cmci.h>
  31
  32 #include "s3cmci.h"
  33
  34 #define DRIVER_NAME "s3c-mci"
  35
  36 enum dbg_channels {
  37         dbg_err   = (1 << 0),
  38         dbg_debug = (1 << 1),
  39         dbg_info  = (1 << 2),
  40         dbg_irq   = (1 << 3),
  41         dbg_sg    = (1 << 4),
  42         dbg_dma   = (1 << 5),
  43         dbg_pio   = (1 << 6),
  44         dbg_fail  = (1 << 7),
  45         dbg_conf  = (1 << 8),
  46 };
  47
  48 static const int dbgmap_err   = dbg_fail;
  49 static const int dbgmap_info  = dbg_info | dbg_conf;
  50 static const int dbgmap_debug = dbg_err | dbg_debug;
  51
  52 #define dbg(host, channels, args...)              \
  53         do {                                      \
  54         if (dbgmap_err & channels)                \
  55                 dev_err(&host->pdev->dev, args);  \
  56         else if (dbgmap_info & channels)          \
  57                 dev_info(&host->pdev->dev, args); \
  58         else if (dbgmap_debug & channels)         \
  59                 dev_dbg(&host->pdev->dev, args);  \
  60         } while (0)
  61
  62 static struct s3c2410_dma_client s3cmci_dma_client = {
  63         .name           = "s3c-mci",
  64 };
  65
  66 static void finalize_request(struct s3cmci_host *host);
  67 static void s3cmci_send_request(struct mmc_host *mmc);
  68 static void s3cmci_reset(struct s3cmci_host *host);
  69
  70 #ifdef CONFIG_MMC_DEBUG
  71
  72 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  73 {
  74         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
  75         u32 datcon, datcnt, datsta, fsta, imask;
  76
  77         con     = readl(host->base + S3C2410_SDICON);
  78         pre     = readl(host->base + S3C2410_SDIPRE);
  79         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
  80         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
  81         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
  82         r0      = readl(host->base + S3C2410_SDIRSP0);
  83         r1      = readl(host->base + S3C2410_SDIRSP1);
  84         r2      = readl(host->base + S3C2410_SDIRSP2);
  85         r3      = readl(host->base + S3C2410_SDIRSP3);
  86         timer   = readl(host->base + S3C2410_SDITIMER);
  87         bsize   = readl(host->base + S3C2410_SDIBSIZE);
  88         datcon  = readl(host->base + S3C2410_SDIDCON);
  89         datcnt  = readl(host->base + S3C2410_SDIDCNT);
  90         datsta  = readl(host->base + S3C2410_SDIDSTA);
  91         fsta    = readl(host->base + S3C2410_SDIFSTA);
  92         imask   = readl(host->base + host->sdiimsk);
  93
  94         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
  95                                 prefix, con, pre, timer);
  96
  97         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  98                                 prefix, cmdcon, cmdarg, cmdsta);
  99
 100         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 101                                " DSTA:[%08x] DCNT:[%08x]\n",
 102                                 prefix, datcon, fsta, datsta, datcnt);
 103
 104         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 105                                "   R2:[%08x]   R3:[%08x]\n",
 106                                 prefix, r0, r1, r2, r3);
 107 }
 108
 109 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 110                            int stop)
 111 {
 112         snprintf(host->dbgmsg_cmd, 300,
 113                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 114                  host->ccnt, (stop ? " (STOP)" : ""),
 115                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 116
 117         if (cmd->data) {
 118                 snprintf(host->dbgmsg_dat, 300,
 119                          "#%u bsize:%u blocks:%u bytes:%u",
 120                          host->dcnt, cmd->data->blksz,
 121                          cmd->data->blocks,
 122                          cmd->data->blocks * cmd->data->blksz);
 123         } else {
 124                 host->dbgmsg_dat[0] = '\0';
 125         }
 126 }
 127
 128 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 129                         int fail)
 130 {
 131         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 132
 133         if (!cmd)
 134                 return;
 135
 136         if (cmd->error == 0) {
 137                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 138                         host->dbgmsg_cmd, cmd->resp[0]);
 139         } else {
 140                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 141                         cmd->error, host->dbgmsg_cmd, host->status);
 142         }
 143
 144         if (!cmd->data)
 145                 return;
 146
 147         if (cmd->data->error == 0) {
 148                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 149         } else {
 150                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 151                         cmd->data->error, host->dbgmsg_dat,
 152                         readl(host->base + S3C2410_SDIDCNT));
 153         }
 154 }
 155 #else
 156 static void dbg_dumpcmd(struct s3cmci_host *host,
 157                         struct mmc_command *cmd, int fail) { }
 158
 159 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 160                            int stop) { }
 161
 162 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 163
 164 #endif /* CONFIG_MMC_DEBUG */
 165
 166 /**
 167  * s3cmci_host_usedma - return whether the host is using dma or pio
 168  * @host: The host state
 169  *
 170  * Return true if the host is using DMA to transfer data, else false
 171  * to use PIO mode. Will return static data depending on the driver
 172  * configuration.
 173  */
 174 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 175 {
 176 #ifdef CONFIG_MMC_S3C_PIO
 177         return false;
 178 #elif defined(CONFIG_MMC_S3C_DMA)
 179         return true;
 180 #else
 181         return host->dodma;
 182 #endif
 183 }
 184
 185 /**
 186  * s3cmci_host_canpio - return true if host has pio code available
 187  *
 188  * Return true if the driver has been compiled with the PIO support code
 189  * available.
 190  */
 191 static inline bool s3cmci_host_canpio(void)
 192 {
 193 #ifdef CONFIG_MMC_S3C_PIO
 194         return true;
 195 #else
 196         return false;
 197 #endif
 198 }
 199
 200 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 201 {
 202         u32 newmask;
 203
 204         newmask = readl(host->base + host->sdiimsk);
 205         newmask |= imask;
 206
 207         writel(newmask, host->base + host->sdiimsk);
 208
 209         return newmask;
 210 }
 211
 212 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 213 {
 214         u32 newmask;
 215
 216         newmask = readl(host->base + host->sdiimsk);
 217         newmask &= ~imask;
 218
 219         writel(newmask, host->base + host->sdiimsk);
 220
 221         return newmask;
 222 }
 223
 224 static inline void clear_imask(struct s3cmci_host *host)
 225 {
 226         u32 mask = readl(host->base + host->sdiimsk);
 227
 228         /* preserve the SDIO IRQ mask state */
 229         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 230         writel(mask, host->base + host->sdiimsk);
 231 }
 232
 233 /**
 234  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 235  * @host: The host to check.
 236  *
 237  * Test to see if the SDIO interrupt is being signalled in case the
 238  * controller has failed to re-detect a card interrupt. Read GPE8 and
 239  * see if it is low and if so, signal a SDIO interrupt.
 240  *
 241  * This is currently called if a request is finished (we assume that the
 242  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 243  * already being indicated.
 244 */
 245 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 246 {
 247         if (host->sdio_irqen) {
 248                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 249                         pr_debug("%s: signalling irq\n", __func__);
 250                         mmc_signal_sdio_irq(host->mmc);
 251                 }
 252         }
 253 }
 254
 255 static inline int get_data_buffer(struct s3cmci_host *host,
 256                                   u32 *bytes, u32 **pointer)
 257 {
 258         struct scatterlist *sg;
 259
 260         if (host->pio_active == XFER_NONE)
 261                 return -EINVAL;
 262
 263         if ((!host->mrq) || (!host->mrq->data))
 264                 return -EINVAL;
 265
 266         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 267                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 268                       host->pio_sgptr, host->mrq->data->sg_len);
 269                 return -EBUSY;
 270         }
 271         sg = &host->mrq->data->sg[host->pio_sgptr];
 272
 273         *bytes = sg->length;
 274         *pointer = sg_virt(sg);
 275
 276         host->pio_sgptr++;
 277
 278         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 279             host->pio_sgptr, host->mrq->data->sg_len);
 280
 281         return 0;
 282 }
 283
 284 static inline u32 fifo_count(struct s3cmci_host *host)
 285 {
 286         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 287
 288         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 289         return fifostat;
 290 }
 291
 292 static inline u32 fifo_free(struct s3cmci_host *host)
 293 {
 294         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 295
 296         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 297         return 63 - fifostat;
 298 }
 299
 300 /**
 301  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 302  * @host: The device state.
 303  * @more: True if more IRQs are expected from transfer.
 304  *
 305  * Enable the main IRQ if needed after it has been disabled.
 306  *
 307  * The IRQ can be one of the following states:
 308  *      - disabled during IDLE
 309  *      - disabled whilst processing data
 310  *      - enabled during transfer
 311  *      - enabled whilst awaiting SDIO interrupt detection
 312  */
 313 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 314 {
 315         unsigned long flags;
 316         bool enable = false;
 317
 318         local_irq_save(flags);
 319
 320         host->irq_enabled = more;
 321         host->irq_disabled = false;
 322
 323         enable = more | host->sdio_irqen;
 324
 325         if (host->irq_state != enable) {
 326                 host->irq_state = enable;
 327
 328                 if (enable)
 329                         enable_irq(host->irq);
 330                 else
 331                         disable_irq(host->irq);
 332         }
 333
 334         local_irq_restore(flags);
 335 }
 336
 337 /**
 338  *
 339  */
 340 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 341 {
 342         unsigned long flags;
 343
 344         local_irq_save(flags);
 345
 346         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 347
 348         host->irq_disabled = transfer;
 349
 350         if (transfer && host->irq_state) {
 351                 host->irq_state = false;
 352                 disable_irq(host->irq);
 353         }
 354
 355         local_irq_restore(flags);
 356 }
 357
 358 static void do_pio_read(struct s3cmci_host *host)
 359 {
 360         int res;
 361         u32 fifo;
 362         u32 *ptr;
 363         u32 fifo_words;
 364         void __iomem *from_ptr;
 365
 366         /* write real prescaler to host, it might be set slow to fix */
 367         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 368
 369         from_ptr = host->base + host->sdidata;
 370
 371         while ((fifo = fifo_count(host))) {
 372                 if (!host->pio_bytes) {
 373                         res = get_data_buffer(host, &host->pio_bytes,
 374                                               &host->pio_ptr);
 375                         if (res) {
 376                                 host->pio_active = XFER_NONE;
 377                                 host->complete_what = COMPLETION_FINALIZE;
 378
 379                                 dbg(host, dbg_pio, "pio_read(): "
 380                                     "complete (no more data).\n");
 381                                 return;
 382                         }
 383
 384                         dbg(host, dbg_pio,
 385                             "pio_read(): new target: [%i]@[%p]\n",
 386                             host->pio_bytes, host->pio_ptr);
 387                 }
 388
 389                 dbg(host, dbg_pio,
 390                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 391                     fifo, host->pio_bytes,
 392                     readl(host->base + S3C2410_SDIDCNT));
 393
 394                 /* If we have reached the end of the block, we can
 395                  * read a word and get 1 to 3 bytes.  If we in the
 396                  * middle of the block, we have to read full words,
 397                  * otherwise we will write garbage, so round down to
 398                  * an even multiple of 4. */
 399                 if (fifo >= host->pio_bytes)
 400                         fifo = host->pio_bytes;
 401                 else
 402                         fifo -= fifo & 3;
 403
 404                 host->pio_bytes -= fifo;
 405                 host->pio_count += fifo;
 406
 407                 fifo_words = fifo >> 2;
 408                 ptr = host->pio_ptr;
 409                 while (fifo_words--)
 410                         *ptr++ = readl(from_ptr);
 411                 host->pio_ptr = ptr;
 412
 413                 if (fifo & 3) {
 414                         u32 n = fifo & 3;
 415                         u32 data = readl(from_ptr);
 416                         u8 *p = (u8 *)host->pio_ptr;
 417
 418                         while (n--) {
 419                                 *p++ = data;
 420                                 data >>= 8;
 421                         }
 422                 }
 423         }
 424
 425         if (!host->pio_bytes) {
 426                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 427                 if (res) {
 428                         dbg(host, dbg_pio,
 429                             "pio_read(): complete (no more buffers).\n");
 430                         host->pio_active = XFER_NONE;
 431                         host->complete_what = COMPLETION_FINALIZE;
 432
 433                         return;
 434                 }
 435         }
 436
 437         enable_imask(host,
 438                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 439 }
 440
 441 static void do_pio_write(struct s3cmci_host *host)
 442 {
 443         void __iomem *to_ptr;
 444         int res;
 445         u32 fifo;
 446         u32 *ptr;
 447
 448         to_ptr = host->base + host->sdidata;
 449
 450         while ((fifo = fifo_free(host)) > 3) {
 451                 if (!host->pio_bytes) {
 452                         res = get_data_buffer(host, &host->pio_bytes,
 453                                                         &host->pio_ptr);
 454                         if (res) {
 455                                 dbg(host, dbg_pio,
 456                                     "pio_write(): complete (no more data).\n");
 457                                 host->pio_active = XFER_NONE;
 458
 459                                 return;
 460                         }
 461
 462                         dbg(host, dbg_pio,
 463                             "pio_write(): new source: [%i]@[%p]\n",
 464                             host->pio_bytes, host->pio_ptr);
 465
 466                 }
 467
 468                 /* If we have reached the end of the block, we have to
 469                  * write exactly the remaining number of bytes.  If we
 470                  * in the middle of the block, we have to write full
 471                  * words, so round down to an even multiple of 4. */
 472                 if (fifo >= host->pio_bytes)
 473                         fifo = host->pio_bytes;
 474                 else
 475                         fifo -= fifo & 3;
 476
 477                 host->pio_bytes -= fifo;
 478                 host->pio_count += fifo;
 479
 480                 fifo = (fifo + 3) >> 2;
 481                 ptr = host->pio_ptr;
 482                 while (fifo--)
 483                         writel(*ptr++, to_ptr);
 484                 host->pio_ptr = ptr;
 485         }
 486
 487         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 488 }
 489
 490 static void pio_tasklet(unsigned long data)
 491 {
 492         struct s3cmci_host *host = (struct s3cmci_host *) data;
 493
 494         s3cmci_disable_irq(host, true);
 495
 496         if (host->pio_active == XFER_WRITE)
 497                 do_pio_write(host);
 498
 499         if (host->pio_active == XFER_READ)
 500                 do_pio_read(host);
 501
 502         if (host->complete_what == COMPLETION_FINALIZE) {
 503                 clear_imask(host);
 504                 if (host->pio_active != XFER_NONE) {
 505                         dbg(host, dbg_err, "unfinished %s "
 506                             "- pio_count:[%u] pio_bytes:[%u]\n",
 507                             (host->pio_active == XFER_READ) ? "read" : "write",
 508                             host->pio_count, host->pio_bytes);
 509
 510                         if (host->mrq->data)
 511                                 host->mrq->data->error = -EINVAL;
 512                 }
 513
 514                 s3cmci_enable_irq(host, false);
 515                 finalize_request(host);
 516         } else
 517                 s3cmci_enable_irq(host, true);
 518 }
 519
 520 /*
 521  * ISR for SDI Interface IRQ
 522  * Communication between driver and ISR works as follows:
 523  *   host->mrq                  points to current request
 524  *   host->complete_what        Indicates when the request is considered done
 525  *     COMPLETION_CMDSENT         when the command was sent
 526  *     COMPLETION_RSPFIN          when a response was received
 527  *     COMPLETION_XFERFINISH      when the data transfer is finished
 528  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 529  *   host->complete_request     is the completion-object the driver waits for
 530  *
 531  * 1) Driver sets up host->mrq and host->complete_what
 532  * 2) Driver prepares the transfer
 533  * 3) Driver enables interrupts
 534  * 4) Driver starts transfer
 535  * 5) Driver waits for host->complete_rquest
 536  * 6) ISR checks for request status (errors and success)
 537  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 538  * 7) ISR completes host->complete_request
 539  * 8) ISR disables interrupts
 540  * 9) Driver wakes up and takes care of the request
 541  *
 542  * Note: "->error"-fields are expected to be set to 0 before the request
 543  *       was issued by mmc.c - therefore they are only set, when an error
 544  *       contition comes up
 545  */
 546
 547 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 548 {
 549         struct s3cmci_host *host = dev_id;
 550         struct mmc_command *cmd;
 551         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 552         u32 mci_cclear = 0, mci_dclear;
 553         unsigned long iflags;
 554
 555         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 556         mci_imsk = readl(host->base + host->sdiimsk);
 557
 558         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 559                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 560                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 561                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 562
 563                         mmc_signal_sdio_irq(host->mmc);
 564                         return IRQ_HANDLED;
 565                 }
 566         }
 567
 568         spin_lock_irqsave(&host->complete_lock, iflags);
 569
 570         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 571         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 572         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 573         mci_dclear = 0;
 574
 575         if ((host->complete_what == COMPLETION_NONE) ||
 576             (host->complete_what == COMPLETION_FINALIZE)) {
 577                 host->status = "nothing to complete";
 578                 clear_imask(host);
 579                 goto irq_out;
 580         }
 581
 582         if (!host->mrq) {
 583                 host->status = "no active mrq";
 584                 clear_imask(host);
 585                 goto irq_out;
 586         }
 587
 588         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 589
 590         if (!cmd) {
 591                 host->status = "no active cmd";
 592                 clear_imask(host);
 593                 goto irq_out;
 594         }
 595
 596         if (!s3cmci_host_usedma(host)) {
 597                 if ((host->pio_active == XFER_WRITE) &&
 598                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 599
 600                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 601                         tasklet_schedule(&host->pio_tasklet);
 602                         host->status = "pio tx";
 603                 }
 604
 605                 if ((host->pio_active == XFER_READ) &&
 606                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 607
 608                         disable_imask(host,
 609                                       S3C2410_SDIIMSK_RXFIFOHALF |
 610                                       S3C2410_SDIIMSK_RXFIFOLAST);
 611
 612                         tasklet_schedule(&host->pio_tasklet);
 613                         host->status = "pio rx";
 614                 }
 615         }
 616
 617         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 618                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 619                 cmd->error = -ETIMEDOUT;
 620                 host->status = "error: command timeout";
 621                 goto fail_transfer;
 622         }
 623
 624         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 625                 if (host->complete_what == COMPLETION_CMDSENT) {
 626                         host->status = "ok: command sent";
 627                         goto close_transfer;
 628                 }
 629
 630                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 631         }
 632
 633         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 634                 if (cmd->flags & MMC_RSP_CRC) {
 635                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 636                                 dbg(host, dbg_irq,
 637                                     "fixup: ignore CRC fail with long rsp\n");
 638                         } else {
 639                                 /* note, we used to fail the transfer
 640                                  * here, but it seems that this is just
 641                                  * the hardware getting it wrong.
 642                                  *
 643                                  * cmd->error = -EILSEQ;
 644                                  * host->status = "error: bad command crc";
 645                                  * goto fail_transfer;
 646                                 */
 647                         }
 648                 }
 649
 650                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 651         }
 652
 653         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 654                 if (host->complete_what == COMPLETION_RSPFIN) {
 655                         host->status = "ok: command response received";
 656                         goto close_transfer;
 657                 }
 658
 659                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 660                         host->complete_what = COMPLETION_XFERFINISH;
 661
 662                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 663         }
 664
 665         /* errors handled after this point are only relevant
 666            when a data transfer is in progress */
 667
 668         if (!cmd->data)
 669                 goto clear_status_bits;
 670
 671         /* Check for FIFO failure */
 672         if (host->is2440) {
 673                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 674                         dbg(host, dbg_err, "FIFO failure\n");
 675                         host->mrq->data->error = -EILSEQ;
 676                         host->status = "error: 2440 fifo failure";
 677                         goto fail_transfer;
 678                 }
 679         } else {
 680                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 681                         dbg(host, dbg_err, "FIFO failure\n");
 682                         cmd->data->error = -EILSEQ;
 683                         host->status = "error:  fifo failure";
 684                         goto fail_transfer;
 685                 }
 686         }
 687
 688         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 689                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 690                 cmd->data->error = -EILSEQ;
 691                 host->status = "error: bad data crc (outgoing)";
 692                 goto fail_transfer;
 693         }
 694
 695         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 696                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 697                 cmd->data->error = -EILSEQ;
 698                 host->status = "error: bad data crc (incoming)";
 699                 goto fail_transfer;
 700         }
 701
 702         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 703                 dbg(host, dbg_err, "data timeout\n");
 704                 cmd->data->error = -ETIMEDOUT;
 705                 host->status = "error: data timeout";
 706                 goto fail_transfer;
 707         }
 708
 709         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 710                 if (host->complete_what == COMPLETION_XFERFINISH) {
 711                         host->status = "ok: data transfer completed";
 712                         goto close_transfer;
 713                 }
 714
 715                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 716                         host->complete_what = COMPLETION_RSPFIN;
 717
 718                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 719         }
 720
 721 clear_status_bits:
 722         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 723         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 724
 725         goto irq_out;
 726
 727 fail_transfer:
 728         host->pio_active = XFER_NONE;
 729
 730 close_transfer:
 731         host->complete_what = COMPLETION_FINALIZE;
 732
 733         clear_imask(host);
 734         tasklet_schedule(&host->pio_tasklet);
 735
 736         goto irq_out;
 737
 738 irq_out:
 739         dbg(host, dbg_irq,
 740             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 741             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 742
 743         spin_unlock_irqrestore(&host->complete_lock, iflags);
 744         return IRQ_HANDLED;
 745
 746 }
 747
 748 /*
 749  * ISR for the CardDetect Pin
 750 */
 751
 752 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 753 {
 754         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 755
 756         dbg(host, dbg_irq, "card detect\n");
 757
 758         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 759
 760         return IRQ_HANDLED;
 761 }
 762
 763 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
 764                                      void *buf_id, int size,
 765                                      enum s3c2410_dma_buffresult result)
 766 {
 767         struct s3cmci_host *host = buf_id;
 768         unsigned long iflags;
 769         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
 770
 771         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 772         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 773         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 774         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 775
 776         BUG_ON(!host->mrq);
 777         BUG_ON(!host->mrq->data);
 778         BUG_ON(!host->dmatogo);
 779
 780         spin_lock_irqsave(&host->complete_lock, iflags);
 781
 782         if (result != S3C2410_RES_OK) {
 783                 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
 784                         "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
 785                         mci_csta, mci_dsta, mci_fsta,
 786                         mci_dcnt, result, host->dmatogo);
 787
 788                 goto fail_request;
 789         }
 790
 791         host->dmatogo--;
 792         if (host->dmatogo) {
 793                 dbg(host, dbg_dma, "DMA DONE  Size:%i DSTA:[%08x] "
 794                         "DCNT:[%08x] toGo:%u\n",
 795                         size, mci_dsta, mci_dcnt, host->dmatogo);
 796
 797                 goto out;
 798         }
 799
 800         dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
 801                 size, mci_dsta, mci_dcnt);
 802
 803         host->dma_complete = 1;
 804         host->complete_what = COMPLETION_FINALIZE;
 805
 806 out:
 807         tasklet_schedule(&host->pio_tasklet);
 808         spin_unlock_irqrestore(&host->complete_lock, iflags);
 809         return;
 810
 811 fail_request:
 812         host->mrq->data->error = -EINVAL;
 813         host->complete_what = COMPLETION_FINALIZE;
 814         clear_imask(host);
 815
 816         goto out;
 817 }
 818
 819 static void finalize_request(struct s3cmci_host *host)
 820 {
 821         struct mmc_request *mrq = host->mrq;
 822         struct mmc_command *cmd;
 823         int debug_as_failure = 0;
 824
 825         if (host->complete_what != COMPLETION_FINALIZE)
 826                 return;
 827
 828         if (!mrq)
 829                 return;
 830         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 831
 832         if (cmd->data && (cmd->error == 0) &&
 833             (cmd->data->error == 0)) {
 834                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 835                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 836                             host->dma_complete);
 837                         return;
 838                 }
 839         }
 840
 841         /* Read response from controller. */
 842         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 843         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 844         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 845         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 846
 847         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 848
 849         if (cmd->error)
 850                 debug_as_failure = 1;
 851
 852         if (cmd->data && cmd->data->error)
 853                 debug_as_failure = 1;
 854
 855         dbg_dumpcmd(host, cmd, debug_as_failure);
 856
 857         /* Cleanup controller */
 858         writel(0, host->base + S3C2410_SDICMDARG);
 859         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 860         writel(0, host->base + S3C2410_SDICMDCON);
 861         clear_imask(host);
 862
 863         if (cmd->data && cmd->error)
 864                 cmd->data->error = cmd->error;
 865
 866         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 867                 host->cmd_is_stop = 1;
 868                 s3cmci_send_request(host->mmc);
 869                 return;
 870         }
 871
 872         /* If we have no data transfer we are finished here */
 873         if (!mrq->data)
 874                 goto request_done;
 875
 876         /* Calculate the amout of bytes transfer if there was no error */
 877         if (mrq->data->error == 0) {
 878                 mrq->data->bytes_xfered =
 879                         (mrq->data->blocks * mrq->data->blksz);
 880         } else {
 881                 mrq->data->bytes_xfered = 0;
 882         }
 883
 884         /* If we had an error while transferring data we flush the
 885          * DMA channel and the fifo to clear out any garbage. */
 886         if (mrq->data->error != 0) {
 887                 if (s3cmci_host_usedma(host))
 888                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
 889
 890                 if (host->is2440) {
 891                         /* Clear failure register and reset fifo. */
 892                         writel(S3C2440_SDIFSTA_FIFORESET |
 893                                S3C2440_SDIFSTA_FIFOFAIL,
 894                                host->base + S3C2410_SDIFSTA);
 895                 } else {
 896                         u32 mci_con;
 897
 898                         /* reset fifo */
 899                         mci_con = readl(host->base + S3C2410_SDICON);
 900                         mci_con |= S3C2410_SDICON_FIFORESET;
 901
 902                         writel(mci_con, host->base + S3C2410_SDICON);
 903                 }
 904         }
 905
 906 request_done:
 907         host->complete_what = COMPLETION_NONE;
 908         host->mrq = NULL;
 909
 910         s3cmci_check_sdio_irq(host);
 911         mmc_request_done(host->mmc, mrq);
 912 }
 913
 914 static void s3cmci_dma_setup(struct s3cmci_host *host,
 915                              enum dma_data_direction source)
 916 {
 917         static enum dma_data_direction last_source = -1;
 918         static int setup_ok;
 919
 920         if (last_source == source)
 921                 return;
 922
 923         last_source = source;
 924
 925         s3c2410_dma_devconfig(host->dma, source,
 926                               host->mem->start + host->sdidata);
 927
 928         if (!setup_ok) {
 929                 s3c2410_dma_config(host->dma, 4);
 930                 s3c2410_dma_set_buffdone_fn(host->dma,
 931                                             s3cmci_dma_done_callback);
 932                 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
 933                 setup_ok = 1;
 934         }
 935 }
 936
 937 static void s3cmci_send_command(struct s3cmci_host *host,
 938                                         struct mmc_command *cmd)
 939 {
 940         u32 ccon, imsk;
 941
 942         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 943                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 944                 S3C2410_SDIIMSK_RESPONSECRC;
 945
 946         enable_imask(host, imsk);
 947
 948         if (cmd->data)
 949                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 950         else if (cmd->flags & MMC_RSP_PRESENT)
 951                 host->complete_what = COMPLETION_RSPFIN;
 952         else
 953                 host->complete_what = COMPLETION_CMDSENT;
 954
 955         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 956
 957         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 958         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 959
 960         if (cmd->flags & MMC_RSP_PRESENT)
 961                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 962
 963         if (cmd->flags & MMC_RSP_136)
 964                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 965
 966         writel(ccon, host->base + S3C2410_SDICMDCON);
 967 }
 968
 969 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 970 {
 971         u32 dcon, imsk, stoptries = 3;
 972
 973         /* write DCON register */
 974
 975         if (!data) {
 976                 writel(0, host->base + S3C2410_SDIDCON);
 977                 return 0;
 978         }
 979
 980         if ((data->blksz & 3) != 0) {
 981                 /* We cannot deal with unaligned blocks with more than
 982                  * one block being transferred. */
 983
 984                 if (data->blocks > 1) {
 985                         pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
 986                         return -EINVAL;
 987                 }
 988         }
 989
 990         while (readl(host->base + S3C2410_SDIDSTA) &
 991                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 992
 993                 dbg(host, dbg_err,
 994                     "mci_setup_data() transfer stillin progress.\n");
 995
 996                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 997                 s3cmci_reset(host);
 998
 999                 if ((stoptries--) == 0) {
1000                         dbg_dumpregs(host, "DRF");
1001                         return -EINVAL;
1002                 }
1003         }
1004
1005         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1006
1007         if (s3cmci_host_usedma(host))
1008                 dcon |= S3C2410_SDIDCON_DMAEN;
1009
1010         if (host->bus_width == MMC_BUS_WIDTH_4)
1011                 dcon |= S3C2410_SDIDCON_WIDEBUS;
1012
1013         if (!(data->flags & MMC_DATA_STREAM))
1014                 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1015
1016         if (data->flags & MMC_DATA_WRITE) {
1017                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1018                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1019         }
1020
1021         if (data->flags & MMC_DATA_READ) {
1022                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1023                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1024         }
1025
1026         if (host->is2440) {
1027                 dcon |= S3C2440_SDIDCON_DS_WORD;
1028                 dcon |= S3C2440_SDIDCON_DATSTART;
1029         }
1030
1031         writel(dcon, host->base + S3C2410_SDIDCON);
1032
1033         /* write BSIZE register */
1034
1035         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1036
1037         /* add to IMASK register */
1038         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1039                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1040
1041         enable_imask(host, imsk);
1042
1043         /* write TIMER register */
1044
1045         if (host->is2440) {
1046                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1047         } else {
1048                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1049
1050                 /* FIX: set slow clock to prevent timeouts on read */
1051                 if (data->flags & MMC_DATA_READ)
1052                         writel(0xFF, host->base + S3C2410_SDIPRE);
1053         }
1054
1055         return 0;
1056 }
1057
1058 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1059
1060 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1061 {
1062         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1063
1064         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1065
1066         host->pio_sgptr = 0;
1067         host->pio_bytes = 0;
1068         host->pio_count = 0;
1069         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1070
1071         if (rw) {
1072                 do_pio_write(host);
1073                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1074         } else {
1075                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1076                              | S3C2410_SDIIMSK_RXFIFOLAST);
1077         }
1078
1079         return 0;
1080 }
1081
1082 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1083 {
1084         int dma_len, i;
1085         int rw = data->flags & MMC_DATA_WRITE;
1086
1087         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1088
1089         s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1090         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1091
1092         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1093                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1094
1095         if (dma_len == 0)
1096                 return -ENOMEM;
1097
1098         host->dma_complete = 0;
1099         host->dmatogo = dma_len;
1100
1101         for (i = 0; i < dma_len; i++) {
1102                 int res;
1103
1104                 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1105                     sg_dma_address(&data->sg[i]),
1106                     sg_dma_len(&data->sg[i]));
1107
1108                 res = s3c2410_dma_enqueue(host->dma, host,
1109                                           sg_dma_address(&data->sg[i]),
1110                                           sg_dma_len(&data->sg[i]));
1111
1112                 if (res) {
1113                         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1114                         return -EBUSY;
1115                 }
1116         }
1117
1118         s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1119
1120         return 0;
1121 }
1122
1123 static void s3cmci_send_request(struct mmc_host *mmc)
1124 {
1125         struct s3cmci_host *host = mmc_priv(mmc);
1126         struct mmc_request *mrq = host->mrq;
1127         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1128
1129         host->ccnt++;
1130         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1131
1132         /* Clear command, data and fifo status registers
1133            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1134         */
1135         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1136         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1137         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1138
1139         if (cmd->data) {
1140                 int res = s3cmci_setup_data(host, cmd->data);
1141
1142                 host->dcnt++;
1143
1144                 if (res) {
1145                         dbg(host, dbg_err, "setup data error %d\n", res);
1146                         cmd->error = res;
1147                         cmd->data->error = res;
1148
1149                         mmc_request_done(mmc, mrq);
1150                         return;
1151                 }
1152
1153                 if (s3cmci_host_usedma(host))
1154                         res = s3cmci_prepare_dma(host, cmd->data);
1155                 else
1156                         res = s3cmci_prepare_pio(host, cmd->data);
1157
1158                 if (res) {
1159                         dbg(host, dbg_err, "data prepare error %d\n", res);
1160                         cmd->error = res;
1161                         cmd->data->error = res;
1162
1163                         mmc_request_done(mmc, mrq);
1164                         return;
1165                 }
1166         }
1167
1168         /* Send command */
1169         s3cmci_send_command(host, cmd);
1170
1171         /* Enable Interrupt */
1172         s3cmci_enable_irq(host, true);
1173 }
1174
1175 static int s3cmci_card_present(struct mmc_host *mmc)
1176 {
1177         struct s3cmci_host *host = mmc_priv(mmc);
1178         struct s3c24xx_mci_pdata *pdata = host->pdata;
1179         int ret;
1180
1181         if (pdata->no_detect)
1182                 return -ENOSYS;
1183
1184         ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1185         return ret ^ pdata->detect_invert;
1186 }
1187
1188 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1189 {
1190         struct s3cmci_host *host = mmc_priv(mmc);
1191
1192         host->status = "mmc request";
1193         host->cmd_is_stop = 0;
1194         host->mrq = mrq;
1195
1196         if (s3cmci_card_present(mmc) == 0) {
1197                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1198                 host->mrq->cmd->error = -ENOMEDIUM;
1199                 mmc_request_done(mmc, mrq);
1200         } else
1201                 s3cmci_send_request(mmc);
1202 }
1203
1204 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1205 {
1206         u32 mci_psc;
1207
1208         /* Set clock */
1209         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1210                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1211
1212                 if (host->real_rate <= ios->clock)
1213                         break;
1214         }
1215
1216         if (mci_psc > 255)
1217                 mci_psc = 255;
1218
1219         host->prescaler = mci_psc;
1220         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1221
1222         /* If requested clock is 0, real_rate will be 0, too */
1223         if (ios->clock == 0)
1224                 host->real_rate = 0;
1225 }
1226
1227 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1228 {
1229         struct s3cmci_host *host = mmc_priv(mmc);
1230         u32 mci_con;
1231
1232         /* Set the power state */
1233
1234         mci_con = readl(host->base + S3C2410_SDICON);
1235
1236         switch (ios->power_mode) {
1237         case MMC_POWER_ON:
1238         case MMC_POWER_UP:
1239                 /* Configure GPE5...GPE10 pins in SD mode */
1240                 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1241                                       S3C_GPIO_PULL_NONE);
1242
1243                 if (host->pdata->set_power)
1244                         host->pdata->set_power(ios->power_mode, ios->vdd);
1245
1246                 if (!host->is2440)
1247                         mci_con |= S3C2410_SDICON_FIFORESET;
1248
1249                 break;
1250
1251         case MMC_POWER_OFF:
1252         default:
1253                 gpio_direction_output(S3C2410_GPE(5), 0);
1254
1255                 if (host->is2440)
1256                         mci_con |= S3C2440_SDICON_SDRESET;
1257
1258                 if (host->pdata->set_power)
1259                         host->pdata->set_power(ios->power_mode, ios->vdd);
1260
1261                 break;
1262         }
1263
1264         s3cmci_set_clk(host, ios);
1265
1266         /* Set CLOCK_ENABLE */
1267         if (ios->clock)
1268                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1269         else
1270                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1271
1272         writel(mci_con, host->base + S3C2410_SDICON);
1273
1274         if ((ios->power_mode == MMC_POWER_ON) ||
1275             (ios->power_mode == MMC_POWER_UP)) {
1276                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1277                         host->real_rate/1000, ios->clock/1000);
1278         } else {
1279                 dbg(host, dbg_conf, "powered down.\n");
1280         }
1281
1282         host->bus_width = ios->bus_width;
1283 }
1284
1285 static void s3cmci_reset(struct s3cmci_host *host)
1286 {
1287         u32 con = readl(host->base + S3C2410_SDICON);
1288
1289         con |= S3C2440_SDICON_SDRESET;
1290         writel(con, host->base + S3C2410_SDICON);
1291 }
1292
1293 static int s3cmci_get_ro(struct mmc_host *mmc)
1294 {
1295         struct s3cmci_host *host = mmc_priv(mmc);
1296         struct s3c24xx_mci_pdata *pdata = host->pdata;
1297         int ret;
1298
1299         if (pdata->no_wprotect)
1300                 return 0;
1301
1302         ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1303         ret ^= pdata->wprotect_invert;
1304
1305         return ret;
1306 }
1307
1308 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1309 {
1310         struct s3cmci_host *host = mmc_priv(mmc);
1311         unsigned long flags;
1312         u32 con;
1313
1314         local_irq_save(flags);
1315
1316         con = readl(host->base + S3C2410_SDICON);
1317         host->sdio_irqen = enable;
1318
1319         if (enable == host->sdio_irqen)
1320                 goto same_state;
1321
1322         if (enable) {
1323                 con |= S3C2410_SDICON_SDIOIRQ;
1324                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1325
1326                 if (!host->irq_state && !host->irq_disabled) {
1327                         host->irq_state = true;
1328                         enable_irq(host->irq);
1329                 }
1330         } else {
1331                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1332                 con &= ~S3C2410_SDICON_SDIOIRQ;
1333
1334                 if (!host->irq_enabled && host->irq_state) {
1335                         disable_irq_nosync(host->irq);
1336                         host->irq_state = false;
1337                 }
1338         }
1339
1340         writel(con, host->base + S3C2410_SDICON);
1341
1342  same_state:
1343         local_irq_restore(flags);
1344
1345         s3cmci_check_sdio_irq(host);
1346 }
1347
1348 static struct mmc_host_ops s3cmci_ops = {
1349         .request        = s3cmci_request,
1350         .set_ios        = s3cmci_set_ios,
1351         .get_ro         = s3cmci_get_ro,
1352         .get_cd         = s3cmci_card_present,
1353         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1354 };
1355
1356 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1357         /* This is currently here to avoid a number of if (host->pdata)
1358          * checks. Any zero fields to ensure reasonable defaults are picked. */
1359          .no_wprotect = 1,
1360          .no_detect = 1,
1361 };
1362
1363 #ifdef CONFIG_CPU_FREQ
1364
1365 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1366                                      unsigned long val, void *data)
1367 {
1368         struct s3cmci_host *host;
1369         struct mmc_host *mmc;
1370         unsigned long newclk;
1371         unsigned long flags;
1372
1373         host = container_of(nb, struct s3cmci_host, freq_transition);
1374         newclk = clk_get_rate(host->clk);
1375         mmc = host->mmc;
1376
1377         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1378             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1379                 spin_lock_irqsave(&mmc->lock, flags);
1380
1381                 host->clk_rate = newclk;
1382
1383                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1384                     mmc->ios.clock != 0)
1385                         s3cmci_set_clk(host, &mmc->ios);
1386
1387                 spin_unlock_irqrestore(&mmc->lock, flags);
1388         }
1389
1390         return 0;
1391 }
1392
1393 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1394 {
1395         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1396
1397         return cpufreq_register_notifier(&host->freq_transition,
1398                                          CPUFREQ_TRANSITION_NOTIFIER);
1399 }
1400
1401 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1402 {
1403         cpufreq_unregister_notifier(&host->freq_transition,
1404                                     CPUFREQ_TRANSITION_NOTIFIER);
1405 }
1406
1407 #else
1408 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1409 {
1410         return 0;
1411 }
1412
1413 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1414 {
1415 }
1416 #endif
1417
1418
1419 #ifdef CONFIG_DEBUG_FS
1420
1421 static int s3cmci_state_show(struct seq_file *seq, void *v)
1422 {
1423         struct s3cmci_host *host = seq->private;
1424
1425         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1426         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1427         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1428         seq_printf(seq, "is2440 = %d\n", host->is2440);
1429         seq_printf(seq, "IRQ = %d\n", host->irq);
1430         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1431         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1432         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1433         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1434         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1435         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1436         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1437
1438         return 0;
1439 }
1440
1441 static int s3cmci_state_open(struct inode *inode, struct file *file)
1442 {
1443         return single_open(file, s3cmci_state_show, inode->i_private);
1444 }
1445
1446 static const struct file_operations s3cmci_fops_state = {
1447         .owner          = THIS_MODULE,
1448         .open           = s3cmci_state_open,
1449         .read           = seq_read,
1450         .llseek         = seq_lseek,
1451         .release        = single_release,
1452 };
1453
1454 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1455
1456 struct s3cmci_reg {
1457         unsigned short  addr;
1458         unsigned char   *name;
1459 } debug_regs[] = {
1460         DBG_REG(CON),
1461         DBG_REG(PRE),
1462         DBG_REG(CMDARG),
1463         DBG_REG(CMDCON),
1464         DBG_REG(CMDSTAT),
1465         DBG_REG(RSP0),
1466         DBG_REG(RSP1),
1467         DBG_REG(RSP2),
1468         DBG_REG(RSP3),
1469         DBG_REG(TIMER),
1470         DBG_REG(BSIZE),
1471         DBG_REG(DCON),
1472         DBG_REG(DCNT),
1473         DBG_REG(DSTA),
1474         DBG_REG(FSTA),
1475         {}
1476 };
1477
1478 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1479 {
1480         struct s3cmci_host *host = seq->private;
1481         struct s3cmci_reg *rptr = debug_regs;
1482
1483         for (; rptr->name; rptr++)
1484                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1485                            readl(host->base + rptr->addr));
1486
1487         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1488
1489         return 0;
1490 }
1491
1492 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1493 {
1494         return single_open(file, s3cmci_regs_show, inode->i_private);
1495 }
1496
1497 static const struct file_operations s3cmci_fops_regs = {
1498         .owner          = THIS_MODULE,
1499         .open           = s3cmci_regs_open,
1500         .read           = seq_read,
1501         .llseek         = seq_lseek,
1502         .release        = single_release,
1503 };
1504
1505 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1506 {
1507         struct device *dev = &host->pdev->dev;
1508
1509         host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1510         if (IS_ERR(host->debug_root)) {
1511                 dev_err(dev, "failed to create debugfs root\n");
1512                 return;
1513         }
1514
1515         host->debug_state = debugfs_create_file("state", 0444,
1516                                                 host->debug_root, host,
1517                                                 &s3cmci_fops_state);
1518
1519         if (IS_ERR(host->debug_state))
1520                 dev_err(dev, "failed to create debug state file\n");
1521
1522         host->debug_regs = debugfs_create_file("regs", 0444,
1523                                                host->debug_root, host,
1524                                                &s3cmci_fops_regs);
1525
1526         if (IS_ERR(host->debug_regs))
1527                 dev_err(dev, "failed to create debug regs file\n");
1528 }
1529
1530 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1531 {
1532         debugfs_remove(host->debug_regs);
1533         debugfs_remove(host->debug_state);
1534         debugfs_remove(host->debug_root);
1535 }
1536
1537 #else
1538 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1539 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1540
1541 #endif /* CONFIG_DEBUG_FS */
1542
1543 static int s3cmci_probe(struct platform_device *pdev)
1544 {
1545         struct s3cmci_host *host;
1546         struct mmc_host *mmc;
1547         int ret;
1548         int is2440;
1549         int i;
1550
1551         is2440 = platform_get_device_id(pdev)->driver_data;
1552
1553         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1554         if (!mmc) {
1555                 ret = -ENOMEM;
1556                 goto probe_out;
1557         }
1558
1559         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1560                 ret = gpio_request(i, dev_name(&pdev->dev));
1561                 if (ret) {
1562                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1563
1564                         for (i--; i >= S3C2410_GPE(5); i--)
1565                                 gpio_free(i);
1566
1567                         goto probe_free_host;
1568                 }
1569         }
1570
1571         host = mmc_priv(mmc);
1572         host->mmc       = mmc;
1573         host->pdev      = pdev;
1574         host->is2440    = is2440;
1575
1576         host->pdata = pdev->dev.platform_data;
1577         if (!host->pdata) {
1578                 pdev->dev.platform_data = &s3cmci_def_pdata;
1579                 host->pdata = &s3cmci_def_pdata;
1580         }
1581
1582         spin_lock_init(&host->complete_lock);
1583         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1584
1585         if (is2440) {
1586                 host->sdiimsk   = S3C2440_SDIIMSK;
1587                 host->sdidata   = S3C2440_SDIDATA;
1588                 host->clk_div   = 1;
1589         } else {
1590                 host->sdiimsk   = S3C2410_SDIIMSK;
1591                 host->sdidata   = S3C2410_SDIDATA;
1592                 host->clk_div   = 2;
1593         }
1594
1595         host->complete_what     = COMPLETION_NONE;
1596         host->pio_active        = XFER_NONE;
1597
1598 #ifdef CONFIG_MMC_S3C_PIODMA
1599         host->dodma             = host->pdata->use_dma;
1600 #endif
1601
1602         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1603         if (!host->mem) {
1604                 dev_err(&pdev->dev,
1605                         "failed to get io memory region resource.\n");
1606
1607                 ret = -ENOENT;
1608                 goto probe_free_gpio;
1609         }
1610
1611         host->mem = request_mem_region(host->mem->start,
1612                                        resource_size(host->mem), pdev->name);
1613
1614         if (!host->mem) {
1615                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1616                 ret = -ENOENT;
1617                 goto probe_free_gpio;
1618         }
1619
1620         host->base = ioremap(host->mem->start, resource_size(host->mem));
1621         if (!host->base) {
1622                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1623                 ret = -EINVAL;
1624                 goto probe_free_mem_region;
1625         }
1626
1627         host->irq = platform_get_irq(pdev, 0);
1628         if (host->irq == 0) {
1629                 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1630                 ret = -EINVAL;
1631                 goto probe_iounmap;
1632         }
1633
1634         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1635                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1636                 ret = -ENOENT;
1637                 goto probe_iounmap;
1638         }
1639
1640         /* We get spurious interrupts even when we have set the IMSK
1641          * register to ignore everything, so use disable_irq() to make
1642          * ensure we don't lock the system with un-serviceable requests. */
1643
1644         disable_irq(host->irq);
1645         host->irq_state = false;
1646
1647         if (!host->pdata->no_detect) {
1648                 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1649                 if (ret) {
1650                         dev_err(&pdev->dev, "failed to get detect gpio\n");
1651                         goto probe_free_irq;
1652                 }
1653
1654                 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1655
1656                 if (host->irq_cd >= 0) {
1657                         if (request_irq(host->irq_cd, s3cmci_irq_cd,
1658                                         IRQF_TRIGGER_RISING |
1659                                         IRQF_TRIGGER_FALLING,
1660                                         DRIVER_NAME, host)) {
1661                                 dev_err(&pdev->dev,
1662                                         "can't get card detect irq.\n");
1663                                 ret = -ENOENT;
1664                                 goto probe_free_gpio_cd;
1665                         }
1666                 } else {
1667                         dev_warn(&pdev->dev,
1668                                  "host detect has no irq available\n");
1669                         gpio_direction_input(host->pdata->gpio_detect);
1670                 }
1671         } else
1672                 host->irq_cd = -1;
1673
1674         if (!host->pdata->no_wprotect) {
1675                 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1676                 if (ret) {
1677                         dev_err(&pdev->dev, "failed to get writeprotect\n");
1678                         goto probe_free_irq_cd;
1679                 }
1680
1681                 gpio_direction_input(host->pdata->gpio_wprotect);
1682         }
1683
1684         /* depending on the dma state, get a dma channel to use. */
1685
1686         if (s3cmci_host_usedma(host)) {
1687                 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1688                                                 host);
1689                 if (host->dma < 0) {
1690                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1691                         if (!s3cmci_host_canpio()) {
1692                                 ret = -EBUSY;
1693                                 goto probe_free_gpio_wp;
1694                         } else {
1695                                 dev_warn(&pdev->dev, "falling back to PIO.\n");
1696                                 host->dodma = 0;
1697                         }
1698                 }
1699         }
1700
1701         host->clk = clk_get(&pdev->dev, "sdi");
1702         if (IS_ERR(host->clk)) {
1703                 dev_err(&pdev->dev, "failed to find clock source.\n");
1704                 ret = PTR_ERR(host->clk);
1705                 host->clk = NULL;
1706                 goto probe_free_dma;
1707         }
1708
1709         ret = clk_enable(host->clk);
1710         if (ret) {
1711                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1712                 goto clk_free;
1713         }
1714
1715         host->clk_rate = clk_get_rate(host->clk);
1716
1717         mmc->ops        = &s3cmci_ops;
1718         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1719 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1720         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1721 #else
1722         mmc->caps       = MMC_CAP_4_BIT_DATA;
1723 #endif
1724         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1725         mmc->f_max      = host->clk_rate / host->clk_div;
1726
1727         if (host->pdata->ocr_avail)
1728                 mmc->ocr_avail = host->pdata->ocr_avail;
1729
1730         mmc->max_blk_count      = 4095;
1731         mmc->max_blk_size       = 4095;
1732         mmc->max_req_size       = 4095 * 512;
1733         mmc->max_seg_size       = mmc->max_req_size;
1734
1735         mmc->max_segs           = 128;
1736
1737         dbg(host, dbg_debug,
1738             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1739             (host->is2440?"2440":""),
1740             host->base, host->irq, host->irq_cd, host->dma);
1741
1742         ret = s3cmci_cpufreq_register(host);
1743         if (ret) {
1744                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1745                 goto free_dmabuf;
1746         }
1747
1748         ret = mmc_add_host(mmc);
1749         if (ret) {
1750                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1751                 goto free_cpufreq;
1752         }
1753
1754         s3cmci_debugfs_attach(host);
1755
1756         platform_set_drvdata(pdev, mmc);
1757         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1758                  s3cmci_host_usedma(host) ? "dma" : "pio",
1759                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1760
1761         return 0;
1762
1763  free_cpufreq:
1764         s3cmci_cpufreq_deregister(host);
1765
1766  free_dmabuf:
1767         clk_disable(host->clk);
1768
1769  clk_free:
1770         clk_put(host->clk);
1771
1772  probe_free_dma:
1773         if (s3cmci_host_usedma(host))
1774                 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1775
1776  probe_free_gpio_wp:
1777         if (!host->pdata->no_wprotect)
1778                 gpio_free(host->pdata->gpio_wprotect);
1779
1780  probe_free_gpio_cd:
1781         if (!host->pdata->no_detect)
1782                 gpio_free(host->pdata->gpio_detect);
1783
1784  probe_free_irq_cd:
1785         if (host->irq_cd >= 0)
1786                 free_irq(host->irq_cd, host);
1787
1788  probe_free_irq:
1789         free_irq(host->irq, host);
1790
1791  probe_iounmap:
1792         iounmap(host->base);
1793
1794  probe_free_mem_region:
1795         release_mem_region(host->mem->start, resource_size(host->mem));
1796
1797  probe_free_gpio:
1798         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1799                 gpio_free(i);
1800
1801  probe_free_host:
1802         mmc_free_host(mmc);
1803
1804  probe_out:
1805         return ret;
1806 }
1807
1808 static void s3cmci_shutdown(struct platform_device *pdev)
1809 {
1810         struct mmc_host *mmc = platform_get_drvdata(pdev);
1811         struct s3cmci_host *host = mmc_priv(mmc);
1812
1813         if (host->irq_cd >= 0)
1814                 free_irq(host->irq_cd, host);
1815
1816         s3cmci_debugfs_remove(host);
1817         s3cmci_cpufreq_deregister(host);
1818         mmc_remove_host(mmc);
1819         clk_disable(host->clk);
1820 }
1821
1822 static int s3cmci_remove(struct platform_device *pdev)
1823 {
1824         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1825         struct s3cmci_host      *host = mmc_priv(mmc);
1826         struct s3c24xx_mci_pdata *pd = host->pdata;
1827         int i;
1828
1829         s3cmci_shutdown(pdev);
1830
1831         clk_put(host->clk);
1832
1833         tasklet_disable(&host->pio_tasklet);
1834
1835         if (s3cmci_host_usedma(host))
1836                 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1837
1838         free_irq(host->irq, host);
1839
1840         if (!pd->no_wprotect)
1841                 gpio_free(pd->gpio_wprotect);
1842
1843         if (!pd->no_detect)
1844                 gpio_free(pd->gpio_detect);
1845
1846         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1847                 gpio_free(i);
1848
1849
1850         iounmap(host->base);
1851         release_mem_region(host->mem->start, resource_size(host->mem));
1852
1853         mmc_free_host(mmc);
1854         return 0;
1855 }
1856
1857 static struct platform_device_id s3cmci_driver_ids[] = {
1858         {
1859                 .name   = "s3c2410-sdi",
1860                 .driver_data    = 0,
1861         }, {
1862                 .name   = "s3c2412-sdi",
1863                 .driver_data    = 1,
1864         }, {
1865                 .name   = "s3c2440-sdi",
1866                 .driver_data    = 1,
1867         },
1868         { }
1869 };
1870
1871 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1872
1873
1874 #ifdef CONFIG_PM
1875
1876 static int s3cmci_suspend(struct device *dev)
1877 {
1878         struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1879
1880         return mmc_suspend_host(mmc);
1881 }
1882
1883 static int s3cmci_resume(struct device *dev)
1884 {
1885         struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1886
1887         return mmc_resume_host(mmc);
1888 }
1889
1890 static const struct dev_pm_ops s3cmci_pm = {
1891         .suspend        = s3cmci_suspend,
1892         .resume         = s3cmci_resume,
1893 };
1894
1895 #define s3cmci_pm_ops &s3cmci_pm
1896 #else /* CONFIG_PM */
1897 #define s3cmci_pm_ops NULL
1898 #endif /* CONFIG_PM */
1899
1900
1901 static struct platform_driver s3cmci_driver = {
1902         .driver = {
1903                 .name   = "s3c-sdi",
1904                 .owner  = THIS_MODULE,
1905                 .pm     = s3cmci_pm_ops,
1906         },
1907         .id_table       = s3cmci_driver_ids,
1908         .probe          = s3cmci_probe,
1909         .remove         = s3cmci_remove,
1910         .shutdown       = s3cmci_shutdown,
1911 };
1912
1913 module_platform_driver(s3cmci_driver);
1914
1915 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1916 MODULE_LICENSE("GPL v2");
1917 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");