drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include "sdhci-pltfm.h"
  31 #include "sdhci-esdhc.h"
  32
  33 #define ESDHC_CTRL_D3CD                 0x08
  34 /* VENDOR SPEC register */
  35 #define ESDHC_VENDOR_SPEC               0xc0
  36 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  37 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  39 #define ESDHC_WTMK_LVL                  0x44
  40 #define ESDHC_MIX_CTRL                  0x48
  41 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  42 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  43 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  44 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  45 /* Bits 3 and 6 are not SDHCI standard definitions */
  46 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  47
  48 /* tune control register */
  49 #define ESDHC_TUNE_CTRL_STATUS          0x68
  50 #define  ESDHC_TUNE_CTRL_STEP           1
  51 #define  ESDHC_TUNE_CTRL_MIN            0
  52 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  53
  54 #define ESDHC_TUNING_BLOCK_PATTERN_LEN  64
  55
  56 /* pinctrl state */
  57 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  58 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  59
  60 /*
  61  * Our interpretation of the SDHCI_HOST_CONTROL register
  62  */
  63 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  64 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  65 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  66
  67 /*
  68  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  69  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  70  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  71  * Define this macro DMA error INT for fsl eSDHC
  72  */
  73 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  74
  75 /*
  76  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  77  * "11" when the STOP CMD12 is issued on imx53 to abort one
  78  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  79  * be generated.
  80  * In exact block transfer, the controller doesn't complete the
  81  * operations automatically as required at the end of the
  82  * transfer and remains on hold if the abort command is not sent.
  83  * As a result, the TC flag is not asserted and SW  received timeout
  84  * exeception. Bit1 of Vendor Spec registor is used to fix it.
  85  */
  86 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
  87 /*
  88  * The flag enables the workaround for ESDHC errata ENGcm07207 which
  89  * affects i.MX25 and i.MX35.
  90  */
  91 #define ESDHC_FLAG_ENGCM07207           BIT(2)
  92 /*
  93  * The flag tells that the ESDHC controller is an USDHC block that is
  94  * integrated on the i.MX6 series.
  95  */
  96 #define ESDHC_FLAG_USDHC                BIT(3)
  97
  98 enum imx_esdhc_type {
  99         IMX25_ESDHC,
 100         IMX35_ESDHC,
 101         IMX51_ESDHC,
 102         IMX53_ESDHC,
 103         IMX6Q_USDHC,
 104 };
 105
 106 struct pltfm_imx_data {
 107         int flags;
 108         u32 scratchpad;
 109         enum imx_esdhc_type devtype;
 110         struct pinctrl *pinctrl;
 111         struct pinctrl_state *pins_default;
 112         struct pinctrl_state *pins_100mhz;
 113         struct pinctrl_state *pins_200mhz;
 114         struct esdhc_platform_data boarddata;
 115         struct clk *clk_ipg;
 116         struct clk *clk_ahb;
 117         struct clk *clk_per;
 118         enum {
 119                 NO_CMD_PENDING,      /* no multiblock command pending*/
 120                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 121                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 122         } multiblock_status;
 123         u32 uhs_mode;
 124 };
 125
 126 static struct platform_device_id imx_esdhc_devtype[] = {
 127         {
 128                 .name = "sdhci-esdhc-imx25",
 129                 .driver_data = IMX25_ESDHC,
 130         }, {
 131                 .name = "sdhci-esdhc-imx35",
 132                 .driver_data = IMX35_ESDHC,
 133         }, {
 134                 .name = "sdhci-esdhc-imx51",
 135                 .driver_data = IMX51_ESDHC,
 136         }, {
 137                 .name = "sdhci-esdhc-imx53",
 138                 .driver_data = IMX53_ESDHC,
 139         }, {
 140                 .name = "sdhci-usdhc-imx6q",
 141                 .driver_data = IMX6Q_USDHC,
 142         }, {
 143                 /* sentinel */
 144         }
 145 };
 146 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 147
 148 static const struct of_device_id imx_esdhc_dt_ids[] = {
 149         { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
 150         { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
 151         { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
 152         { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
 153         { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
 154         { /* sentinel */ }
 155 };
 156 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 157
 158 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 159 {
 160         return data->devtype == IMX25_ESDHC;
 161 }
 162
 163 static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
 164 {
 165         return data->devtype == IMX35_ESDHC;
 166 }
 167
 168 static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
 169 {
 170         return data->devtype == IMX51_ESDHC;
 171 }
 172
 173 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 174 {
 175         return data->devtype == IMX53_ESDHC;
 176 }
 177
 178 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 179 {
 180         return data->devtype == IMX6Q_USDHC;
 181 }
 182
 183 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 184 {
 185         return !!(data->flags & ESDHC_FLAG_USDHC);
 186 }
 187
 188 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 189 {
 190         void __iomem *base = host->ioaddr + (reg & ~0x3);
 191         u32 shift = (reg & 0x3) * 8;
 192
 193         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 194 }
 195
 196 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 197 {
 198         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 199         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 200         u32 val = readl(host->ioaddr + reg);
 201
 202         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 203                 u32 fsl_prss = val;
 204                 /* save the least 20 bits */
 205                 val = fsl_prss & 0x000FFFFF;
 206                 /* move dat[0-3] bits */
 207                 val |= (fsl_prss & 0x0F000000) >> 4;
 208                 /* move cmd line bit */
 209                 val |= (fsl_prss & 0x00800000) << 1;
 210         }
 211
 212         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 213                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 214                  * ADMA2 capability of esdhc, but this bit is messed up on
 215                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 216                  * don't actually support ADMA2). So set the BROKEN_ADMA
 217                  * uirk on MX25/35 platforms.
 218                  */
 219
 220                 if (val & SDHCI_CAN_DO_ADMA1) {
 221                         val &= ~SDHCI_CAN_DO_ADMA1;
 222                         val |= SDHCI_CAN_DO_ADMA2;
 223                 }
 224         }
 225
 226         if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data))
 227                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 228                                 | SDHCI_SUPPORT_SDR50;
 229
 230         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 231                 val = 0;
 232                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 233                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 234                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 235         }
 236
 237         if (unlikely(reg == SDHCI_INT_STATUS)) {
 238                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 239                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 240                         val |= SDHCI_INT_ADMA_ERROR;
 241                 }
 242
 243                 /*
 244                  * mask off the interrupt we get in response to the manually
 245                  * sent CMD12
 246                  */
 247                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 248                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 249                         val &= ~SDHCI_INT_RESPONSE;
 250                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 251                                                    SDHCI_INT_STATUS);
 252                         imx_data->multiblock_status = NO_CMD_PENDING;
 253                 }
 254         }
 255
 256         return val;
 257 }
 258
 259 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 260 {
 261         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 262         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 263         u32 data;
 264
 265         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 266                 if (val & SDHCI_INT_CARD_INT) {
 267                         /*
 268                          * Clear and then set D3CD bit to avoid missing the
 269                          * card interrupt.  This is a eSDHC controller problem
 270                          * so we need to apply the following workaround: clear
 271                          * and set D3CD bit will make eSDHC re-sample the card
 272                          * interrupt. In case a card interrupt was lost,
 273                          * re-sample it by the following steps.
 274                          */
 275                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 276                         data &= ~ESDHC_CTRL_D3CD;
 277                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 278                         data |= ESDHC_CTRL_D3CD;
 279                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 280                 }
 281         }
 282
 283         if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 284                                 && (reg == SDHCI_INT_STATUS)
 285                                 && (val & SDHCI_INT_DATA_END))) {
 286                         u32 v;
 287                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 288                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 289                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 290
 291                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 292                         {
 293                                 /* send a manual CMD12 with RESPTYP=none */
 294                                 data = MMC_STOP_TRANSMISSION << 24 |
 295                                        SDHCI_CMD_ABORTCMD << 16;
 296                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 297                                 imx_data->multiblock_status = WAIT_FOR_INT;
 298                         }
 299         }
 300
 301         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 302                 if (val & SDHCI_INT_ADMA_ERROR) {
 303                         val &= ~SDHCI_INT_ADMA_ERROR;
 304                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 305                 }
 306         }
 307
 308         writel(val, host->ioaddr + reg);
 309 }
 310
 311 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 312 {
 313         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 314         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 315         u16 ret = 0;
 316         u32 val;
 317
 318         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 319                 reg ^= 2;
 320                 if (esdhc_is_usdhc(imx_data)) {
 321                         /*
 322                          * The usdhc register returns a wrong host version.
 323                          * Correct it here.
 324                          */
 325                         return SDHCI_SPEC_300;
 326                 }
 327         }
 328
 329         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 330                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 331                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 332                         ret |= SDHCI_CTRL_VDD_180;
 333
 334                 if (esdhc_is_usdhc(imx_data)) {
 335                         val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 336                         if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 337                                 ret |= SDHCI_CTRL_EXEC_TUNING;
 338                         if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 339                                 ret |= SDHCI_CTRL_TUNED_CLK;
 340                 }
 341
 342                 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
 343                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 344
 345                 return ret;
 346         }
 347
 348         return readw(host->ioaddr + reg);
 349 }
 350
 351 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 352 {
 353         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 354         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 355         u32 new_val = 0;
 356
 357         switch (reg) {
 358         case SDHCI_CLOCK_CONTROL:
 359                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 360                 if (val & SDHCI_CLOCK_CARD_EN)
 361                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 362                 else
 363                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 364                         writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 365                 return;
 366         case SDHCI_HOST_CONTROL2:
 367                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 368                 if (val & SDHCI_CTRL_VDD_180)
 369                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 370                 else
 371                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 372                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 373                 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
 374                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 375                 if (val & SDHCI_CTRL_TUNED_CLK)
 376                         new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 377                 else
 378                         new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 379                 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 380                 return;
 381         case SDHCI_TRANSFER_MODE:
 382                 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 383                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 384                                 && (host->cmd->data->blocks > 1)
 385                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 386                         u32 v;
 387                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 388                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 389                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 390                 }
 391
 392                 if (esdhc_is_usdhc(imx_data)) {
 393                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 394                         /* Swap AC23 bit */
 395                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 396                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 397                                 val |= ESDHC_MIX_CTRL_AC23EN;
 398                         }
 399                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 400                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 401                 } else {
 402                         /*
 403                          * Postpone this write, we must do it together with a
 404                          * command write that is down below.
 405                          */
 406                         imx_data->scratchpad = val;
 407                 }
 408                 return;
 409         case SDHCI_COMMAND:
 410                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 411                         val |= SDHCI_CMD_ABORTCMD;
 412
 413                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 414                     (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 415                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 416
 417                 if (esdhc_is_usdhc(imx_data))
 418                         writel(val << 16,
 419                                host->ioaddr + SDHCI_TRANSFER_MODE);
 420                 else
 421                         writel(val << 16 | imx_data->scratchpad,
 422                                host->ioaddr + SDHCI_TRANSFER_MODE);
 423                 return;
 424         case SDHCI_BLOCK_SIZE:
 425                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 426                 break;
 427         }
 428         esdhc_clrset_le(host, 0xffff, val, reg);
 429 }
 430
 431 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 432 {
 433         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 434         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 435         u32 new_val;
 436         u32 mask;
 437
 438         switch (reg) {
 439         case SDHCI_POWER_CONTROL:
 440                 /*
 441                  * FSL put some DMA bits here
 442                  * If your board has a regulator, code should be here
 443                  */
 444                 return;
 445         case SDHCI_HOST_CONTROL:
 446                 /* FSL messed up here, so we need to manually compose it. */
 447                 new_val = val & SDHCI_CTRL_LED;
 448                 /* ensure the endianness */
 449                 new_val |= ESDHC_HOST_CONTROL_LE;
 450                 /* bits 8&9 are reserved on mx25 */
 451                 if (!is_imx25_esdhc(imx_data)) {
 452                         /* DMA mode bits are shifted */
 453                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 454                 }
 455
 456                 /*
 457                  * Do not touch buswidth bits here. This is done in
 458                  * esdhc_pltfm_bus_width.
 459                  * Do not touch the D3CD bit either which is used for the
 460                  * SDIO interrupt errata workaround.
 461                  */
 462                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 463
 464                 esdhc_clrset_le(host, mask, new_val, reg);
 465                 return;
 466         }
 467         esdhc_clrset_le(host, 0xff, val, reg);
 468
 469         /*
 470          * The esdhc has a design violation to SDHC spec which tells
 471          * that software reset should not affect card detection circuit.
 472          * But esdhc clears its SYSCTL register bits [0..2] during the
 473          * software reset.  This will stop those clocks that card detection
 474          * circuit relies on.  To work around it, we turn the clocks on back
 475          * to keep card detection circuit functional.
 476          */
 477         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 478                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 479                 /*
 480                  * The reset on usdhc fails to clear MIX_CTRL register.
 481                  * Do it manually here.
 482                  */
 483                 if (esdhc_is_usdhc(imx_data))
 484                         writel(0, host->ioaddr + ESDHC_MIX_CTRL);
 485         }
 486 }
 487
 488 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 489 {
 490         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 491         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 492         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 493
 494         u32 f_host = clk_get_rate(pltfm_host->clk);
 495
 496         if (boarddata->f_max && (boarddata->f_max < f_host))
 497                 return boarddata->f_max;
 498         else
 499                 return f_host;
 500 }
 501
 502 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 503 {
 504         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 505
 506         return clk_get_rate(pltfm_host->clk) / 256 / 16;
 507 }
 508
 509 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 510                                          unsigned int clock)
 511 {
 512         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 513         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 514         unsigned int host_clock = clk_get_rate(pltfm_host->clk);
 515         int pre_div = 2;
 516         int div = 1;
 517         u32 temp, val;
 518
 519         if (clock == 0) {
 520                 if (esdhc_is_usdhc(imx_data)) {
 521                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 522                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 523                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 524                 }
 525                 goto out;
 526         }
 527
 528         if (esdhc_is_usdhc(imx_data))
 529                 pre_div = 1;
 530
 531         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 532         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 533                 | ESDHC_CLOCK_MASK);
 534         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 535
 536         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 537                 pre_div *= 2;
 538
 539         while (host_clock / pre_div / div > clock && div < 16)
 540                 div++;
 541
 542         host->mmc->actual_clock = host_clock / pre_div / div;
 543         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 544                 clock, host->mmc->actual_clock);
 545
 546         pre_div >>= 1;
 547         div--;
 548
 549         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 550         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 551                 | (div << ESDHC_DIVIDER_SHIFT)
 552                 | (pre_div << ESDHC_PREDIV_SHIFT));
 553         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 554
 555         if (esdhc_is_usdhc(imx_data)) {
 556                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 557                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 558                 host->ioaddr + ESDHC_VENDOR_SPEC);
 559         }
 560
 561         mdelay(1);
 562 out:
 563         host->clock = clock;
 564 }
 565
 566 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 567 {
 568         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 569         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 570         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 571
 572         switch (boarddata->wp_type) {
 573         case ESDHC_WP_GPIO:
 574                 return mmc_gpio_get_ro(host->mmc);
 575         case ESDHC_WP_CONTROLLER:
 576                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 577                                SDHCI_WRITE_PROTECT);
 578         case ESDHC_WP_NONE:
 579                 break;
 580         }
 581
 582         return -ENOSYS;
 583 }
 584
 585 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
 586 {
 587         u32 ctrl;
 588
 589         switch (width) {
 590         case MMC_BUS_WIDTH_8:
 591                 ctrl = ESDHC_CTRL_8BITBUS;
 592                 break;
 593         case MMC_BUS_WIDTH_4:
 594                 ctrl = ESDHC_CTRL_4BITBUS;
 595                 break;
 596         default:
 597                 ctrl = 0;
 598                 break;
 599         }
 600
 601         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 602                         SDHCI_HOST_CONTROL);
 603
 604         return 0;
 605 }
 606
 607 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 608 {
 609         u32 reg;
 610
 611         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 612         mdelay(1);
 613
 614         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 615         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 616                         ESDHC_MIX_CTRL_FBCLK_SEL;
 617         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 618         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 619         dev_dbg(mmc_dev(host->mmc),
 620                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 621                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 622 }
 623
 624 static void esdhc_request_done(struct mmc_request *mrq)
 625 {
 626         complete(&mrq->completion);
 627 }
 628
 629 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
 630 {
 631         struct mmc_command cmd = {0};
 632         struct mmc_request mrq = {0};
 633         struct mmc_data data = {0};
 634         struct scatterlist sg;
 635         char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
 636
 637         cmd.opcode = opcode;
 638         cmd.arg = 0;
 639         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 640
 641         data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
 642         data.blocks = 1;
 643         data.flags = MMC_DATA_READ;
 644         data.sg = &sg;
 645         data.sg_len = 1;
 646
 647         sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
 648
 649         mrq.cmd = &cmd;
 650         mrq.cmd->mrq = &mrq;
 651         mrq.data = &data;
 652         mrq.data->mrq = &mrq;
 653         mrq.cmd->data = mrq.data;
 654
 655         mrq.done = esdhc_request_done;
 656         init_completion(&(mrq.completion));
 657
 658         disable_irq(host->irq);
 659         spin_lock(&host->lock);
 660         host->mrq = &mrq;
 661
 662         sdhci_send_command(host, mrq.cmd);
 663
 664         spin_unlock(&host->lock);
 665         enable_irq(host->irq);
 666
 667         wait_for_completion(&mrq.completion);
 668
 669         if (cmd.error)
 670                 return cmd.error;
 671         if (data.error)
 672                 return data.error;
 673
 674         return 0;
 675 }
 676
 677 static void esdhc_post_tuning(struct sdhci_host *host)
 678 {
 679         u32 reg;
 680
 681         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 682         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 683         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 684 }
 685
 686 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 687 {
 688         int min, max, avg, ret;
 689
 690         /* find the mininum delay first which can pass tuning */
 691         min = ESDHC_TUNE_CTRL_MIN;
 692         while (min < ESDHC_TUNE_CTRL_MAX) {
 693                 esdhc_prepare_tuning(host, min);
 694                 if (!esdhc_send_tuning_cmd(host, opcode))
 695                         break;
 696                 min += ESDHC_TUNE_CTRL_STEP;
 697         }
 698
 699         /* find the maxinum delay which can not pass tuning */
 700         max = min + ESDHC_TUNE_CTRL_STEP;
 701         while (max < ESDHC_TUNE_CTRL_MAX) {
 702                 esdhc_prepare_tuning(host, max);
 703                 if (esdhc_send_tuning_cmd(host, opcode)) {
 704                         max -= ESDHC_TUNE_CTRL_STEP;
 705                         break;
 706                 }
 707                 max += ESDHC_TUNE_CTRL_STEP;
 708         }
 709
 710         /* use average delay to get the best timing */
 711         avg = (min + max) / 2;
 712         esdhc_prepare_tuning(host, avg);
 713         ret = esdhc_send_tuning_cmd(host, opcode);
 714         esdhc_post_tuning(host);
 715
 716         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 717                 ret ? "failed" : "passed", avg, ret);
 718
 719         return ret;
 720 }
 721
 722 static int esdhc_change_pinstate(struct sdhci_host *host,
 723                                                 unsigned int uhs)
 724 {
 725         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 726         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 727         struct pinctrl_state *pinctrl;
 728
 729         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 730
 731         if (IS_ERR(imx_data->pinctrl) ||
 732                 IS_ERR(imx_data->pins_default) ||
 733                 IS_ERR(imx_data->pins_100mhz) ||
 734                 IS_ERR(imx_data->pins_200mhz))
 735                 return -EINVAL;
 736
 737         switch (uhs) {
 738         case MMC_TIMING_UHS_SDR50:
 739                 pinctrl = imx_data->pins_100mhz;
 740                 break;
 741         case MMC_TIMING_UHS_SDR104:
 742                 pinctrl = imx_data->pins_200mhz;
 743                 break;
 744         default:
 745                 /* back to default state for other legacy timing */
 746                 pinctrl = imx_data->pins_default;
 747         }
 748
 749         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 750 }
 751
 752 static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 753 {
 754         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 755         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 756
 757         switch (uhs) {
 758         case MMC_TIMING_UHS_SDR12:
 759                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
 760                 break;
 761         case MMC_TIMING_UHS_SDR25:
 762                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
 763                 break;
 764         case MMC_TIMING_UHS_SDR50:
 765                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
 766                 break;
 767         case MMC_TIMING_UHS_SDR104:
 768                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
 769                 break;
 770         case MMC_TIMING_UHS_DDR50:
 771                 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
 772                 break;
 773         }
 774
 775         return esdhc_change_pinstate(host, uhs);
 776 }
 777
 778 static const struct sdhci_ops sdhci_esdhc_ops = {
 779         .read_l = esdhc_readl_le,
 780         .read_w = esdhc_readw_le,
 781         .write_l = esdhc_writel_le,
 782         .write_w = esdhc_writew_le,
 783         .write_b = esdhc_writeb_le,
 784         .set_clock = esdhc_pltfm_set_clock,
 785         .get_max_clock = esdhc_pltfm_get_max_clock,
 786         .get_min_clock = esdhc_pltfm_get_min_clock,
 787         .get_ro = esdhc_pltfm_get_ro,
 788         .platform_bus_width = esdhc_pltfm_bus_width,
 789         .set_uhs_signaling = esdhc_set_uhs_signaling,
 790         .platform_execute_tuning = esdhc_executing_tuning,
 791 };
 792
 793 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 794         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 795                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 796                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 797                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 798         .ops = &sdhci_esdhc_ops,
 799 };
 800
 801 #ifdef CONFIG_OF
 802 static int
 803 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 804                          struct esdhc_platform_data *boarddata)
 805 {
 806         struct device_node *np = pdev->dev.of_node;
 807
 808         if (!np)
 809                 return -ENODEV;
 810
 811         if (of_get_property(np, "non-removable", NULL))
 812                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 813
 814         if (of_get_property(np, "fsl,cd-controller", NULL))
 815                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 816
 817         if (of_get_property(np, "fsl,wp-controller", NULL))
 818                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 819
 820         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 821         if (gpio_is_valid(boarddata->cd_gpio))
 822                 boarddata->cd_type = ESDHC_CD_GPIO;
 823
 824         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 825         if (gpio_is_valid(boarddata->wp_gpio))
 826                 boarddata->wp_type = ESDHC_WP_GPIO;
 827
 828         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 829
 830         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 831
 832         if (of_find_property(np, "no-1-8-v", NULL))
 833                 boarddata->support_vsel = false;
 834         else
 835                 boarddata->support_vsel = true;
 836
 837         return 0;
 838 }
 839 #else
 840 static inline int
 841 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 842                          struct esdhc_platform_data *boarddata)
 843 {
 844         return -ENODEV;
 845 }
 846 #endif
 847
 848 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 849 {
 850         const struct of_device_id *of_id =
 851                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 852         struct sdhci_pltfm_host *pltfm_host;
 853         struct sdhci_host *host;
 854         struct esdhc_platform_data *boarddata;
 855         int err;
 856         struct pltfm_imx_data *imx_data;
 857
 858         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 859         if (IS_ERR(host))
 860                 return PTR_ERR(host);
 861
 862         pltfm_host = sdhci_priv(host);
 863
 864         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 865         if (!imx_data) {
 866                 err = -ENOMEM;
 867                 goto free_sdhci;
 868         }
 869
 870         if (of_id)
 871                 pdev->id_entry = of_id->data;
 872         imx_data->devtype = pdev->id_entry->driver_data;
 873         pltfm_host->priv = imx_data;
 874
 875         if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
 876                 imx_data->flags |= ESDHC_FLAG_ENGCM07207;
 877
 878         if (is_imx6q_usdhc(imx_data))
 879                 imx_data->flags |= ESDHC_FLAG_USDHC;
 880
 881         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 882         if (IS_ERR(imx_data->clk_ipg)) {
 883                 err = PTR_ERR(imx_data->clk_ipg);
 884                 goto free_sdhci;
 885         }
 886
 887         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 888         if (IS_ERR(imx_data->clk_ahb)) {
 889                 err = PTR_ERR(imx_data->clk_ahb);
 890                 goto free_sdhci;
 891         }
 892
 893         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
 894         if (IS_ERR(imx_data->clk_per)) {
 895                 err = PTR_ERR(imx_data->clk_per);
 896                 goto free_sdhci;
 897         }
 898
 899         pltfm_host->clk = imx_data->clk_per;
 900
 901         clk_prepare_enable(imx_data->clk_per);
 902         clk_prepare_enable(imx_data->clk_ipg);
 903         clk_prepare_enable(imx_data->clk_ahb);
 904
 905         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
 906         if (IS_ERR(imx_data->pinctrl)) {
 907                 err = PTR_ERR(imx_data->pinctrl);
 908                 goto disable_clk;
 909         }
 910
 911         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
 912                                                 PINCTRL_STATE_DEFAULT);
 913         if (IS_ERR(imx_data->pins_default)) {
 914                 err = PTR_ERR(imx_data->pins_default);
 915                 dev_err(mmc_dev(host->mmc), "could not get default state\n");
 916                 goto disable_clk;
 917         }
 918
 919         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 920
 921         if (imx_data->flags & ESDHC_FLAG_ENGCM07207)
 922                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
 923                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
 924                         | SDHCI_QUIRK_BROKEN_ADMA;
 925
 926         if (is_imx53_esdhc(imx_data))
 927                 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
 928
 929         /*
 930          * The imx6q ROM code will change the default watermark level setting
 931          * to something insane.  Change it back here.
 932          */
 933         if (esdhc_is_usdhc(imx_data))
 934                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
 935
 936         boarddata = &imx_data->boarddata;
 937         if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
 938                 if (!host->mmc->parent->platform_data) {
 939                         dev_err(mmc_dev(host->mmc), "no board data!\n");
 940                         err = -EINVAL;
 941                         goto disable_clk;
 942                 }
 943                 imx_data->boarddata = *((struct esdhc_platform_data *)
 944                                         host->mmc->parent->platform_data);
 945         }
 946
 947         /* write_protect */
 948         if (boarddata->wp_type == ESDHC_WP_GPIO) {
 949                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
 950                 if (err) {
 951                         dev_err(mmc_dev(host->mmc),
 952                                 "failed to request write-protect gpio!\n");
 953                         goto disable_clk;
 954                 }
 955                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
 956         }
 957
 958         /* card_detect */
 959         switch (boarddata->cd_type) {
 960         case ESDHC_CD_GPIO:
 961                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
 962                 if (err) {
 963                         dev_err(mmc_dev(host->mmc),
 964                                 "failed to request card-detect gpio!\n");
 965                         goto disable_clk;
 966                 }
 967                 /* fall through */
 968
 969         case ESDHC_CD_CONTROLLER:
 970                 /* we have a working card_detect back */
 971                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 972                 break;
 973
 974         case ESDHC_CD_PERMANENT:
 975                 host->mmc->caps = MMC_CAP_NONREMOVABLE;
 976                 break;
 977
 978         case ESDHC_CD_NONE:
 979                 break;
 980         }
 981
 982         switch (boarddata->max_bus_width) {
 983         case 8:
 984                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
 985                 break;
 986         case 4:
 987                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
 988                 break;
 989         case 1:
 990         default:
 991                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
 992                 break;
 993         }
 994
 995         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
 996         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
 997                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
 998                                                 ESDHC_PINCTRL_STATE_100MHZ);
 999                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1000                                                 ESDHC_PINCTRL_STATE_200MHZ);
1001                 if (IS_ERR(imx_data->pins_100mhz) ||
1002                                 IS_ERR(imx_data->pins_200mhz)) {
1003                         dev_warn(mmc_dev(host->mmc),
1004                                 "could not get ultra high speed state, work on normal mode\n");
1005                         /* fall back to not support uhs by specify no 1.8v quirk */
1006                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1007                 }
1008         } else {
1009                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1010         }
1011
1012         err = sdhci_add_host(host);
1013         if (err)
1014                 goto disable_clk;
1015
1016         return 0;
1017
1018 disable_clk:
1019         clk_disable_unprepare(imx_data->clk_per);
1020         clk_disable_unprepare(imx_data->clk_ipg);
1021         clk_disable_unprepare(imx_data->clk_ahb);
1022 free_sdhci:
1023         sdhci_pltfm_free(pdev);
1024         return err;
1025 }
1026
1027 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1028 {
1029         struct sdhci_host *host = platform_get_drvdata(pdev);
1030         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1031         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1032         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1033
1034         sdhci_remove_host(host, dead);
1035
1036         clk_disable_unprepare(imx_data->clk_per);
1037         clk_disable_unprepare(imx_data->clk_ipg);
1038         clk_disable_unprepare(imx_data->clk_ahb);
1039
1040         sdhci_pltfm_free(pdev);
1041
1042         return 0;
1043 }
1044
1045 static struct platform_driver sdhci_esdhc_imx_driver = {
1046         .driver         = {
1047                 .name   = "sdhci-esdhc-imx",
1048                 .owner  = THIS_MODULE,
1049                 .of_match_table = imx_esdhc_dt_ids,
1050                 .pm     = SDHCI_PLTFM_PMOPS,
1051         },
1052         .id_table       = imx_esdhc_devtype,
1053         .probe          = sdhci_esdhc_imx_probe,
1054         .remove         = sdhci_esdhc_imx_remove,
1055 };
1056
1057 module_platform_driver(sdhci_esdhc_imx_driver);
1058
1059 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1060 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1061 MODULE_LICENSE("GPL v2");