drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include <linux/pm_runtime.h>
  31 #include "sdhci-pltfm.h"
  32 #include "sdhci-esdhc.h"
  33
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 /* VENDOR SPEC register */
  36 #define ESDHC_VENDOR_SPEC               0xc0
  37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  40 #define ESDHC_WTMK_LVL                  0x44
  41 #define ESDHC_MIX_CTRL                  0x48
  42 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  43 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  44 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  45 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  46 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  47 /* Bits 3 and 6 are not SDHCI standard definitions */
  48 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  49 /* Tuning bits */
  50 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  51
  52 /* dll control register */
  53 #define ESDHC_DLL_CTRL                  0x60
  54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  56
  57 /* dll control register */
  58 #define ESDHC_DLL_CTRL                  0x60
  59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  61
  62 /* tune control register */
  63 #define ESDHC_TUNE_CTRL_STATUS          0x68
  64 #define  ESDHC_TUNE_CTRL_STEP           1
  65 #define  ESDHC_TUNE_CTRL_MIN            0
  66 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  67
  68 #define ESDHC_TUNING_CTRL               0xcc
  69 #define ESDHC_STD_TUNING_EN             (1 << 24)
  70 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  71 #define ESDHC_TUNING_START_TAP          0x1
  72
  73 #define ESDHC_TUNING_BLOCK_PATTERN_LEN  64
  74
  75 /* pinctrl state */
  76 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  77 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  78
  79 /*
  80  * Our interpretation of the SDHCI_HOST_CONTROL register
  81  */
  82 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  83 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  84 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  85
  86 /*
  87  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  88  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  89  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  90  * Define this macro DMA error INT for fsl eSDHC
  91  */
  92 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  93
  94 /*
  95  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  96  * "11" when the STOP CMD12 is issued on imx53 to abort one
  97  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  98  * be generated.
  99  * In exact block transfer, the controller doesn't complete the
 100  * operations automatically as required at the end of the
 101  * transfer and remains on hold if the abort command is not sent.
 102  * As a result, the TC flag is not asserted and SW  received timeout
 103  * exeception. Bit1 of Vendor Spec registor is used to fix it.
 104  */
 105 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 106 /*
 107  * The flag enables the workaround for ESDHC errata ENGcm07207 which
 108  * affects i.MX25 and i.MX35.
 109  */
 110 #define ESDHC_FLAG_ENGCM07207           BIT(2)
 111 /*
 112  * The flag tells that the ESDHC controller is an USDHC block that is
 113  * integrated on the i.MX6 series.
 114  */
 115 #define ESDHC_FLAG_USDHC                BIT(3)
 116 /* The IP supports manual tuning process */
 117 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 118 /* The IP supports standard tuning process */
 119 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 120 /* The IP has SDHCI_CAPABILITIES_1 register */
 121 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 122 /* The IP has errata ERR004536 */
 123 #define ESDHC_FLAG_ERR004536            BIT(7)
 124
 125 struct esdhc_soc_data {
 126         u32 flags;
 127 };
 128
 129 static struct esdhc_soc_data esdhc_imx25_data = {
 130         .flags = ESDHC_FLAG_ENGCM07207,
 131 };
 132
 133 static struct esdhc_soc_data esdhc_imx35_data = {
 134         .flags = ESDHC_FLAG_ENGCM07207,
 135 };
 136
 137 static struct esdhc_soc_data esdhc_imx51_data = {
 138         .flags = 0,
 139 };
 140
 141 static struct esdhc_soc_data esdhc_imx53_data = {
 142         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 143 };
 144
 145 static struct esdhc_soc_data usdhc_imx6q_data = {
 146         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 147 };
 148
 149 static struct esdhc_soc_data usdhc_imx6sl_data = {
 150         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 151                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
 152 };
 153
 154 struct pltfm_imx_data {
 155         u32 scratchpad;
 156         struct pinctrl *pinctrl;
 157         struct pinctrl_state *pins_default;
 158         struct pinctrl_state *pins_100mhz;
 159         struct pinctrl_state *pins_200mhz;
 160         const struct esdhc_soc_data *socdata;
 161         struct esdhc_platform_data boarddata;
 162         struct clk *clk_ipg;
 163         struct clk *clk_ahb;
 164         struct clk *clk_per;
 165         enum {
 166                 NO_CMD_PENDING,      /* no multiblock command pending*/
 167                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 168                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 169         } multiblock_status;
 170         u32 is_ddr;
 171 };
 172
 173 static struct platform_device_id imx_esdhc_devtype[] = {
 174         {
 175                 .name = "sdhci-esdhc-imx25",
 176                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 177         }, {
 178                 .name = "sdhci-esdhc-imx35",
 179                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 180         }, {
 181                 .name = "sdhci-esdhc-imx51",
 182                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 183         }, {
 184                 /* sentinel */
 185         }
 186 };
 187 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 188
 189 static const struct of_device_id imx_esdhc_dt_ids[] = {
 190         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 191         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 192         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 193         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 194         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 195         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 196         { /* sentinel */ }
 197 };
 198 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 199
 200 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 201 {
 202         return data->socdata == &esdhc_imx25_data;
 203 }
 204
 205 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 206 {
 207         return data->socdata == &esdhc_imx53_data;
 208 }
 209
 210 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 211 {
 212         return data->socdata == &usdhc_imx6q_data;
 213 }
 214
 215 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 216 {
 217         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 218 }
 219
 220 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 221 {
 222         void __iomem *base = host->ioaddr + (reg & ~0x3);
 223         u32 shift = (reg & 0x3) * 8;
 224
 225         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 226 }
 227
 228 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 229 {
 230         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 231         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 232         u32 val = readl(host->ioaddr + reg);
 233
 234         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 235                 u32 fsl_prss = val;
 236                 /* save the least 20 bits */
 237                 val = fsl_prss & 0x000FFFFF;
 238                 /* move dat[0-3] bits */
 239                 val |= (fsl_prss & 0x0F000000) >> 4;
 240                 /* move cmd line bit */
 241                 val |= (fsl_prss & 0x00800000) << 1;
 242         }
 243
 244         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 245                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 246                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 247                         val &= 0xffff0000;
 248
 249                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 250                  * ADMA2 capability of esdhc, but this bit is messed up on
 251                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 252                  * don't actually support ADMA2). So set the BROKEN_ADMA
 253                  * uirk on MX25/35 platforms.
 254                  */
 255
 256                 if (val & SDHCI_CAN_DO_ADMA1) {
 257                         val &= ~SDHCI_CAN_DO_ADMA1;
 258                         val |= SDHCI_CAN_DO_ADMA2;
 259                 }
 260         }
 261
 262         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 263                 if (esdhc_is_usdhc(imx_data)) {
 264                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 265                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 266                         else
 267                                 /* imx6q/dl does not have cap_1 register, fake one */
 268                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 269                                         | SDHCI_SUPPORT_SDR50
 270                                         | SDHCI_USE_SDR50_TUNING;
 271                 }
 272         }
 273
 274         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 275                 val = 0;
 276                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 277                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 278                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 279         }
 280
 281         if (unlikely(reg == SDHCI_INT_STATUS)) {
 282                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 283                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 284                         val |= SDHCI_INT_ADMA_ERROR;
 285                 }
 286
 287                 /*
 288                  * mask off the interrupt we get in response to the manually
 289                  * sent CMD12
 290                  */
 291                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 292                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 293                         val &= ~SDHCI_INT_RESPONSE;
 294                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 295                                                    SDHCI_INT_STATUS);
 296                         imx_data->multiblock_status = NO_CMD_PENDING;
 297                 }
 298         }
 299
 300         return val;
 301 }
 302
 303 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 304 {
 305         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 306         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 307         u32 data;
 308
 309         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 310                 if (val & SDHCI_INT_CARD_INT) {
 311                         /*
 312                          * Clear and then set D3CD bit to avoid missing the
 313                          * card interrupt.  This is a eSDHC controller problem
 314                          * so we need to apply the following workaround: clear
 315                          * and set D3CD bit will make eSDHC re-sample the card
 316                          * interrupt. In case a card interrupt was lost,
 317                          * re-sample it by the following steps.
 318                          */
 319                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 320                         data &= ~ESDHC_CTRL_D3CD;
 321                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 322                         data |= ESDHC_CTRL_D3CD;
 323                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 324                 }
 325         }
 326
 327         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 328                                 && (reg == SDHCI_INT_STATUS)
 329                                 && (val & SDHCI_INT_DATA_END))) {
 330                         u32 v;
 331                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 332                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 333                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 334
 335                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 336                         {
 337                                 /* send a manual CMD12 with RESPTYP=none */
 338                                 data = MMC_STOP_TRANSMISSION << 24 |
 339                                        SDHCI_CMD_ABORTCMD << 16;
 340                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 341                                 imx_data->multiblock_status = WAIT_FOR_INT;
 342                         }
 343         }
 344
 345         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 346                 if (val & SDHCI_INT_ADMA_ERROR) {
 347                         val &= ~SDHCI_INT_ADMA_ERROR;
 348                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 349                 }
 350         }
 351
 352         writel(val, host->ioaddr + reg);
 353 }
 354
 355 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 356 {
 357         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 358         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 359         u16 ret = 0;
 360         u32 val;
 361
 362         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 363                 reg ^= 2;
 364                 if (esdhc_is_usdhc(imx_data)) {
 365                         /*
 366                          * The usdhc register returns a wrong host version.
 367                          * Correct it here.
 368                          */
 369                         return SDHCI_SPEC_300;
 370                 }
 371         }
 372
 373         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 374                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 375                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 376                         ret |= SDHCI_CTRL_VDD_180;
 377
 378                 if (esdhc_is_usdhc(imx_data)) {
 379                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 380                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 381                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 382                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 383                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 384                 }
 385
 386                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 387                         ret |= SDHCI_CTRL_EXEC_TUNING;
 388                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 389                         ret |= SDHCI_CTRL_TUNED_CLK;
 390
 391                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 392
 393                 return ret;
 394         }
 395
 396         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 397                 if (esdhc_is_usdhc(imx_data)) {
 398                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 399                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 400                         /* Swap AC23 bit */
 401                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 402                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 403                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 404                         }
 405                 } else {
 406                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 407                 }
 408
 409                 return ret;
 410         }
 411
 412         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 413                 if (esdhc_is_usdhc(imx_data)) {
 414                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 415                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 416                         /* Swap AC23 bit */
 417                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 418                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 419                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 420                         }
 421                 } else {
 422                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 423                 }
 424
 425                 return ret;
 426         }
 427
 428         return readw(host->ioaddr + reg);
 429 }
 430
 431 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 432 {
 433         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 434         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 435         u32 new_val = 0;
 436
 437         switch (reg) {
 438         case SDHCI_CLOCK_CONTROL:
 439                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 440                 if (val & SDHCI_CLOCK_CARD_EN)
 441                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 442                 else
 443                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 444                         writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 445                 return;
 446         case SDHCI_HOST_CONTROL2:
 447                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 448                 if (val & SDHCI_CTRL_VDD_180)
 449                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 450                 else
 451                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 452                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 453                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 454                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 455                         if (val & SDHCI_CTRL_TUNED_CLK)
 456                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 457                         else
 458                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 459                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 460                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 461                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 462                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 463                         if (val & SDHCI_CTRL_TUNED_CLK) {
 464                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 465                         } else {
 466                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 467                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 468                         }
 469
 470                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 471                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 472                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 473                         } else {
 474                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 475                         }
 476
 477                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 478                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 479                 }
 480                 return;
 481         case SDHCI_TRANSFER_MODE:
 482                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 483                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 484                                 && (host->cmd->data->blocks > 1)
 485                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 486                         u32 v;
 487                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 488                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 489                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 490                 }
 491
 492                 if (esdhc_is_usdhc(imx_data)) {
 493                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 494                         /* Swap AC23 bit */
 495                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 496                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 497                                 val |= ESDHC_MIX_CTRL_AC23EN;
 498                         }
 499                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 500                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 501                 } else {
 502                         /*
 503                          * Postpone this write, we must do it together with a
 504                          * command write that is down below.
 505                          */
 506                         imx_data->scratchpad = val;
 507                 }
 508                 return;
 509         case SDHCI_COMMAND:
 510                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 511                         val |= SDHCI_CMD_ABORTCMD;
 512
 513                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 514                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 515                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 516
 517                 if (esdhc_is_usdhc(imx_data))
 518                         writel(val << 16,
 519                                host->ioaddr + SDHCI_TRANSFER_MODE);
 520                 else
 521                         writel(val << 16 | imx_data->scratchpad,
 522                                host->ioaddr + SDHCI_TRANSFER_MODE);
 523                 return;
 524         case SDHCI_BLOCK_SIZE:
 525                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 526                 break;
 527         }
 528         esdhc_clrset_le(host, 0xffff, val, reg);
 529 }
 530
 531 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 532 {
 533         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 534         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 535         u32 new_val;
 536         u32 mask;
 537
 538         switch (reg) {
 539         case SDHCI_POWER_CONTROL:
 540                 /*
 541                  * FSL put some DMA bits here
 542                  * If your board has a regulator, code should be here
 543                  */
 544                 return;
 545         case SDHCI_HOST_CONTROL:
 546                 /* FSL messed up here, so we need to manually compose it. */
 547                 new_val = val & SDHCI_CTRL_LED;
 548                 /* ensure the endianness */
 549                 new_val |= ESDHC_HOST_CONTROL_LE;
 550                 /* bits 8&9 are reserved on mx25 */
 551                 if (!is_imx25_esdhc(imx_data)) {
 552                         /* DMA mode bits are shifted */
 553                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 554                 }
 555
 556                 /*
 557                  * Do not touch buswidth bits here. This is done in
 558                  * esdhc_pltfm_bus_width.
 559                  * Do not touch the D3CD bit either which is used for the
 560                  * SDIO interrupt errata workaround.
 561                  */
 562                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 563
 564                 esdhc_clrset_le(host, mask, new_val, reg);
 565                 return;
 566         }
 567         esdhc_clrset_le(host, 0xff, val, reg);
 568
 569         /*
 570          * The esdhc has a design violation to SDHC spec which tells
 571          * that software reset should not affect card detection circuit.
 572          * But esdhc clears its SYSCTL register bits [0..2] during the
 573          * software reset.  This will stop those clocks that card detection
 574          * circuit relies on.  To work around it, we turn the clocks on back
 575          * to keep card detection circuit functional.
 576          */
 577         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 578                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 579                 /*
 580                  * The reset on usdhc fails to clear MIX_CTRL register.
 581                  * Do it manually here.
 582                  */
 583                 if (esdhc_is_usdhc(imx_data)) {
 584                         /* the tuning bits should be kept during reset */
 585                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 586                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 587                                         host->ioaddr + ESDHC_MIX_CTRL);
 588                         imx_data->is_ddr = 0;
 589                 }
 590         }
 591 }
 592
 593 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 594 {
 595         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 596         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 597         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 598
 599         if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
 600                 return boarddata->f_max;
 601         else
 602                 return pltfm_host->clock;
 603 }
 604
 605 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 606 {
 607         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 608
 609         return pltfm_host->clock / 256 / 16;
 610 }
 611
 612 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 613                                          unsigned int clock)
 614 {
 615         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 616         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 617         unsigned int host_clock = pltfm_host->clock;
 618         int pre_div = 2;
 619         int div = 1;
 620         u32 temp, val;
 621
 622         if (clock == 0) {
 623                 host->mmc->actual_clock = 0;
 624
 625                 if (esdhc_is_usdhc(imx_data)) {
 626                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 627                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 628                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 629                 }
 630                 return;
 631         }
 632
 633         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
 634                 pre_div = 1;
 635
 636         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 637         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 638                 | ESDHC_CLOCK_MASK);
 639         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 640
 641         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 642                 pre_div *= 2;
 643
 644         while (host_clock / pre_div / div > clock && div < 16)
 645                 div++;
 646
 647         host->mmc->actual_clock = host_clock / pre_div / div;
 648         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 649                 clock, host->mmc->actual_clock);
 650
 651         if (imx_data->is_ddr)
 652                 pre_div >>= 2;
 653         else
 654                 pre_div >>= 1;
 655         div--;
 656
 657         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 658         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 659                 | (div << ESDHC_DIVIDER_SHIFT)
 660                 | (pre_div << ESDHC_PREDIV_SHIFT));
 661         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 662
 663         if (esdhc_is_usdhc(imx_data)) {
 664                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 665                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 666                 host->ioaddr + ESDHC_VENDOR_SPEC);
 667         }
 668
 669         mdelay(1);
 670 }
 671
 672 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 673 {
 674         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 675         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 676         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 677
 678         switch (boarddata->wp_type) {
 679         case ESDHC_WP_GPIO:
 680                 return mmc_gpio_get_ro(host->mmc);
 681         case ESDHC_WP_CONTROLLER:
 682                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 683                                SDHCI_WRITE_PROTECT);
 684         case ESDHC_WP_NONE:
 685                 break;
 686         }
 687
 688         return -ENOSYS;
 689 }
 690
 691 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 692 {
 693         u32 ctrl;
 694
 695         switch (width) {
 696         case MMC_BUS_WIDTH_8:
 697                 ctrl = ESDHC_CTRL_8BITBUS;
 698                 break;
 699         case MMC_BUS_WIDTH_4:
 700                 ctrl = ESDHC_CTRL_4BITBUS;
 701                 break;
 702         default:
 703                 ctrl = 0;
 704                 break;
 705         }
 706
 707         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 708                         SDHCI_HOST_CONTROL);
 709 }
 710
 711 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 712 {
 713         u32 reg;
 714
 715         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 716         mdelay(1);
 717
 718         /* This is balanced by the runtime put in sdhci_tasklet_finish */
 719         pm_runtime_get_sync(host->mmc->parent);
 720         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 721         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 722                         ESDHC_MIX_CTRL_FBCLK_SEL;
 723         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 724         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 725         dev_dbg(mmc_dev(host->mmc),
 726                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 727                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 728 }
 729
 730 static void esdhc_request_done(struct mmc_request *mrq)
 731 {
 732         complete(&mrq->completion);
 733 }
 734
 735 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
 736                                  struct scatterlist *sg)
 737 {
 738         struct mmc_command cmd = {0};
 739         struct mmc_request mrq = {NULL};
 740         struct mmc_data data = {0};
 741
 742         cmd.opcode = opcode;
 743         cmd.arg = 0;
 744         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 745
 746         data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
 747         data.blocks = 1;
 748         data.flags = MMC_DATA_READ;
 749         data.sg = sg;
 750         data.sg_len = 1;
 751
 752         mrq.cmd = &cmd;
 753         mrq.cmd->mrq = &mrq;
 754         mrq.data = &data;
 755         mrq.data->mrq = &mrq;
 756         mrq.cmd->data = mrq.data;
 757
 758         mrq.done = esdhc_request_done;
 759         init_completion(&(mrq.completion));
 760
 761         spin_lock_irq(&host->lock);
 762         host->mrq = &mrq;
 763
 764         sdhci_send_command(host, mrq.cmd);
 765
 766         spin_unlock_irq(&host->lock);
 767
 768         wait_for_completion(&mrq.completion);
 769
 770         if (cmd.error)
 771                 return cmd.error;
 772         if (data.error)
 773                 return data.error;
 774
 775         return 0;
 776 }
 777
 778 static void esdhc_post_tuning(struct sdhci_host *host)
 779 {
 780         u32 reg;
 781
 782         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 783         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 784         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 785 }
 786
 787 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 788 {
 789         struct scatterlist sg;
 790         char *tuning_pattern;
 791         int min, max, avg, ret;
 792
 793         tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
 794         if (!tuning_pattern)
 795                 return -ENOMEM;
 796
 797         sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
 798
 799         /* find the mininum delay first which can pass tuning */
 800         min = ESDHC_TUNE_CTRL_MIN;
 801         while (min < ESDHC_TUNE_CTRL_MAX) {
 802                 esdhc_prepare_tuning(host, min);
 803                 if (!esdhc_send_tuning_cmd(host, opcode, &sg))
 804                         break;
 805                 min += ESDHC_TUNE_CTRL_STEP;
 806         }
 807
 808         /* find the maxinum delay which can not pass tuning */
 809         max = min + ESDHC_TUNE_CTRL_STEP;
 810         while (max < ESDHC_TUNE_CTRL_MAX) {
 811                 esdhc_prepare_tuning(host, max);
 812                 if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
 813                         max -= ESDHC_TUNE_CTRL_STEP;
 814                         break;
 815                 }
 816                 max += ESDHC_TUNE_CTRL_STEP;
 817         }
 818
 819         /* use average delay to get the best timing */
 820         avg = (min + max) / 2;
 821         esdhc_prepare_tuning(host, avg);
 822         ret = esdhc_send_tuning_cmd(host, opcode, &sg);
 823         esdhc_post_tuning(host);
 824
 825         kfree(tuning_pattern);
 826
 827         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 828                 ret ? "failed" : "passed", avg, ret);
 829
 830         return ret;
 831 }
 832
 833 static int esdhc_change_pinstate(struct sdhci_host *host,
 834                                                 unsigned int uhs)
 835 {
 836         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 837         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 838         struct pinctrl_state *pinctrl;
 839
 840         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 841
 842         if (IS_ERR(imx_data->pinctrl) ||
 843                 IS_ERR(imx_data->pins_default) ||
 844                 IS_ERR(imx_data->pins_100mhz) ||
 845                 IS_ERR(imx_data->pins_200mhz))
 846                 return -EINVAL;
 847
 848         switch (uhs) {
 849         case MMC_TIMING_UHS_SDR50:
 850                 pinctrl = imx_data->pins_100mhz;
 851                 break;
 852         case MMC_TIMING_UHS_SDR104:
 853         case MMC_TIMING_MMC_HS200:
 854                 pinctrl = imx_data->pins_200mhz;
 855                 break;
 856         default:
 857                 /* back to default state for other legacy timing */
 858                 pinctrl = imx_data->pins_default;
 859         }
 860
 861         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 862 }
 863
 864 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 865 {
 866         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 867         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 868         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 869
 870         switch (timing) {
 871         case MMC_TIMING_UHS_SDR12:
 872         case MMC_TIMING_UHS_SDR25:
 873         case MMC_TIMING_UHS_SDR50:
 874         case MMC_TIMING_UHS_SDR104:
 875         case MMC_TIMING_MMC_HS200:
 876                 break;
 877         case MMC_TIMING_UHS_DDR50:
 878         case MMC_TIMING_MMC_DDR52:
 879                 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
 880                                 ESDHC_MIX_CTRL_DDREN,
 881                                 host->ioaddr + ESDHC_MIX_CTRL);
 882                 imx_data->is_ddr = 1;
 883                 if (boarddata->delay_line) {
 884                         u32 v;
 885                         v = boarddata->delay_line <<
 886                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 887                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 888                         if (is_imx53_esdhc(imx_data))
 889                                 v <<= 1;
 890                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 891                 }
 892                 break;
 893         }
 894
 895         esdhc_change_pinstate(host, timing);
 896 }
 897
 898 static void esdhc_reset(struct sdhci_host *host, u8 mask)
 899 {
 900         sdhci_reset(host, mask);
 901
 902         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 903         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 904 }
 905
 906 static struct sdhci_ops sdhci_esdhc_ops = {
 907         .read_l = esdhc_readl_le,
 908         .read_w = esdhc_readw_le,
 909         .write_l = esdhc_writel_le,
 910         .write_w = esdhc_writew_le,
 911         .write_b = esdhc_writeb_le,
 912         .set_clock = esdhc_pltfm_set_clock,
 913         .get_max_clock = esdhc_pltfm_get_max_clock,
 914         .get_min_clock = esdhc_pltfm_get_min_clock,
 915         .get_ro = esdhc_pltfm_get_ro,
 916         .set_bus_width = esdhc_pltfm_set_bus_width,
 917         .set_uhs_signaling = esdhc_set_uhs_signaling,
 918         .reset = esdhc_reset,
 919 };
 920
 921 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 922         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 923                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 924                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 925                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 926         .ops = &sdhci_esdhc_ops,
 927 };
 928
 929 #ifdef CONFIG_OF
 930 static int
 931 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 932                          struct esdhc_platform_data *boarddata)
 933 {
 934         struct device_node *np = pdev->dev.of_node;
 935
 936         if (!np)
 937                 return -ENODEV;
 938
 939         if (of_get_property(np, "non-removable", NULL))
 940                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 941
 942         if (of_get_property(np, "fsl,cd-controller", NULL))
 943                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 944
 945         if (of_get_property(np, "fsl,wp-controller", NULL))
 946                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 947
 948         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 949         if (gpio_is_valid(boarddata->cd_gpio))
 950                 boarddata->cd_type = ESDHC_CD_GPIO;
 951
 952         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 953         if (gpio_is_valid(boarddata->wp_gpio))
 954                 boarddata->wp_type = ESDHC_WP_GPIO;
 955
 956         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 957
 958         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 959
 960         if (of_find_property(np, "no-1-8-v", NULL))
 961                 boarddata->support_vsel = false;
 962         else
 963                 boarddata->support_vsel = true;
 964
 965         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 966                 boarddata->delay_line = 0;
 967
 968         return 0;
 969 }
 970 #else
 971 static inline int
 972 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 973                          struct esdhc_platform_data *boarddata)
 974 {
 975         return -ENODEV;
 976 }
 977 #endif
 978
 979 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 980 {
 981         const struct of_device_id *of_id =
 982                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 983         struct sdhci_pltfm_host *pltfm_host;
 984         struct sdhci_host *host;
 985         struct esdhc_platform_data *boarddata;
 986         int err;
 987         struct pltfm_imx_data *imx_data;
 988
 989         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 990         if (IS_ERR(host))
 991                 return PTR_ERR(host);
 992
 993         pltfm_host = sdhci_priv(host);
 994
 995         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 996         if (!imx_data) {
 997                 err = -ENOMEM;
 998                 goto free_sdhci;
 999         }
1000
1001         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1002                                                   pdev->id_entry->driver_data;
1003         pltfm_host->priv = imx_data;
1004
1005         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1006         if (IS_ERR(imx_data->clk_ipg)) {
1007                 err = PTR_ERR(imx_data->clk_ipg);
1008                 goto free_sdhci;
1009         }
1010
1011         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1012         if (IS_ERR(imx_data->clk_ahb)) {
1013                 err = PTR_ERR(imx_data->clk_ahb);
1014                 goto free_sdhci;
1015         }
1016
1017         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1018         if (IS_ERR(imx_data->clk_per)) {
1019                 err = PTR_ERR(imx_data->clk_per);
1020                 goto free_sdhci;
1021         }
1022
1023         pltfm_host->clk = imx_data->clk_per;
1024         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1025         clk_prepare_enable(imx_data->clk_per);
1026         clk_prepare_enable(imx_data->clk_ipg);
1027         clk_prepare_enable(imx_data->clk_ahb);
1028
1029         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1030         if (IS_ERR(imx_data->pinctrl)) {
1031                 err = PTR_ERR(imx_data->pinctrl);
1032                 goto disable_clk;
1033         }
1034
1035         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1036                                                 PINCTRL_STATE_DEFAULT);
1037         if (IS_ERR(imx_data->pins_default)) {
1038                 err = PTR_ERR(imx_data->pins_default);
1039                 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1040                 goto disable_clk;
1041         }
1042
1043         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1044
1045         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1046                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1047                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1048                         | SDHCI_QUIRK_BROKEN_ADMA;
1049
1050         /*
1051          * The imx6q ROM code will change the default watermark level setting
1052          * to something insane.  Change it back here.
1053          */
1054         if (esdhc_is_usdhc(imx_data)) {
1055                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1056                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1057                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1058
1059                 /*
1060                  * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1061                  * TO1.1, it's harmless for MX6SL
1062                  */
1063                 writel(readl(host->ioaddr + 0x6c) | BIT(7), host->ioaddr + 0x6c);
1064         }
1065
1066         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1067                 sdhci_esdhc_ops.platform_execute_tuning =
1068                                         esdhc_executing_tuning;
1069
1070         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1071                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1072                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1073                         host->ioaddr + ESDHC_TUNING_CTRL);
1074
1075         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1076                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1077
1078         boarddata = &imx_data->boarddata;
1079         if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1080                 if (!host->mmc->parent->platform_data) {
1081                         dev_err(mmc_dev(host->mmc), "no board data!\n");
1082                         err = -EINVAL;
1083                         goto disable_clk;
1084                 }
1085                 imx_data->boarddata = *((struct esdhc_platform_data *)
1086                                         host->mmc->parent->platform_data);
1087         }
1088
1089         /* write_protect */
1090         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1091                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1092                 if (err) {
1093                         dev_err(mmc_dev(host->mmc),
1094                                 "failed to request write-protect gpio!\n");
1095                         goto disable_clk;
1096                 }
1097                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1098         }
1099
1100         /* card_detect */
1101         switch (boarddata->cd_type) {
1102         case ESDHC_CD_GPIO:
1103                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1104                 if (err) {
1105                         dev_err(mmc_dev(host->mmc),
1106                                 "failed to request card-detect gpio!\n");
1107                         goto disable_clk;
1108                 }
1109                 /* fall through */
1110
1111         case ESDHC_CD_CONTROLLER:
1112                 /* we have a working card_detect back */
1113                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1114                 break;
1115
1116         case ESDHC_CD_PERMANENT:
1117                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1118                 break;
1119
1120         case ESDHC_CD_NONE:
1121                 break;
1122         }
1123
1124         switch (boarddata->max_bus_width) {
1125         case 8:
1126                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1127                 break;
1128         case 4:
1129                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1130                 break;
1131         case 1:
1132         default:
1133                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1134                 break;
1135         }
1136
1137         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1138         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
1139                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1140                                                 ESDHC_PINCTRL_STATE_100MHZ);
1141                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1142                                                 ESDHC_PINCTRL_STATE_200MHZ);
1143                 if (IS_ERR(imx_data->pins_100mhz) ||
1144                                 IS_ERR(imx_data->pins_200mhz)) {
1145                         dev_warn(mmc_dev(host->mmc),
1146                                 "could not get ultra high speed state, work on normal mode\n");
1147                         /* fall back to not support uhs by specify no 1.8v quirk */
1148                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1149                 }
1150         } else {
1151                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1152         }
1153
1154         err = sdhci_add_host(host);
1155         if (err)
1156                 goto disable_clk;
1157
1158         pm_runtime_set_active(&pdev->dev);
1159         pm_runtime_enable(&pdev->dev);
1160         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1161         pm_runtime_use_autosuspend(&pdev->dev);
1162         pm_suspend_ignore_children(&pdev->dev, 1);
1163
1164         return 0;
1165
1166 disable_clk:
1167         clk_disable_unprepare(imx_data->clk_per);
1168         clk_disable_unprepare(imx_data->clk_ipg);
1169         clk_disable_unprepare(imx_data->clk_ahb);
1170 free_sdhci:
1171         sdhci_pltfm_free(pdev);
1172         return err;
1173 }
1174
1175 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1176 {
1177         struct sdhci_host *host = platform_get_drvdata(pdev);
1178         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1179         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1180         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1181
1182         sdhci_remove_host(host, dead);
1183
1184         pm_runtime_dont_use_autosuspend(&pdev->dev);
1185         pm_runtime_disable(&pdev->dev);
1186
1187         if (!IS_ENABLED(CONFIG_PM_RUNTIME)) {
1188                 clk_disable_unprepare(imx_data->clk_per);
1189                 clk_disable_unprepare(imx_data->clk_ipg);
1190                 clk_disable_unprepare(imx_data->clk_ahb);
1191         }
1192
1193         sdhci_pltfm_free(pdev);
1194
1195         return 0;
1196 }
1197
1198 #ifdef CONFIG_PM_RUNTIME
1199 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1200 {
1201         struct sdhci_host *host = dev_get_drvdata(dev);
1202         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1203         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1204         int ret;
1205
1206         ret = sdhci_runtime_suspend_host(host);
1207
1208         if (!sdhci_sdio_irq_enabled(host)) {
1209                 clk_disable_unprepare(imx_data->clk_per);
1210                 clk_disable_unprepare(imx_data->clk_ipg);
1211         }
1212         clk_disable_unprepare(imx_data->clk_ahb);
1213
1214         return ret;
1215 }
1216
1217 static int sdhci_esdhc_runtime_resume(struct device *dev)
1218 {
1219         struct sdhci_host *host = dev_get_drvdata(dev);
1220         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1221         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1222
1223         if (!sdhci_sdio_irq_enabled(host)) {
1224                 clk_prepare_enable(imx_data->clk_per);
1225                 clk_prepare_enable(imx_data->clk_ipg);
1226         }
1227         clk_prepare_enable(imx_data->clk_ahb);
1228
1229         return sdhci_runtime_resume_host(host);
1230 }
1231 #endif
1232
1233 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1234         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1235         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1236                                 sdhci_esdhc_runtime_resume, NULL)
1237 };
1238
1239 static struct platform_driver sdhci_esdhc_imx_driver = {
1240         .driver         = {
1241                 .name   = "sdhci-esdhc-imx",
1242                 .owner  = THIS_MODULE,
1243                 .of_match_table = imx_esdhc_dt_ids,
1244                 .pm     = &sdhci_esdhc_pmops,
1245         },
1246         .id_table       = imx_esdhc_devtype,
1247         .probe          = sdhci_esdhc_imx_probe,
1248         .remove         = sdhci_esdhc_imx_remove,
1249 };
1250
1251 module_platform_driver(sdhci_esdhc_imx_driver);
1252
1253 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1254 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1255 MODULE_LICENSE("GPL v2");