drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include <linux/pm_runtime.h>
  31 #include "sdhci-pltfm.h"
  32 #include "sdhci-esdhc.h"
  33
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 /* VENDOR SPEC register */
  36 #define ESDHC_VENDOR_SPEC               0xc0
  37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  40 #define ESDHC_WTMK_LVL                  0x44
  41 #define ESDHC_MIX_CTRL                  0x48
  42 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  43 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  44 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  45 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  46 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  47 /* Bits 3 and 6 are not SDHCI standard definitions */
  48 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  49 /* Tuning bits */
  50 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  51
  52 /* dll control register */
  53 #define ESDHC_DLL_CTRL                  0x60
  54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  56
  57 /* dll control register */
  58 #define ESDHC_DLL_CTRL                  0x60
  59 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  60 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  61
  62 /* tune control register */
  63 #define ESDHC_TUNE_CTRL_STATUS          0x68
  64 #define  ESDHC_TUNE_CTRL_STEP           1
  65 #define  ESDHC_TUNE_CTRL_MIN            0
  66 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  67
  68 #define ESDHC_TUNING_CTRL               0xcc
  69 #define ESDHC_STD_TUNING_EN             (1 << 24)
  70 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  71 #define ESDHC_TUNING_START_TAP          0x1
  72
  73 #define ESDHC_TUNING_BLOCK_PATTERN_LEN  64
  74
  75 /* pinctrl state */
  76 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  77 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  78
  79 /*
  80  * Our interpretation of the SDHCI_HOST_CONTROL register
  81  */
  82 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  83 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  84 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  85
  86 /*
  87  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  88  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  89  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  90  * Define this macro DMA error INT for fsl eSDHC
  91  */
  92 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  93
  94 /*
  95  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  96  * "11" when the STOP CMD12 is issued on imx53 to abort one
  97  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  98  * be generated.
  99  * In exact block transfer, the controller doesn't complete the
 100  * operations automatically as required at the end of the
 101  * transfer and remains on hold if the abort command is not sent.
 102  * As a result, the TC flag is not asserted and SW  received timeout
 103  * exeception. Bit1 of Vendor Spec registor is used to fix it.
 104  */
 105 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 106 /*
 107  * The flag enables the workaround for ESDHC errata ENGcm07207 which
 108  * affects i.MX25 and i.MX35.
 109  */
 110 #define ESDHC_FLAG_ENGCM07207           BIT(2)
 111 /*
 112  * The flag tells that the ESDHC controller is an USDHC block that is
 113  * integrated on the i.MX6 series.
 114  */
 115 #define ESDHC_FLAG_USDHC                BIT(3)
 116 /* The IP supports manual tuning process */
 117 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 118 /* The IP supports standard tuning process */
 119 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 120 /* The IP has SDHCI_CAPABILITIES_1 register */
 121 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 122
 123 struct esdhc_soc_data {
 124         u32 flags;
 125 };
 126
 127 static struct esdhc_soc_data esdhc_imx25_data = {
 128         .flags = ESDHC_FLAG_ENGCM07207,
 129 };
 130
 131 static struct esdhc_soc_data esdhc_imx35_data = {
 132         .flags = ESDHC_FLAG_ENGCM07207,
 133 };
 134
 135 static struct esdhc_soc_data esdhc_imx51_data = {
 136         .flags = 0,
 137 };
 138
 139 static struct esdhc_soc_data esdhc_imx53_data = {
 140         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 141 };
 142
 143 static struct esdhc_soc_data usdhc_imx6q_data = {
 144         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 145 };
 146
 147 static struct esdhc_soc_data usdhc_imx6sl_data = {
 148         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 149                         | ESDHC_FLAG_HAVE_CAP1,
 150 };
 151
 152 struct pltfm_imx_data {
 153         u32 scratchpad;
 154         struct pinctrl *pinctrl;
 155         struct pinctrl_state *pins_default;
 156         struct pinctrl_state *pins_100mhz;
 157         struct pinctrl_state *pins_200mhz;
 158         const struct esdhc_soc_data *socdata;
 159         struct esdhc_platform_data boarddata;
 160         struct clk *clk_ipg;
 161         struct clk *clk_ahb;
 162         struct clk *clk_per;
 163         enum {
 164                 NO_CMD_PENDING,      /* no multiblock command pending*/
 165                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 166                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 167         } multiblock_status;
 168         u32 is_ddr;
 169 };
 170
 171 static struct platform_device_id imx_esdhc_devtype[] = {
 172         {
 173                 .name = "sdhci-esdhc-imx25",
 174                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 175         }, {
 176                 .name = "sdhci-esdhc-imx35",
 177                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 178         }, {
 179                 .name = "sdhci-esdhc-imx51",
 180                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 181         }, {
 182                 /* sentinel */
 183         }
 184 };
 185 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 186
 187 static const struct of_device_id imx_esdhc_dt_ids[] = {
 188         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 189         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 190         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 191         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 192         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 193         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 194         { /* sentinel */ }
 195 };
 196 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 197
 198 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 199 {
 200         return data->socdata == &esdhc_imx25_data;
 201 }
 202
 203 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 204 {
 205         return data->socdata == &esdhc_imx53_data;
 206 }
 207
 208 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 209 {
 210         return data->socdata == &usdhc_imx6q_data;
 211 }
 212
 213 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 214 {
 215         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 216 }
 217
 218 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 219 {
 220         void __iomem *base = host->ioaddr + (reg & ~0x3);
 221         u32 shift = (reg & 0x3) * 8;
 222
 223         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 224 }
 225
 226 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 227 {
 228         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 229         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 230         u32 val = readl(host->ioaddr + reg);
 231
 232         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 233                 u32 fsl_prss = val;
 234                 /* save the least 20 bits */
 235                 val = fsl_prss & 0x000FFFFF;
 236                 /* move dat[0-3] bits */
 237                 val |= (fsl_prss & 0x0F000000) >> 4;
 238                 /* move cmd line bit */
 239                 val |= (fsl_prss & 0x00800000) << 1;
 240         }
 241
 242         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 243                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 244                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 245                         val &= 0xffff0000;
 246
 247                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 248                  * ADMA2 capability of esdhc, but this bit is messed up on
 249                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 250                  * don't actually support ADMA2). So set the BROKEN_ADMA
 251                  * uirk on MX25/35 platforms.
 252                  */
 253
 254                 if (val & SDHCI_CAN_DO_ADMA1) {
 255                         val &= ~SDHCI_CAN_DO_ADMA1;
 256                         val |= SDHCI_CAN_DO_ADMA2;
 257                 }
 258         }
 259
 260         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 261                 if (esdhc_is_usdhc(imx_data)) {
 262                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 263                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 264                         else
 265                                 /* imx6q/dl does not have cap_1 register, fake one */
 266                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 267                                         | SDHCI_SUPPORT_SDR50
 268                                         | SDHCI_USE_SDR50_TUNING;
 269                 }
 270         }
 271
 272         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 273                 val = 0;
 274                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 275                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 276                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 277         }
 278
 279         if (unlikely(reg == SDHCI_INT_STATUS)) {
 280                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 281                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 282                         val |= SDHCI_INT_ADMA_ERROR;
 283                 }
 284
 285                 /*
 286                  * mask off the interrupt we get in response to the manually
 287                  * sent CMD12
 288                  */
 289                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 290                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 291                         val &= ~SDHCI_INT_RESPONSE;
 292                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 293                                                    SDHCI_INT_STATUS);
 294                         imx_data->multiblock_status = NO_CMD_PENDING;
 295                 }
 296         }
 297
 298         return val;
 299 }
 300
 301 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 302 {
 303         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 304         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 305         u32 data;
 306
 307         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 308                 if (val & SDHCI_INT_CARD_INT) {
 309                         /*
 310                          * Clear and then set D3CD bit to avoid missing the
 311                          * card interrupt.  This is a eSDHC controller problem
 312                          * so we need to apply the following workaround: clear
 313                          * and set D3CD bit will make eSDHC re-sample the card
 314                          * interrupt. In case a card interrupt was lost,
 315                          * re-sample it by the following steps.
 316                          */
 317                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 318                         data &= ~ESDHC_CTRL_D3CD;
 319                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 320                         data |= ESDHC_CTRL_D3CD;
 321                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 322                 }
 323         }
 324
 325         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 326                                 && (reg == SDHCI_INT_STATUS)
 327                                 && (val & SDHCI_INT_DATA_END))) {
 328                         u32 v;
 329                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 330                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 331                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 332
 333                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 334                         {
 335                                 /* send a manual CMD12 with RESPTYP=none */
 336                                 data = MMC_STOP_TRANSMISSION << 24 |
 337                                        SDHCI_CMD_ABORTCMD << 16;
 338                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 339                                 imx_data->multiblock_status = WAIT_FOR_INT;
 340                         }
 341         }
 342
 343         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 344                 if (val & SDHCI_INT_ADMA_ERROR) {
 345                         val &= ~SDHCI_INT_ADMA_ERROR;
 346                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 347                 }
 348         }
 349
 350         writel(val, host->ioaddr + reg);
 351 }
 352
 353 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 354 {
 355         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 356         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 357         u16 ret = 0;
 358         u32 val;
 359
 360         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 361                 reg ^= 2;
 362                 if (esdhc_is_usdhc(imx_data)) {
 363                         /*
 364                          * The usdhc register returns a wrong host version.
 365                          * Correct it here.
 366                          */
 367                         return SDHCI_SPEC_300;
 368                 }
 369         }
 370
 371         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 372                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 373                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 374                         ret |= SDHCI_CTRL_VDD_180;
 375
 376                 if (esdhc_is_usdhc(imx_data)) {
 377                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 378                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 379                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 380                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 381                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 382                 }
 383
 384                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 385                         ret |= SDHCI_CTRL_EXEC_TUNING;
 386                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 387                         ret |= SDHCI_CTRL_TUNED_CLK;
 388
 389                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 390
 391                 return ret;
 392         }
 393
 394         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 395                 if (esdhc_is_usdhc(imx_data)) {
 396                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 397                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 398                         /* Swap AC23 bit */
 399                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 400                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 401                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 402                         }
 403                 } else {
 404                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 405                 }
 406
 407                 return ret;
 408         }
 409
 410         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 411                 if (esdhc_is_usdhc(imx_data)) {
 412                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 413                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 414                         /* Swap AC23 bit */
 415                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 416                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 417                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 418                         }
 419                 } else {
 420                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 421                 }
 422
 423                 return ret;
 424         }
 425
 426         return readw(host->ioaddr + reg);
 427 }
 428
 429 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 430 {
 431         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 432         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 433         u32 new_val = 0;
 434
 435         switch (reg) {
 436         case SDHCI_CLOCK_CONTROL:
 437                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 438                 if (val & SDHCI_CLOCK_CARD_EN)
 439                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 440                 else
 441                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 442                         writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 443                 return;
 444         case SDHCI_HOST_CONTROL2:
 445                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 446                 if (val & SDHCI_CTRL_VDD_180)
 447                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 448                 else
 449                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 450                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 451                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 452                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 453                         if (val & SDHCI_CTRL_TUNED_CLK)
 454                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 455                         else
 456                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 457                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 458                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 459                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 460                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 461                         if (val & SDHCI_CTRL_TUNED_CLK) {
 462                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 463                         } else {
 464                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 465                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 466                         }
 467
 468                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 469                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 470                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 471                         } else {
 472                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 473                         }
 474
 475                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 476                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 477                 }
 478                 return;
 479         case SDHCI_TRANSFER_MODE:
 480                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 481                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 482                                 && (host->cmd->data->blocks > 1)
 483                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 484                         u32 v;
 485                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 486                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 487                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 488                 }
 489
 490                 if (esdhc_is_usdhc(imx_data)) {
 491                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 492                         /* Swap AC23 bit */
 493                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 494                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 495                                 val |= ESDHC_MIX_CTRL_AC23EN;
 496                         }
 497                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 498                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 499                 } else {
 500                         /*
 501                          * Postpone this write, we must do it together with a
 502                          * command write that is down below.
 503                          */
 504                         imx_data->scratchpad = val;
 505                 }
 506                 return;
 507         case SDHCI_COMMAND:
 508                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 509                         val |= SDHCI_CMD_ABORTCMD;
 510
 511                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 512                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 513                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 514
 515                 if (esdhc_is_usdhc(imx_data))
 516                         writel(val << 16,
 517                                host->ioaddr + SDHCI_TRANSFER_MODE);
 518                 else
 519                         writel(val << 16 | imx_data->scratchpad,
 520                                host->ioaddr + SDHCI_TRANSFER_MODE);
 521                 return;
 522         case SDHCI_BLOCK_SIZE:
 523                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 524                 break;
 525         }
 526         esdhc_clrset_le(host, 0xffff, val, reg);
 527 }
 528
 529 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 530 {
 531         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 532         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 533         u32 new_val;
 534         u32 mask;
 535
 536         switch (reg) {
 537         case SDHCI_POWER_CONTROL:
 538                 /*
 539                  * FSL put some DMA bits here
 540                  * If your board has a regulator, code should be here
 541                  */
 542                 return;
 543         case SDHCI_HOST_CONTROL:
 544                 /* FSL messed up here, so we need to manually compose it. */
 545                 new_val = val & SDHCI_CTRL_LED;
 546                 /* ensure the endianness */
 547                 new_val |= ESDHC_HOST_CONTROL_LE;
 548                 /* bits 8&9 are reserved on mx25 */
 549                 if (!is_imx25_esdhc(imx_data)) {
 550                         /* DMA mode bits are shifted */
 551                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 552                 }
 553
 554                 /*
 555                  * Do not touch buswidth bits here. This is done in
 556                  * esdhc_pltfm_bus_width.
 557                  * Do not touch the D3CD bit either which is used for the
 558                  * SDIO interrupt errata workaround.
 559                  */
 560                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 561
 562                 esdhc_clrset_le(host, mask, new_val, reg);
 563                 return;
 564         }
 565         esdhc_clrset_le(host, 0xff, val, reg);
 566
 567         /*
 568          * The esdhc has a design violation to SDHC spec which tells
 569          * that software reset should not affect card detection circuit.
 570          * But esdhc clears its SYSCTL register bits [0..2] during the
 571          * software reset.  This will stop those clocks that card detection
 572          * circuit relies on.  To work around it, we turn the clocks on back
 573          * to keep card detection circuit functional.
 574          */
 575         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 576                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 577                 /*
 578                  * The reset on usdhc fails to clear MIX_CTRL register.
 579                  * Do it manually here.
 580                  */
 581                 if (esdhc_is_usdhc(imx_data)) {
 582                         /* the tuning bits should be kept during reset */
 583                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 584                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 585                                         host->ioaddr + ESDHC_MIX_CTRL);
 586                         imx_data->is_ddr = 0;
 587                 }
 588         }
 589 }
 590
 591 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 592 {
 593         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 594         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 595         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 596
 597         if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
 598                 return boarddata->f_max;
 599         else
 600                 return pltfm_host->clock;
 601 }
 602
 603 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 604 {
 605         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 606
 607         return pltfm_host->clock / 256 / 16;
 608 }
 609
 610 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 611                                          unsigned int clock)
 612 {
 613         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 614         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 615         unsigned int host_clock = pltfm_host->clock;
 616         int pre_div = 2;
 617         int div = 1;
 618         u32 temp, val;
 619
 620         if (clock == 0) {
 621                 host->mmc->actual_clock = 0;
 622
 623                 if (esdhc_is_usdhc(imx_data)) {
 624                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 625                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 626                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 627                 }
 628                 return;
 629         }
 630
 631         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
 632                 pre_div = 1;
 633
 634         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 635         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 636                 | ESDHC_CLOCK_MASK);
 637         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 638
 639         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 640                 pre_div *= 2;
 641
 642         while (host_clock / pre_div / div > clock && div < 16)
 643                 div++;
 644
 645         host->mmc->actual_clock = host_clock / pre_div / div;
 646         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 647                 clock, host->mmc->actual_clock);
 648
 649         if (imx_data->is_ddr)
 650                 pre_div >>= 2;
 651         else
 652                 pre_div >>= 1;
 653         div--;
 654
 655         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 656         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 657                 | (div << ESDHC_DIVIDER_SHIFT)
 658                 | (pre_div << ESDHC_PREDIV_SHIFT));
 659         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 660
 661         if (esdhc_is_usdhc(imx_data)) {
 662                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 663                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 664                 host->ioaddr + ESDHC_VENDOR_SPEC);
 665         }
 666
 667         mdelay(1);
 668 }
 669
 670 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 671 {
 672         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 673         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 674         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 675
 676         switch (boarddata->wp_type) {
 677         case ESDHC_WP_GPIO:
 678                 return mmc_gpio_get_ro(host->mmc);
 679         case ESDHC_WP_CONTROLLER:
 680                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 681                                SDHCI_WRITE_PROTECT);
 682         case ESDHC_WP_NONE:
 683                 break;
 684         }
 685
 686         return -ENOSYS;
 687 }
 688
 689 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 690 {
 691         u32 ctrl;
 692
 693         switch (width) {
 694         case MMC_BUS_WIDTH_8:
 695                 ctrl = ESDHC_CTRL_8BITBUS;
 696                 break;
 697         case MMC_BUS_WIDTH_4:
 698                 ctrl = ESDHC_CTRL_4BITBUS;
 699                 break;
 700         default:
 701                 ctrl = 0;
 702                 break;
 703         }
 704
 705         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 706                         SDHCI_HOST_CONTROL);
 707 }
 708
 709 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 710 {
 711         u32 reg;
 712
 713         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 714         mdelay(1);
 715
 716         /* This is balanced by the runtime put in sdhci_tasklet_finish */
 717         pm_runtime_get_sync(host->mmc->parent);
 718         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 719         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 720                         ESDHC_MIX_CTRL_FBCLK_SEL;
 721         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 722         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 723         dev_dbg(mmc_dev(host->mmc),
 724                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 725                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 726 }
 727
 728 static void esdhc_request_done(struct mmc_request *mrq)
 729 {
 730         complete(&mrq->completion);
 731 }
 732
 733 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
 734                                  struct scatterlist *sg)
 735 {
 736         struct mmc_command cmd = {0};
 737         struct mmc_request mrq = {NULL};
 738         struct mmc_data data = {0};
 739
 740         cmd.opcode = opcode;
 741         cmd.arg = 0;
 742         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 743
 744         data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
 745         data.blocks = 1;
 746         data.flags = MMC_DATA_READ;
 747         data.sg = sg;
 748         data.sg_len = 1;
 749
 750         mrq.cmd = &cmd;
 751         mrq.cmd->mrq = &mrq;
 752         mrq.data = &data;
 753         mrq.data->mrq = &mrq;
 754         mrq.cmd->data = mrq.data;
 755
 756         mrq.done = esdhc_request_done;
 757         init_completion(&(mrq.completion));
 758
 759         spin_lock_irq(&host->lock);
 760         host->mrq = &mrq;
 761
 762         sdhci_send_command(host, mrq.cmd);
 763
 764         spin_unlock_irq(&host->lock);
 765
 766         wait_for_completion(&mrq.completion);
 767
 768         if (cmd.error)
 769                 return cmd.error;
 770         if (data.error)
 771                 return data.error;
 772
 773         return 0;
 774 }
 775
 776 static void esdhc_post_tuning(struct sdhci_host *host)
 777 {
 778         u32 reg;
 779
 780         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 781         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 782         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 783 }
 784
 785 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 786 {
 787         struct scatterlist sg;
 788         char *tuning_pattern;
 789         int min, max, avg, ret;
 790
 791         tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
 792         if (!tuning_pattern)
 793                 return -ENOMEM;
 794
 795         sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
 796
 797         /* find the mininum delay first which can pass tuning */
 798         min = ESDHC_TUNE_CTRL_MIN;
 799         while (min < ESDHC_TUNE_CTRL_MAX) {
 800                 esdhc_prepare_tuning(host, min);
 801                 if (!esdhc_send_tuning_cmd(host, opcode, &sg))
 802                         break;
 803                 min += ESDHC_TUNE_CTRL_STEP;
 804         }
 805
 806         /* find the maxinum delay which can not pass tuning */
 807         max = min + ESDHC_TUNE_CTRL_STEP;
 808         while (max < ESDHC_TUNE_CTRL_MAX) {
 809                 esdhc_prepare_tuning(host, max);
 810                 if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
 811                         max -= ESDHC_TUNE_CTRL_STEP;
 812                         break;
 813                 }
 814                 max += ESDHC_TUNE_CTRL_STEP;
 815         }
 816
 817         /* use average delay to get the best timing */
 818         avg = (min + max) / 2;
 819         esdhc_prepare_tuning(host, avg);
 820         ret = esdhc_send_tuning_cmd(host, opcode, &sg);
 821         esdhc_post_tuning(host);
 822
 823         kfree(tuning_pattern);
 824
 825         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 826                 ret ? "failed" : "passed", avg, ret);
 827
 828         return ret;
 829 }
 830
 831 static int esdhc_change_pinstate(struct sdhci_host *host,
 832                                                 unsigned int uhs)
 833 {
 834         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 835         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 836         struct pinctrl_state *pinctrl;
 837
 838         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 839
 840         if (IS_ERR(imx_data->pinctrl) ||
 841                 IS_ERR(imx_data->pins_default) ||
 842                 IS_ERR(imx_data->pins_100mhz) ||
 843                 IS_ERR(imx_data->pins_200mhz))
 844                 return -EINVAL;
 845
 846         switch (uhs) {
 847         case MMC_TIMING_UHS_SDR50:
 848                 pinctrl = imx_data->pins_100mhz;
 849                 break;
 850         case MMC_TIMING_UHS_SDR104:
 851         case MMC_TIMING_MMC_HS200:
 852                 pinctrl = imx_data->pins_200mhz;
 853                 break;
 854         default:
 855                 /* back to default state for other legacy timing */
 856                 pinctrl = imx_data->pins_default;
 857         }
 858
 859         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 860 }
 861
 862 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 863 {
 864         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 865         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 866         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 867
 868         switch (timing) {
 869         case MMC_TIMING_UHS_SDR12:
 870         case MMC_TIMING_UHS_SDR25:
 871         case MMC_TIMING_UHS_SDR50:
 872         case MMC_TIMING_UHS_SDR104:
 873         case MMC_TIMING_MMC_HS200:
 874                 break;
 875         case MMC_TIMING_UHS_DDR50:
 876         case MMC_TIMING_MMC_DDR52:
 877                 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
 878                                 ESDHC_MIX_CTRL_DDREN,
 879                                 host->ioaddr + ESDHC_MIX_CTRL);
 880                 imx_data->is_ddr = 1;
 881                 if (boarddata->delay_line) {
 882                         u32 v;
 883                         v = boarddata->delay_line <<
 884                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 885                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 886                         if (is_imx53_esdhc(imx_data))
 887                                 v <<= 1;
 888                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 889                 }
 890                 break;
 891         }
 892
 893         esdhc_change_pinstate(host, timing);
 894 }
 895
 896 static void esdhc_reset(struct sdhci_host *host, u8 mask)
 897 {
 898         sdhci_reset(host, mask);
 899
 900         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 901         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 902 }
 903
 904 static struct sdhci_ops sdhci_esdhc_ops = {
 905         .read_l = esdhc_readl_le,
 906         .read_w = esdhc_readw_le,
 907         .write_l = esdhc_writel_le,
 908         .write_w = esdhc_writew_le,
 909         .write_b = esdhc_writeb_le,
 910         .set_clock = esdhc_pltfm_set_clock,
 911         .get_max_clock = esdhc_pltfm_get_max_clock,
 912         .get_min_clock = esdhc_pltfm_get_min_clock,
 913         .get_ro = esdhc_pltfm_get_ro,
 914         .set_bus_width = esdhc_pltfm_set_bus_width,
 915         .set_uhs_signaling = esdhc_set_uhs_signaling,
 916         .reset = esdhc_reset,
 917 };
 918
 919 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 920         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 921                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 922                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 923                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 924         .ops = &sdhci_esdhc_ops,
 925 };
 926
 927 #ifdef CONFIG_OF
 928 static int
 929 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 930                          struct esdhc_platform_data *boarddata)
 931 {
 932         struct device_node *np = pdev->dev.of_node;
 933
 934         if (!np)
 935                 return -ENODEV;
 936
 937         if (of_get_property(np, "non-removable", NULL))
 938                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 939
 940         if (of_get_property(np, "fsl,cd-controller", NULL))
 941                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 942
 943         if (of_get_property(np, "fsl,wp-controller", NULL))
 944                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 945
 946         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 947         if (gpio_is_valid(boarddata->cd_gpio))
 948                 boarddata->cd_type = ESDHC_CD_GPIO;
 949
 950         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 951         if (gpio_is_valid(boarddata->wp_gpio))
 952                 boarddata->wp_type = ESDHC_WP_GPIO;
 953
 954         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 955
 956         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 957
 958         if (of_find_property(np, "no-1-8-v", NULL))
 959                 boarddata->support_vsel = false;
 960         else
 961                 boarddata->support_vsel = true;
 962
 963         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 964                 boarddata->delay_line = 0;
 965
 966         return 0;
 967 }
 968 #else
 969 static inline int
 970 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 971                          struct esdhc_platform_data *boarddata)
 972 {
 973         return -ENODEV;
 974 }
 975 #endif
 976
 977 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 978 {
 979         const struct of_device_id *of_id =
 980                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 981         struct sdhci_pltfm_host *pltfm_host;
 982         struct sdhci_host *host;
 983         struct esdhc_platform_data *boarddata;
 984         int err;
 985         struct pltfm_imx_data *imx_data;
 986
 987         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 988         if (IS_ERR(host))
 989                 return PTR_ERR(host);
 990
 991         pltfm_host = sdhci_priv(host);
 992
 993         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 994         if (!imx_data) {
 995                 err = -ENOMEM;
 996                 goto free_sdhci;
 997         }
 998
 999         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1000                                                   pdev->id_entry->driver_data;
1001         pltfm_host->priv = imx_data;
1002
1003         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1004         if (IS_ERR(imx_data->clk_ipg)) {
1005                 err = PTR_ERR(imx_data->clk_ipg);
1006                 goto free_sdhci;
1007         }
1008
1009         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1010         if (IS_ERR(imx_data->clk_ahb)) {
1011                 err = PTR_ERR(imx_data->clk_ahb);
1012                 goto free_sdhci;
1013         }
1014
1015         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1016         if (IS_ERR(imx_data->clk_per)) {
1017                 err = PTR_ERR(imx_data->clk_per);
1018                 goto free_sdhci;
1019         }
1020
1021         pltfm_host->clk = imx_data->clk_per;
1022         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1023         clk_prepare_enable(imx_data->clk_per);
1024         clk_prepare_enable(imx_data->clk_ipg);
1025         clk_prepare_enable(imx_data->clk_ahb);
1026
1027         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1028         if (IS_ERR(imx_data->pinctrl)) {
1029                 err = PTR_ERR(imx_data->pinctrl);
1030                 goto disable_clk;
1031         }
1032
1033         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1034                                                 PINCTRL_STATE_DEFAULT);
1035         if (IS_ERR(imx_data->pins_default)) {
1036                 err = PTR_ERR(imx_data->pins_default);
1037                 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1038                 goto disable_clk;
1039         }
1040
1041         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1042
1043         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1044                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1045                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1046                         | SDHCI_QUIRK_BROKEN_ADMA;
1047
1048         /*
1049          * The imx6q ROM code will change the default watermark level setting
1050          * to something insane.  Change it back here.
1051          */
1052         if (esdhc_is_usdhc(imx_data)) {
1053                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1054                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1055                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1056         }
1057
1058         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1059                 sdhci_esdhc_ops.platform_execute_tuning =
1060                                         esdhc_executing_tuning;
1061
1062         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1063                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1064                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1065                         host->ioaddr + ESDHC_TUNING_CTRL);
1066
1067         boarddata = &imx_data->boarddata;
1068         if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1069                 if (!host->mmc->parent->platform_data) {
1070                         dev_err(mmc_dev(host->mmc), "no board data!\n");
1071                         err = -EINVAL;
1072                         goto disable_clk;
1073                 }
1074                 imx_data->boarddata = *((struct esdhc_platform_data *)
1075                                         host->mmc->parent->platform_data);
1076         }
1077
1078         /* write_protect */
1079         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1080                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1081                 if (err) {
1082                         dev_err(mmc_dev(host->mmc),
1083                                 "failed to request write-protect gpio!\n");
1084                         goto disable_clk;
1085                 }
1086                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1087         }
1088
1089         /* card_detect */
1090         switch (boarddata->cd_type) {
1091         case ESDHC_CD_GPIO:
1092                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1093                 if (err) {
1094                         dev_err(mmc_dev(host->mmc),
1095                                 "failed to request card-detect gpio!\n");
1096                         goto disable_clk;
1097                 }
1098                 /* fall through */
1099
1100         case ESDHC_CD_CONTROLLER:
1101                 /* we have a working card_detect back */
1102                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1103                 break;
1104
1105         case ESDHC_CD_PERMANENT:
1106                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1107                 break;
1108
1109         case ESDHC_CD_NONE:
1110                 break;
1111         }
1112
1113         switch (boarddata->max_bus_width) {
1114         case 8:
1115                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1116                 break;
1117         case 4:
1118                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1119                 break;
1120         case 1:
1121         default:
1122                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1123                 break;
1124         }
1125
1126         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1127         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
1128                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1129                                                 ESDHC_PINCTRL_STATE_100MHZ);
1130                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1131                                                 ESDHC_PINCTRL_STATE_200MHZ);
1132                 if (IS_ERR(imx_data->pins_100mhz) ||
1133                                 IS_ERR(imx_data->pins_200mhz)) {
1134                         dev_warn(mmc_dev(host->mmc),
1135                                 "could not get ultra high speed state, work on normal mode\n");
1136                         /* fall back to not support uhs by specify no 1.8v quirk */
1137                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1138                 }
1139         } else {
1140                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1141         }
1142
1143         err = sdhci_add_host(host);
1144         if (err)
1145                 goto disable_clk;
1146
1147         pm_runtime_set_active(&pdev->dev);
1148         pm_runtime_enable(&pdev->dev);
1149         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1150         pm_runtime_use_autosuspend(&pdev->dev);
1151         pm_suspend_ignore_children(&pdev->dev, 1);
1152
1153         return 0;
1154
1155 disable_clk:
1156         clk_disable_unprepare(imx_data->clk_per);
1157         clk_disable_unprepare(imx_data->clk_ipg);
1158         clk_disable_unprepare(imx_data->clk_ahb);
1159 free_sdhci:
1160         sdhci_pltfm_free(pdev);
1161         return err;
1162 }
1163
1164 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1165 {
1166         struct sdhci_host *host = platform_get_drvdata(pdev);
1167         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1168         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1169         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1170
1171         sdhci_remove_host(host, dead);
1172
1173         pm_runtime_dont_use_autosuspend(&pdev->dev);
1174         pm_runtime_disable(&pdev->dev);
1175
1176         if (!IS_ENABLED(CONFIG_PM_RUNTIME)) {
1177                 clk_disable_unprepare(imx_data->clk_per);
1178                 clk_disable_unprepare(imx_data->clk_ipg);
1179                 clk_disable_unprepare(imx_data->clk_ahb);
1180         }
1181
1182         sdhci_pltfm_free(pdev);
1183
1184         return 0;
1185 }
1186
1187 #ifdef CONFIG_PM_RUNTIME
1188 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1189 {
1190         struct sdhci_host *host = dev_get_drvdata(dev);
1191         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1192         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1193         int ret;
1194
1195         ret = sdhci_runtime_suspend_host(host);
1196
1197         if (!sdhci_sdio_irq_enabled(host)) {
1198                 clk_disable_unprepare(imx_data->clk_per);
1199                 clk_disable_unprepare(imx_data->clk_ipg);
1200         }
1201         clk_disable_unprepare(imx_data->clk_ahb);
1202
1203         return ret;
1204 }
1205
1206 static int sdhci_esdhc_runtime_resume(struct device *dev)
1207 {
1208         struct sdhci_host *host = dev_get_drvdata(dev);
1209         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1210         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1211
1212         if (!sdhci_sdio_irq_enabled(host)) {
1213                 clk_prepare_enable(imx_data->clk_per);
1214                 clk_prepare_enable(imx_data->clk_ipg);
1215         }
1216         clk_prepare_enable(imx_data->clk_ahb);
1217
1218         return sdhci_runtime_resume_host(host);
1219 }
1220 #endif
1221
1222 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1223         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1224         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1225                                 sdhci_esdhc_runtime_resume, NULL)
1226 };
1227
1228 static struct platform_driver sdhci_esdhc_imx_driver = {
1229         .driver         = {
1230                 .name   = "sdhci-esdhc-imx",
1231                 .owner  = THIS_MODULE,
1232                 .of_match_table = imx_esdhc_dt_ids,
1233                 .pm     = &sdhci_esdhc_pmops,
1234         },
1235         .id_table       = imx_esdhc_devtype,
1236         .probe          = sdhci_esdhc_imx_probe,
1237         .remove         = sdhci_esdhc_imx_remove,
1238 };
1239
1240 module_platform_driver(sdhci_esdhc_imx_driver);
1241
1242 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1243 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1244 MODULE_LICENSE("GPL v2");