drivers/mmc/host/sdhci-msm.c

   1 /*
   2  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   3  *
   4  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/delay.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/iopoll.h>
  24
  25 #include "sdhci-pltfm.h"
  26
  27 #define CORE_MCI_VERSION                0x50
  28 #define CORE_VERSION_MAJOR_SHIFT        28
  29 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  30 #define CORE_VERSION_MINOR_MASK         0xff
  31
  32 #define CORE_HC_MODE            0x78
  33 #define HC_MODE_EN              0x1
  34 #define CORE_POWER              0x0
  35 #define CORE_SW_RST             BIT(7)
  36 #define FF_CLK_SW_RST_DIS       BIT(13)
  37
  38 #define CORE_PWRCTL_STATUS      0xdc
  39 #define CORE_PWRCTL_MASK        0xe0
  40 #define CORE_PWRCTL_CLEAR       0xe4
  41 #define CORE_PWRCTL_CTL         0xe8
  42 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  43 #define CORE_PWRCTL_BUS_ON      BIT(1)
  44 #define CORE_PWRCTL_IO_LOW      BIT(2)
  45 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  46 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  47 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  48 #define REQ_BUS_OFF             BIT(0)
  49 #define REQ_BUS_ON              BIT(1)
  50 #define REQ_IO_LOW              BIT(2)
  51 #define REQ_IO_HIGH             BIT(3)
  52 #define INT_MASK                0xf
  53 #define MAX_PHASES              16
  54 #define CORE_DLL_LOCK           BIT(7)
  55 #define CORE_DDR_DLL_LOCK       BIT(11)
  56 #define CORE_DLL_EN             BIT(16)
  57 #define CORE_CDR_EN             BIT(17)
  58 #define CORE_CK_OUT_EN          BIT(18)
  59 #define CORE_CDR_EXT_EN         BIT(19)
  60 #define CORE_DLL_PDN            BIT(29)
  61 #define CORE_DLL_RST            BIT(30)
  62 #define CORE_DLL_CONFIG         0x100
  63 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  64 #define CORE_DLL_STATUS         0x108
  65
  66 #define CORE_DLL_CONFIG_2       0x1b4
  67 #define CORE_DDR_CAL_EN         BIT(0)
  68 #define CORE_FLL_CYCLE_CNT      BIT(18)
  69 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  70
  71 #define CORE_VENDOR_SPEC        0x10c
  72 #define CORE_VENDOR_SPEC_POR_VAL        0xa1c
  73 #define CORE_CLK_PWRSAVE        BIT(1)
  74 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  75 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  76 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  77 #define CORE_HC_SELECT_IN_EN    BIT(18)
  78 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  79 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  80
  81 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  82 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  83 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  84
  85 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  86 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  87 #define CORE_TIMER_ENA                  BIT(16)
  88
  89 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  90 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  91 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  92 #define CORE_CDC_OFFSET_CFG             0x14C
  93 #define CORE_CSR_CDC_DELAY_CFG          0x150
  94 #define CORE_CDC_SLAVE_DDA_CFG          0x160
  95 #define CORE_CSR_CDC_STATUS0            0x164
  96 #define CORE_CALIBRATION_DONE           BIT(0)
  97
  98 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
  99
 100 #define CORE_CSR_CDC_GEN_CFG            0x178
 101 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 102 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 103
 104 #define CORE_DDR_200_CFG                0x184
 105 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 106 #define CORE_CMDIN_RCLK_EN              BIT(1)
 107 #define CORE_START_CDC_TRAFFIC          BIT(6)
 108 #define CORE_VENDOR_SPEC3       0x1b0
 109 #define CORE_PWRSAVE_DLL        BIT(3)
 110
 111 #define CORE_DDR_CONFIG         0x1b8
 112 #define DDR_CONFIG_POR_VAL      0x80040853
 113
 114 #define CORE_VENDOR_SPEC_CAPABILITIES0  0x11c
 115
 116 #define INVALID_TUNING_PHASE    -1
 117 #define SDHCI_MSM_MIN_CLOCK     400000
 118 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 119
 120 #define CDR_SELEXT_SHIFT        20
 121 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 122 #define CMUX_SHIFT_PHASE_SHIFT  24
 123 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 124
 125 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 126 struct sdhci_msm_host {
 127         struct platform_device *pdev;
 128         void __iomem *core_mem; /* MSM SDCC mapped address */
 129         int pwr_irq;            /* power irq */
 130         struct clk *clk;        /* main SD/MMC bus clock */
 131         struct clk *pclk;       /* SDHC peripheral bus clock */
 132         struct clk *bus_clk;    /* SDHC bus voter clock */
 133         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 134         unsigned long clk_rate;
 135         struct mmc_host *mmc;
 136         bool use_14lpp_dll_reset;
 137         bool tuning_done;
 138         bool calibration_done;
 139         u8 saved_tuning_phase;
 140         bool use_cdclp533;
 141 };
 142
 143 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 144                                                     unsigned int clock)
 145 {
 146         struct mmc_ios ios = host->mmc->ios;
 147         /*
 148          * The SDHC requires internal clock frequency to be double the
 149          * actual clock that will be set for DDR mode. The controller
 150          * uses the faster clock(100/400MHz) for some of its parts and
 151          * send the actual required clock (50/200MHz) to the card.
 152          */
 153         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 154             ios.timing == MMC_TIMING_MMC_DDR52 ||
 155             ios.timing == MMC_TIMING_MMC_HS400 ||
 156             host->flags & SDHCI_HS400_TUNING)
 157                 clock *= 2;
 158         return clock;
 159 }
 160
 161 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 162                                             unsigned int clock)
 163 {
 164         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 165         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 166         struct mmc_ios curr_ios = host->mmc->ios;
 167         int rc;
 168
 169         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 170         rc = clk_set_rate(msm_host->clk, clock);
 171         if (rc) {
 172                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 173                        mmc_hostname(host->mmc), clock,
 174                        curr_ios.timing);
 175                 return;
 176         }
 177         msm_host->clk_rate = clock;
 178         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 179                  mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
 180                  curr_ios.timing);
 181 }
 182
 183 /* Platform specific tuning */
 184 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 185 {
 186         u32 wait_cnt = 50;
 187         u8 ck_out_en;
 188         struct mmc_host *mmc = host->mmc;
 189
 190         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 191         ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 192                         CORE_CK_OUT_EN);
 193
 194         while (ck_out_en != poll) {
 195                 if (--wait_cnt == 0) {
 196                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 197                                mmc_hostname(mmc), poll);
 198                         return -ETIMEDOUT;
 199                 }
 200                 udelay(1);
 201
 202                 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 203                                 CORE_CK_OUT_EN);
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 210 {
 211         int rc;
 212         static const u8 grey_coded_phase_table[] = {
 213                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 214                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 215         };
 216         unsigned long flags;
 217         u32 config;
 218         struct mmc_host *mmc = host->mmc;
 219
 220         if (phase > 0xf)
 221                 return -EINVAL;
 222
 223         spin_lock_irqsave(&host->lock, flags);
 224
 225         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 226         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 227         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 228         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 229
 230         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 231         rc = msm_dll_poll_ck_out_en(host, 0);
 232         if (rc)
 233                 goto err_out;
 234
 235         /*
 236          * Write the selected DLL clock output phase (0 ... 15)
 237          * to CDR_SELEXT bit field of DLL_CONFIG register.
 238          */
 239         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 240         config &= ~CDR_SELEXT_MASK;
 241         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 242         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 243
 244         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 245         config |= CORE_CK_OUT_EN;
 246         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 247
 248         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 249         rc = msm_dll_poll_ck_out_en(host, 1);
 250         if (rc)
 251                 goto err_out;
 252
 253         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 254         config |= CORE_CDR_EN;
 255         config &= ~CORE_CDR_EXT_EN;
 256         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 257         goto out;
 258
 259 err_out:
 260         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 261                mmc_hostname(mmc), phase);
 262 out:
 263         spin_unlock_irqrestore(&host->lock, flags);
 264         return rc;
 265 }
 266
 267 /*
 268  * Find out the greatest range of consecuitive selected
 269  * DLL clock output phases that can be used as sampling
 270  * setting for SD3.0 UHS-I card read operation (in SDR104
 271  * timing mode) or for eMMC4.5 card read operation (in
 272  * HS400/HS200 timing mode).
 273  * Select the 3/4 of the range and configure the DLL with the
 274  * selected DLL clock output phase.
 275  */
 276
 277 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 278                                            u8 *phase_table, u8 total_phases)
 279 {
 280         int ret;
 281         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 282         u8 phases_per_row[MAX_PHASES] = { 0 };
 283         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 284         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 285         bool phase_0_found = false, phase_15_found = false;
 286         struct mmc_host *mmc = host->mmc;
 287
 288         if (!total_phases || (total_phases > MAX_PHASES)) {
 289                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 290                        mmc_hostname(mmc), total_phases);
 291                 return -EINVAL;
 292         }
 293
 294         for (cnt = 0; cnt < total_phases; cnt++) {
 295                 ranges[row_index][col_index] = phase_table[cnt];
 296                 phases_per_row[row_index] += 1;
 297                 col_index++;
 298
 299                 if ((cnt + 1) == total_phases) {
 300                         continue;
 301                 /* check if next phase in phase_table is consecutive or not */
 302                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 303                         row_index++;
 304                         col_index = 0;
 305                 }
 306         }
 307
 308         if (row_index >= MAX_PHASES)
 309                 return -EINVAL;
 310
 311         /* Check if phase-0 is present in first valid window? */
 312         if (!ranges[0][0]) {
 313                 phase_0_found = true;
 314                 phase_0_raw_index = 0;
 315                 /* Check if cycle exist between 2 valid windows */
 316                 for (cnt = 1; cnt <= row_index; cnt++) {
 317                         if (phases_per_row[cnt]) {
 318                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 319                                         if (ranges[cnt][i] == 15) {
 320                                                 phase_15_found = true;
 321                                                 phase_15_raw_index = cnt;
 322                                                 break;
 323                                         }
 324                                 }
 325                         }
 326                 }
 327         }
 328
 329         /* If 2 valid windows form cycle then merge them as single window */
 330         if (phase_0_found && phase_15_found) {
 331                 /* number of phases in raw where phase 0 is present */
 332                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 333                 /* number of phases in raw where phase 15 is present */
 334                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 335
 336                 if (phases_0 + phases_15 >= MAX_PHASES)
 337                         /*
 338                          * If there are more than 1 phase windows then total
 339                          * number of phases in both the windows should not be
 340                          * more than or equal to MAX_PHASES.
 341                          */
 342                         return -EINVAL;
 343
 344                 /* Merge 2 cyclic windows */
 345                 i = phases_15;
 346                 for (cnt = 0; cnt < phases_0; cnt++) {
 347                         ranges[phase_15_raw_index][i] =
 348                             ranges[phase_0_raw_index][cnt];
 349                         if (++i >= MAX_PHASES)
 350                                 break;
 351                 }
 352
 353                 phases_per_row[phase_0_raw_index] = 0;
 354                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 355         }
 356
 357         for (cnt = 0; cnt <= row_index; cnt++) {
 358                 if (phases_per_row[cnt] > curr_max) {
 359                         curr_max = phases_per_row[cnt];
 360                         selected_row_index = cnt;
 361                 }
 362         }
 363
 364         i = (curr_max * 3) / 4;
 365         if (i)
 366                 i--;
 367
 368         ret = ranges[selected_row_index][i];
 369
 370         if (ret >= MAX_PHASES) {
 371                 ret = -EINVAL;
 372                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 373                        mmc_hostname(mmc), ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 380 {
 381         u32 mclk_freq = 0, config;
 382
 383         /* Program the MCLK value to MCLK_FREQ bit field */
 384         if (host->clock <= 112000000)
 385                 mclk_freq = 0;
 386         else if (host->clock <= 125000000)
 387                 mclk_freq = 1;
 388         else if (host->clock <= 137000000)
 389                 mclk_freq = 2;
 390         else if (host->clock <= 150000000)
 391                 mclk_freq = 3;
 392         else if (host->clock <= 162000000)
 393                 mclk_freq = 4;
 394         else if (host->clock <= 175000000)
 395                 mclk_freq = 5;
 396         else if (host->clock <= 187000000)
 397                 mclk_freq = 6;
 398         else if (host->clock <= 200000000)
 399                 mclk_freq = 7;
 400
 401         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 402         config &= ~CMUX_SHIFT_PHASE_MASK;
 403         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 404         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 405 }
 406
 407 /* Initialize the DLL (Programmable Delay Line) */
 408 static int msm_init_cm_dll(struct sdhci_host *host)
 409 {
 410         struct mmc_host *mmc = host->mmc;
 411         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 412         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 413         int wait_cnt = 50;
 414         unsigned long flags;
 415         u32 config;
 416
 417         spin_lock_irqsave(&host->lock, flags);
 418
 419         /*
 420          * Make sure that clock is always enabled when DLL
 421          * tuning is in progress. Keeping PWRSAVE ON may
 422          * turn off the clock.
 423          */
 424         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 425         config &= ~CORE_CLK_PWRSAVE;
 426         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 427
 428         if (msm_host->use_14lpp_dll_reset) {
 429                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 430                 config &= ~CORE_CK_OUT_EN;
 431                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 432
 433                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 434                 config |= CORE_DLL_CLOCK_DISABLE;
 435                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 436         }
 437
 438         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 439         config |= CORE_DLL_RST;
 440         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 441
 442         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 443         config |= CORE_DLL_PDN;
 444         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 445         msm_cm_dll_set_freq(host);
 446
 447         if (msm_host->use_14lpp_dll_reset &&
 448             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 449                 u32 mclk_freq = 0;
 450
 451                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 452                 config &= CORE_FLL_CYCLE_CNT;
 453                 if (config)
 454                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 455                                         clk_get_rate(msm_host->xo_clk));
 456                 else
 457                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 458                                         clk_get_rate(msm_host->xo_clk));
 459
 460                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 461                 config &= ~(0xFF << 10);
 462                 config |= mclk_freq << 10;
 463
 464                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 465                 /* wait for 5us before enabling DLL clock */
 466                 udelay(5);
 467         }
 468
 469         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 470         config &= ~CORE_DLL_RST;
 471         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 472
 473         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 474         config &= ~CORE_DLL_PDN;
 475         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 476
 477         if (msm_host->use_14lpp_dll_reset) {
 478                 msm_cm_dll_set_freq(host);
 479                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 480                 config &= ~CORE_DLL_CLOCK_DISABLE;
 481                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 482         }
 483
 484         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 485         config |= CORE_DLL_EN;
 486         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 487
 488         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 489         config |= CORE_CK_OUT_EN;
 490         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 491
 492         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 493         while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
 494                  CORE_DLL_LOCK)) {
 495                 /* max. wait for 50us sec for LOCK bit to be set */
 496                 if (--wait_cnt == 0) {
 497                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 498                                mmc_hostname(mmc));
 499                         spin_unlock_irqrestore(&host->lock, flags);
 500                         return -ETIMEDOUT;
 501                 }
 502                 udelay(1);
 503         }
 504
 505         spin_unlock_irqrestore(&host->lock, flags);
 506         return 0;
 507 }
 508
 509 static void msm_hc_select_default(struct sdhci_host *host)
 510 {
 511         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 512         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 513         u32 config;
 514
 515         if (!msm_host->use_cdclp533) {
 516                 config = readl_relaxed(host->ioaddr +
 517                                 CORE_VENDOR_SPEC3);
 518                 config &= ~CORE_PWRSAVE_DLL;
 519                 writel_relaxed(config, host->ioaddr +
 520                                 CORE_VENDOR_SPEC3);
 521         }
 522
 523         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 524         config &= ~CORE_HC_MCLK_SEL_MASK;
 525         config |= CORE_HC_MCLK_SEL_DFLT;
 526         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 527
 528         /*
 529          * Disable HC_SELECT_IN to be able to use the UHS mode select
 530          * configuration from Host Control2 register for all other
 531          * modes.
 532          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 533          * in VENDOR_SPEC_FUNC
 534          */
 535         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 536         config &= ~CORE_HC_SELECT_IN_EN;
 537         config &= ~CORE_HC_SELECT_IN_MASK;
 538         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 539
 540         /*
 541          * Make sure above writes impacting free running MCLK are completed
 542          * before changing the clk_rate at GCC.
 543          */
 544         wmb();
 545 }
 546
 547 static void msm_hc_select_hs400(struct sdhci_host *host)
 548 {
 549         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 550         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 551         struct mmc_ios ios = host->mmc->ios;
 552         u32 config, dll_lock;
 553         int rc;
 554
 555         /* Select the divided clock (free running MCLK/2) */
 556         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 557         config &= ~CORE_HC_MCLK_SEL_MASK;
 558         config |= CORE_HC_MCLK_SEL_HS400;
 559
 560         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 561         /*
 562          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 563          * register
 564          */
 565         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 566             !msm_host->calibration_done) {
 567                 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 568                 config |= CORE_HC_SELECT_IN_HS400;
 569                 config |= CORE_HC_SELECT_IN_EN;
 570                 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 571         }
 572         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 573                 /*
 574                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 575                  * CORE_DLL_STATUS to be set.  This should get set
 576                  * within 15 us at 200 MHz.
 577                  */
 578                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 579                                                 CORE_DLL_STATUS,
 580                                                 dll_lock,
 581                                                 (dll_lock &
 582                                                 (CORE_DLL_LOCK |
 583                                                 CORE_DDR_DLL_LOCK)), 10,
 584                                                 1000);
 585                 if (rc == -ETIMEDOUT)
 586                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 587                                mmc_hostname(host->mmc), dll_lock);
 588         }
 589         /*
 590          * Make sure above writes impacting free running MCLK are completed
 591          * before changing the clk_rate at GCC.
 592          */
 593         wmb();
 594 }
 595
 596 /*
 597  * sdhci_msm_hc_select_mode :- In general all timing modes are
 598  * controlled via UHS mode select in Host Control2 register.
 599  * eMMC specific HS200/HS400 doesn't have their respective modes
 600  * defined here, hence we use these values.
 601  *
 602  * HS200 - SDR104 (Since they both are equivalent in functionality)
 603  * HS400 - This involves multiple configurations
 604  *              Initially SDR104 - when tuning is required as HS200
 605  *              Then when switching to DDR @ 400MHz (HS400) we use
 606  *              the vendor specific HC_SELECT_IN to control the mode.
 607  *
 608  * In addition to controlling the modes we also need to select the
 609  * correct input clock for DLL depending on the mode.
 610  *
 611  * HS400 - divided clock (free running MCLK/2)
 612  * All other modes - default (free running MCLK)
 613  */
 614 void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 615 {
 616         struct mmc_ios ios = host->mmc->ios;
 617
 618         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 619             host->flags & SDHCI_HS400_TUNING)
 620                 msm_hc_select_hs400(host);
 621         else
 622                 msm_hc_select_default(host);
 623 }
 624
 625 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 626 {
 627         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 628         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 629         u32 config, calib_done;
 630         int ret;
 631
 632         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 633
 634         /*
 635          * Retuning in HS400 (DDR mode) will fail, just reset the
 636          * tuning block and restore the saved tuning phase.
 637          */
 638         ret = msm_init_cm_dll(host);
 639         if (ret)
 640                 goto out;
 641
 642         /* Set the selected phase in delay line hw block */
 643         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 644         if (ret)
 645                 goto out;
 646
 647         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 648         config |= CORE_CMD_DAT_TRACK_SEL;
 649         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 650
 651         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 652         config &= ~CORE_CDC_T4_DLY_SEL;
 653         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 654
 655         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 656         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 657         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 658
 659         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 660         config |= CORE_CDC_SWITCH_RC_EN;
 661         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 662
 663         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 664         config &= ~CORE_START_CDC_TRAFFIC;
 665         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 666
 667         /* Perform CDC Register Initialization Sequence */
 668
 669         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 670         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 671         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 672         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 673         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 674         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 675         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 676         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 677         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 678
 679         /* CDC HW Calibration */
 680
 681         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 682         config |= CORE_SW_TRIG_FULL_CALIB;
 683         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 684
 685         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 686         config &= ~CORE_SW_TRIG_FULL_CALIB;
 687         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 688
 689         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 690         config |= CORE_HW_AUTOCAL_ENA;
 691         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 692
 693         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 694         config |= CORE_TIMER_ENA;
 695         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 696
 697         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 698                                          calib_done,
 699                                          (calib_done & CORE_CALIBRATION_DONE),
 700                                          1, 50);
 701
 702         if (ret == -ETIMEDOUT) {
 703                 pr_err("%s: %s: CDC calibration was not completed\n",
 704                        mmc_hostname(host->mmc), __func__);
 705                 goto out;
 706         }
 707
 708         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 709                         & CORE_CDC_ERROR_CODE_MASK;
 710         if (ret) {
 711                 pr_err("%s: %s: CDC error code %d\n",
 712                        mmc_hostname(host->mmc), __func__, ret);
 713                 ret = -EINVAL;
 714                 goto out;
 715         }
 716
 717         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 718         config |= CORE_START_CDC_TRAFFIC;
 719         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 720 out:
 721         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 722                  __func__, ret);
 723         return ret;
 724 }
 725
 726 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 727 {
 728         struct mmc_host *mmc = host->mmc;
 729         u32 dll_status, config;
 730         int ret;
 731
 732         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 733
 734         /*
 735          * Currently the CORE_DDR_CONFIG register defaults to desired
 736          * configuration on reset. Currently reprogramming the power on
 737          * reset (POR) value in case it might have been modified by
 738          * bootloaders. In the future, if this changes, then the desired
 739          * values will need to be programmed appropriately.
 740          */
 741         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
 742
 743         if (mmc->ios.enhanced_strobe) {
 744                 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 745                 config |= CORE_CMDIN_RCLK_EN;
 746                 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 747         }
 748
 749         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 750         config |= CORE_DDR_CAL_EN;
 751         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 752
 753         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
 754                                          dll_status,
 755                                          (dll_status & CORE_DDR_DLL_LOCK),
 756                                          10, 1000);
 757
 758         if (ret == -ETIMEDOUT) {
 759                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 760                        mmc_hostname(host->mmc), __func__);
 761                 goto out;
 762         }
 763
 764         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
 765         config |= CORE_PWRSAVE_DLL;
 766         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
 767
 768         /*
 769          * Drain writebuffer to ensure above DLL calibration
 770          * and PWRSAVE DLL is enabled.
 771          */
 772         wmb();
 773 out:
 774         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 775                  __func__, ret);
 776         return ret;
 777 }
 778
 779 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 780 {
 781         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 782         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 783         struct mmc_host *mmc = host->mmc;
 784         int ret;
 785         u32 config;
 786
 787         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 788
 789         /*
 790          * Retuning in HS400 (DDR mode) will fail, just reset the
 791          * tuning block and restore the saved tuning phase.
 792          */
 793         ret = msm_init_cm_dll(host);
 794         if (ret)
 795                 goto out;
 796
 797         if (!mmc->ios.enhanced_strobe) {
 798                 /* Set the selected phase in delay line hw block */
 799                 ret = msm_config_cm_dll_phase(host,
 800                                               msm_host->saved_tuning_phase);
 801                 if (ret)
 802                         goto out;
 803                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 804                 config |= CORE_CMD_DAT_TRACK_SEL;
 805                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 806         }
 807
 808         if (msm_host->use_cdclp533)
 809                 ret = sdhci_msm_cdclp533_calibration(host);
 810         else
 811                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
 812 out:
 813         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 814                  __func__, ret);
 815         return ret;
 816 }
 817
 818 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
 819 {
 820         struct sdhci_host *host = mmc_priv(mmc);
 821         int tuning_seq_cnt = 3;
 822         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
 823         int rc;
 824         struct mmc_ios ios = host->mmc->ios;
 825         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 826         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 827
 828         /*
 829          * Tuning is required for SDR104, HS200 and HS400 cards and
 830          * if clock frequency is greater than 100MHz in these modes.
 831          */
 832         if (host->clock <= CORE_FREQ_100MHZ ||
 833             !(ios.timing == MMC_TIMING_MMC_HS400 ||
 834             ios.timing == MMC_TIMING_MMC_HS200 ||
 835             ios.timing == MMC_TIMING_UHS_SDR104))
 836                 return 0;
 837
 838         /*
 839          * For HS400 tuning in HS200 timing requires:
 840          * - select MCLK/2 in VENDOR_SPEC
 841          * - program MCLK to 400MHz (or nearest supported) in GCC
 842          */
 843         if (host->flags & SDHCI_HS400_TUNING) {
 844                 sdhci_msm_hc_select_mode(host);
 845                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
 846                 host->flags &= ~SDHCI_HS400_TUNING;
 847         }
 848
 849 retry:
 850         /* First of all reset the tuning block */
 851         rc = msm_init_cm_dll(host);
 852         if (rc)
 853                 return rc;
 854
 855         phase = 0;
 856         do {
 857                 /* Set the phase in delay line hw block */
 858                 rc = msm_config_cm_dll_phase(host, phase);
 859                 if (rc)
 860                         return rc;
 861
 862                 msm_host->saved_tuning_phase = phase;
 863                 rc = mmc_send_tuning(mmc, opcode, NULL);
 864                 if (!rc) {
 865                         /* Tuning is successful at this tuning point */
 866                         tuned_phases[tuned_phase_cnt++] = phase;
 867                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
 868                                  mmc_hostname(mmc), phase);
 869                 }
 870         } while (++phase < ARRAY_SIZE(tuned_phases));
 871
 872         if (tuned_phase_cnt) {
 873                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
 874                                                      tuned_phase_cnt);
 875                 if (rc < 0)
 876                         return rc;
 877                 else
 878                         phase = rc;
 879
 880                 /*
 881                  * Finally set the selected phase in delay
 882                  * line hw block.
 883                  */
 884                 rc = msm_config_cm_dll_phase(host, phase);
 885                 if (rc)
 886                         return rc;
 887                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
 888                          mmc_hostname(mmc), phase);
 889         } else {
 890                 if (--tuning_seq_cnt)
 891                         goto retry;
 892                 /* Tuning failed */
 893                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
 894                        mmc_hostname(mmc));
 895                 rc = -EIO;
 896         }
 897
 898         if (!rc)
 899                 msm_host->tuning_done = true;
 900         return rc;
 901 }
 902
 903 /*
 904  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
 905  * This needs to be done for both tuning and enhanced_strobe mode.
 906  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
 907  * fixed feedback clock is used.
 908  */
 909 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
 910 {
 911         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 912         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 913         int ret;
 914
 915         if (host->clock > CORE_FREQ_100MHZ &&
 916             (msm_host->tuning_done || ios->enhanced_strobe) &&
 917             !msm_host->calibration_done) {
 918                 ret = sdhci_msm_hs400_dll_calibration(host);
 919                 if (!ret)
 920                         msm_host->calibration_done = true;
 921                 else
 922                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
 923                                mmc_hostname(host->mmc), ret);
 924         }
 925 }
 926
 927 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 928                                         unsigned int uhs)
 929 {
 930         struct mmc_host *mmc = host->mmc;
 931         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 932         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 933         u16 ctrl_2;
 934         u32 config;
 935
 936         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 937         /* Select Bus Speed Mode for host */
 938         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 939         switch (uhs) {
 940         case MMC_TIMING_UHS_SDR12:
 941                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 942                 break;
 943         case MMC_TIMING_UHS_SDR25:
 944                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 945                 break;
 946         case MMC_TIMING_UHS_SDR50:
 947                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 948                 break;
 949         case MMC_TIMING_MMC_HS400:
 950         case MMC_TIMING_MMC_HS200:
 951         case MMC_TIMING_UHS_SDR104:
 952                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 953                 break;
 954         case MMC_TIMING_UHS_DDR50:
 955         case MMC_TIMING_MMC_DDR52:
 956                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 957                 break;
 958         }
 959
 960         /*
 961          * When clock frequency is less than 100MHz, the feedback clock must be
 962          * provided and DLL must not be used so that tuning can be skipped. To
 963          * provide feedback clock, the mode selection can be any value less
 964          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
 965          */
 966         if (host->clock <= CORE_FREQ_100MHZ) {
 967                 if (uhs == MMC_TIMING_MMC_HS400 ||
 968                     uhs == MMC_TIMING_MMC_HS200 ||
 969                     uhs == MMC_TIMING_UHS_SDR104)
 970                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 971                 /*
 972                  * DLL is not required for clock <= 100MHz
 973                  * Thus, make sure DLL it is disabled when not required
 974                  */
 975                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 976                 config |= CORE_DLL_RST;
 977                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 978
 979                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 980                 config |= CORE_DLL_PDN;
 981                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 982
 983                 /*
 984                  * The DLL needs to be restored and CDCLP533 recalibrated
 985                  * when the clock frequency is set back to 400MHz.
 986                  */
 987                 msm_host->calibration_done = false;
 988         }
 989
 990         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
 991                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
 992         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 993
 994         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
 995                 sdhci_msm_hs400(host, &mmc->ios);
 996 }
 997
 998 static void sdhci_msm_voltage_switch(struct sdhci_host *host)
 999 {
1000         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1001         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1002         u32 irq_status, irq_ack = 0;
1003
1004         irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
1005         irq_status &= INT_MASK;
1006
1007         writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
1008
1009         if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
1010                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1011         if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
1012                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1013
1014         /*
1015          * The driver has to acknowledge the interrupt, switch voltages and
1016          * report back if it succeded or not to this register. The voltage
1017          * switches are handled by the sdhci core, so just report success.
1018          */
1019         writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
1020 }
1021
1022 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1023 {
1024         struct sdhci_host *host = (struct sdhci_host *)data;
1025
1026         sdhci_msm_voltage_switch(host);
1027
1028         return IRQ_HANDLED;
1029 }
1030
1031 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1032 {
1033         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1034         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1035
1036         return clk_round_rate(msm_host->clk, ULONG_MAX);
1037 }
1038
1039 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1040 {
1041         return SDHCI_MSM_MIN_CLOCK;
1042 }
1043
1044 /**
1045  * __sdhci_msm_set_clock - sdhci_msm clock control.
1046  *
1047  * Description:
1048  * MSM controller does not use internal divider and
1049  * instead directly control the GCC clock as per
1050  * HW recommendation.
1051  **/
1052 void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1053 {
1054         u16 clk;
1055         /*
1056          * Keep actual_clock as zero -
1057          * - since there is no divider used so no need of having actual_clock.
1058          * - MSM controller uses SDCLK for data timeout calculation. If
1059          *   actual_clock is zero, host->clock is taken for calculation.
1060          */
1061         host->mmc->actual_clock = 0;
1062
1063         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1064
1065         if (clock == 0)
1066                 return;
1067
1068         /*
1069          * MSM controller do not use clock divider.
1070          * Thus read SDHCI_CLOCK_CONTROL and only enable
1071          * clock with no divider value programmed.
1072          */
1073         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1074         sdhci_enable_clk(host, clk);
1075 }
1076
1077 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1078 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1079 {
1080         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1081         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1082
1083         if (!clock) {
1084                 msm_host->clk_rate = clock;
1085                 goto out;
1086         }
1087
1088         sdhci_msm_hc_select_mode(host);
1089
1090         msm_set_clock_rate_for_bus_mode(host, clock);
1091 out:
1092         __sdhci_msm_set_clock(host, clock);
1093 }
1094
1095 static const struct of_device_id sdhci_msm_dt_match[] = {
1096         { .compatible = "qcom,sdhci-msm-v4" },
1097         {},
1098 };
1099
1100 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1101
1102 static const struct sdhci_ops sdhci_msm_ops = {
1103         .reset = sdhci_reset,
1104         .set_clock = sdhci_msm_set_clock,
1105         .get_min_clock = sdhci_msm_get_min_clock,
1106         .get_max_clock = sdhci_msm_get_max_clock,
1107         .set_bus_width = sdhci_set_bus_width,
1108         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1109         .voltage_switch = sdhci_msm_voltage_switch,
1110 };
1111
1112 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1113         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1114                   SDHCI_QUIRK_NO_CARD_NO_RESET |
1115                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1116                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1117         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1118         .ops = &sdhci_msm_ops,
1119 };
1120
1121 static int sdhci_msm_probe(struct platform_device *pdev)
1122 {
1123         struct sdhci_host *host;
1124         struct sdhci_pltfm_host *pltfm_host;
1125         struct sdhci_msm_host *msm_host;
1126         struct resource *core_memres;
1127         int ret;
1128         u16 host_version, core_minor;
1129         u32 core_version, config;
1130         u8 core_major;
1131
1132         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1133         if (IS_ERR(host))
1134                 return PTR_ERR(host);
1135
1136         pltfm_host = sdhci_priv(host);
1137         msm_host = sdhci_pltfm_priv(pltfm_host);
1138         msm_host->mmc = host->mmc;
1139         msm_host->pdev = pdev;
1140
1141         ret = mmc_of_parse(host->mmc);
1142         if (ret)
1143                 goto pltfm_free;
1144
1145         sdhci_get_of_property(pdev);
1146
1147         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1148
1149         /* Setup SDCC bus voter clock. */
1150         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1151         if (!IS_ERR(msm_host->bus_clk)) {
1152                 /* Vote for max. clk rate for max. performance */
1153                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1154                 if (ret)
1155                         goto pltfm_free;
1156                 ret = clk_prepare_enable(msm_host->bus_clk);
1157                 if (ret)
1158                         goto pltfm_free;
1159         }
1160
1161         /* Setup main peripheral bus clock */
1162         msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
1163         if (IS_ERR(msm_host->pclk)) {
1164                 ret = PTR_ERR(msm_host->pclk);
1165                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1166                 goto bus_clk_disable;
1167         }
1168
1169         ret = clk_prepare_enable(msm_host->pclk);
1170         if (ret)
1171                 goto bus_clk_disable;
1172
1173         /* Setup SDC MMC clock */
1174         msm_host->clk = devm_clk_get(&pdev->dev, "core");
1175         if (IS_ERR(msm_host->clk)) {
1176                 ret = PTR_ERR(msm_host->clk);
1177                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1178                 goto pclk_disable;
1179         }
1180
1181         /*
1182          * xo clock is needed for FLL feature of cm_dll.
1183          * In case if xo clock is not mentioned in DT, warn and proceed.
1184          */
1185         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1186         if (IS_ERR(msm_host->xo_clk)) {
1187                 ret = PTR_ERR(msm_host->xo_clk);
1188                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1189         }
1190
1191         /* Vote for maximum clock rate for maximum performance */
1192         ret = clk_set_rate(msm_host->clk, INT_MAX);
1193         if (ret)
1194                 dev_warn(&pdev->dev, "core clock boost failed\n");
1195
1196         ret = clk_prepare_enable(msm_host->clk);
1197         if (ret)
1198                 goto pclk_disable;
1199
1200         core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1201         msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1202
1203         if (IS_ERR(msm_host->core_mem)) {
1204                 dev_err(&pdev->dev, "Failed to remap registers\n");
1205                 ret = PTR_ERR(msm_host->core_mem);
1206                 goto clk_disable;
1207         }
1208
1209         /* Reset the vendor spec register to power on reset state */
1210         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1211                        host->ioaddr + CORE_VENDOR_SPEC);
1212
1213         /* Set HC_MODE_EN bit in HC_MODE register */
1214         writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1215
1216         config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1217         config |= FF_CLK_SW_RST_DIS;
1218         writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1219
1220         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1221         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1222                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1223                                SDHCI_VENDOR_VER_SHIFT));
1224
1225         core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1226         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1227                       CORE_VERSION_MAJOR_SHIFT;
1228         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1229         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1230                 core_version, core_major, core_minor);
1231
1232         if (core_major == 1 && core_minor >= 0x42)
1233                 msm_host->use_14lpp_dll_reset = true;
1234
1235         /*
1236          * SDCC 5 controller with major version 1, minor version 0x34 and later
1237          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1238          */
1239         if (core_major == 1 && core_minor < 0x34)
1240                 msm_host->use_cdclp533 = true;
1241
1242         /*
1243          * Support for some capabilities is not advertised by newer
1244          * controller versions and must be explicitly enabled.
1245          */
1246         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1247                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1248                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1249                 writel_relaxed(config, host->ioaddr +
1250                                CORE_VENDOR_SPEC_CAPABILITIES0);
1251         }
1252
1253         /* Setup IRQ for handling power/voltage tasks with PMIC */
1254         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1255         if (msm_host->pwr_irq < 0) {
1256                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1257                         msm_host->pwr_irq);
1258                 ret = msm_host->pwr_irq;
1259                 goto clk_disable;
1260         }
1261
1262         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1263                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1264                                         dev_name(&pdev->dev), host);
1265         if (ret) {
1266                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1267                 goto clk_disable;
1268         }
1269
1270         pm_runtime_get_noresume(&pdev->dev);
1271         pm_runtime_set_active(&pdev->dev);
1272         pm_runtime_enable(&pdev->dev);
1273         pm_runtime_set_autosuspend_delay(&pdev->dev,
1274                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1275         pm_runtime_use_autosuspend(&pdev->dev);
1276
1277         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1278         ret = sdhci_add_host(host);
1279         if (ret)
1280                 goto pm_runtime_disable;
1281
1282         pm_runtime_mark_last_busy(&pdev->dev);
1283         pm_runtime_put_autosuspend(&pdev->dev);
1284
1285         return 0;
1286
1287 pm_runtime_disable:
1288         pm_runtime_disable(&pdev->dev);
1289         pm_runtime_set_suspended(&pdev->dev);
1290         pm_runtime_put_noidle(&pdev->dev);
1291 clk_disable:
1292         clk_disable_unprepare(msm_host->clk);
1293 pclk_disable:
1294         clk_disable_unprepare(msm_host->pclk);
1295 bus_clk_disable:
1296         if (!IS_ERR(msm_host->bus_clk))
1297                 clk_disable_unprepare(msm_host->bus_clk);
1298 pltfm_free:
1299         sdhci_pltfm_free(pdev);
1300         return ret;
1301 }
1302
1303 static int sdhci_msm_remove(struct platform_device *pdev)
1304 {
1305         struct sdhci_host *host = platform_get_drvdata(pdev);
1306         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1307         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1308         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1309                     0xffffffff);
1310
1311         sdhci_remove_host(host, dead);
1312
1313         pm_runtime_get_sync(&pdev->dev);
1314         pm_runtime_disable(&pdev->dev);
1315         pm_runtime_put_noidle(&pdev->dev);
1316
1317         clk_disable_unprepare(msm_host->clk);
1318         clk_disable_unprepare(msm_host->pclk);
1319         if (!IS_ERR(msm_host->bus_clk))
1320                 clk_disable_unprepare(msm_host->bus_clk);
1321         sdhci_pltfm_free(pdev);
1322         return 0;
1323 }
1324
1325 #ifdef CONFIG_PM
1326 static int sdhci_msm_runtime_suspend(struct device *dev)
1327 {
1328         struct sdhci_host *host = dev_get_drvdata(dev);
1329         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1330         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1331
1332         clk_disable_unprepare(msm_host->clk);
1333         clk_disable_unprepare(msm_host->pclk);
1334
1335         return 0;
1336 }
1337
1338 static int sdhci_msm_runtime_resume(struct device *dev)
1339 {
1340         struct sdhci_host *host = dev_get_drvdata(dev);
1341         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1342         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1343         int ret;
1344
1345         ret = clk_prepare_enable(msm_host->clk);
1346         if (ret) {
1347                 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
1348                 return ret;
1349         }
1350         ret = clk_prepare_enable(msm_host->pclk);
1351         if (ret) {
1352                 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
1353                 clk_disable_unprepare(msm_host->clk);
1354                 return ret;
1355         }
1356
1357         return 0;
1358 }
1359 #endif
1360
1361 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1362         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1363                                 pm_runtime_force_resume)
1364         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1365                            sdhci_msm_runtime_resume,
1366                            NULL)
1367 };
1368
1369 static struct platform_driver sdhci_msm_driver = {
1370         .probe = sdhci_msm_probe,
1371         .remove = sdhci_msm_remove,
1372         .driver = {
1373                    .name = "sdhci_msm",
1374                    .of_match_table = sdhci_msm_dt_match,
1375                    .pm = &sdhci_msm_pm_ops,
1376         },
1377 };
1378
1379 module_platform_driver(sdhci_msm_driver);
1380
1381 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1382 MODULE_LICENSE("GPL v2");