2 * Freescale eSDHC controller driver.
4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/err.h>
19 #include <linux/of_address.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/sys_soc.h>
23 #include <linux/clk.h>
24 #include <linux/ktime.h>
25 #include <linux/mmc/host.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
29 #define VENDOR_V_22 0x12
30 #define VENDOR_V_23 0x13
35 bool quirk_incorrect_hostver;
36 unsigned int peripheral_clock;
40 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
41 * to make it compatible with SD spec.
43 * @host: pointer to sdhci_host
44 * @spec_reg: SD spec register address
45 * @value: 32bit eSDHC register value on spec_reg address
47 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
48 * registers are 32 bits. There are differences in register size, register
49 * address, register function, bit position and function between eSDHC spec
52 * Return a fixed up register value
54 static u32 esdhc_readl_fixup(struct sdhci_host *host,
55 int spec_reg, u32 value)
57 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
58 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
62 * The bit of ADMA flag in eSDHC is not compatible with standard
63 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
65 * And for many FSL eSDHC controller, the reset value of field
66 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
67 * only these vendor version is greater than 2.2/0x12 support ADMA.
69 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
70 if (esdhc->vendor_ver > VENDOR_V_22) {
71 ret = value | SDHCI_CAN_DO_ADMA2;
76 * The DAT[3:0] line signal levels and the CMD line signal level are
77 * not compatible with standard SDHC register. The line signal levels
78 * DAT[7:0] are at bits 31:24 and the command line signal level is at
79 * bit 23. All other bits are the same as in the standard SDHC
82 if (spec_reg == SDHCI_PRESENT_STATE) {
83 ret = value & 0x000fffff;
84 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
85 ret |= (value << 1) & SDHCI_CMD_LVL;
93 static u16 esdhc_readw_fixup(struct sdhci_host *host,
94 int spec_reg, u32 value)
96 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
97 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
99 int shift = (spec_reg & 0x2) * 8;
101 if (spec_reg == SDHCI_HOST_VERSION)
102 ret = value & 0xffff;
104 ret = (value >> shift) & 0xffff;
105 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
106 * vendor version and spec version information.
108 if ((spec_reg == SDHCI_HOST_VERSION) &&
109 (esdhc->quirk_incorrect_hostver))
110 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
114 static u8 esdhc_readb_fixup(struct sdhci_host *host,
115 int spec_reg, u32 value)
119 int shift = (spec_reg & 0x3) * 8;
121 ret = (value >> shift) & 0xff;
124 * "DMA select" locates at offset 0x28 in SD specification, but on
125 * P5020 or P3041, it locates at 0x29.
127 if (spec_reg == SDHCI_HOST_CONTROL) {
128 /* DMA select is 22,23 bits in Protocol Control Register */
129 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
130 /* fixup the result */
131 ret &= ~SDHCI_CTRL_DMA_MASK;
138 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
139 * written into eSDHC register.
141 * @host: pointer to sdhci_host
142 * @spec_reg: SD spec register address
143 * @value: 8/16/32bit SD spec register value that would be written
144 * @old_value: 32bit eSDHC register value on spec_reg address
146 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
147 * registers are 32 bits. There are differences in register size, register
148 * address, register function, bit position and function between eSDHC spec
151 * Return a fixed up register value
153 static u32 esdhc_writel_fixup(struct sdhci_host *host,
154 int spec_reg, u32 value, u32 old_value)
159 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
160 * when SYSCTL[RSTD] is set for some special operations.
161 * No any impact on other operation.
163 if (spec_reg == SDHCI_INT_ENABLE)
164 ret = value | SDHCI_INT_BLK_GAP;
171 static u32 esdhc_writew_fixup(struct sdhci_host *host,
172 int spec_reg, u16 value, u32 old_value)
174 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
175 int shift = (spec_reg & 0x2) * 8;
179 case SDHCI_TRANSFER_MODE:
181 * Postpone this write, we must do it together with a
182 * command write that is down below. Return old value.
184 pltfm_host->xfer_mode_shadow = value;
187 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
191 ret = old_value & (~(0xffff << shift));
192 ret |= (value << shift);
194 if (spec_reg == SDHCI_BLOCK_SIZE) {
196 * Two last DMA bits are reserved, and first one is used for
197 * non-standard blksz of 4096 bytes that we don't support
198 * yet. So clear the DMA boundary bits.
200 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
205 static u32 esdhc_writeb_fixup(struct sdhci_host *host,
206 int spec_reg, u8 value, u32 old_value)
211 int shift = (spec_reg & 0x3) * 8;
214 * eSDHC doesn't have a standard power control register, so we do
215 * nothing here to avoid incorrect operation.
217 if (spec_reg == SDHCI_POWER_CONTROL)
220 * "DMA select" location is offset 0x28 in SD specification, but on
221 * P5020 or P3041, it's located at 0x29.
223 if (spec_reg == SDHCI_HOST_CONTROL) {
225 * If host control register is not standard, exit
228 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
231 /* DMA select is 22,23 bits in Protocol Control Register */
232 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
233 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
234 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
235 (old_value & SDHCI_CTRL_DMA_MASK);
236 ret = (ret & (~0xff)) | tmp;
238 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
239 ret &= ~ESDHC_HOST_CONTROL_RES;
243 ret = (old_value & (~(0xff << shift))) | (value << shift);
247 static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
252 value = ioread32be(host->ioaddr + reg);
253 ret = esdhc_readl_fixup(host, reg, value);
258 static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
263 value = ioread32(host->ioaddr + reg);
264 ret = esdhc_readl_fixup(host, reg, value);
269 static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
273 int base = reg & ~0x3;
275 value = ioread32be(host->ioaddr + base);
276 ret = esdhc_readw_fixup(host, reg, value);
280 static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
284 int base = reg & ~0x3;
286 value = ioread32(host->ioaddr + base);
287 ret = esdhc_readw_fixup(host, reg, value);
291 static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
295 int base = reg & ~0x3;
297 value = ioread32be(host->ioaddr + base);
298 ret = esdhc_readb_fixup(host, reg, value);
302 static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
306 int base = reg & ~0x3;
308 value = ioread32(host->ioaddr + base);
309 ret = esdhc_readb_fixup(host, reg, value);
313 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
317 value = esdhc_writel_fixup(host, reg, val, 0);
318 iowrite32be(value, host->ioaddr + reg);
321 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
325 value = esdhc_writel_fixup(host, reg, val, 0);
326 iowrite32(value, host->ioaddr + reg);
329 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
331 int base = reg & ~0x3;
335 value = ioread32be(host->ioaddr + base);
336 ret = esdhc_writew_fixup(host, reg, val, value);
337 if (reg != SDHCI_TRANSFER_MODE)
338 iowrite32be(ret, host->ioaddr + base);
341 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
343 int base = reg & ~0x3;
347 value = ioread32(host->ioaddr + base);
348 ret = esdhc_writew_fixup(host, reg, val, value);
349 if (reg != SDHCI_TRANSFER_MODE)
350 iowrite32(ret, host->ioaddr + base);
353 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
355 int base = reg & ~0x3;
359 value = ioread32be(host->ioaddr + base);
360 ret = esdhc_writeb_fixup(host, reg, val, value);
361 iowrite32be(ret, host->ioaddr + base);
364 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
366 int base = reg & ~0x3;
370 value = ioread32(host->ioaddr + base);
371 ret = esdhc_writeb_fixup(host, reg, val, value);
372 iowrite32(ret, host->ioaddr + base);
376 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
377 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
378 * and Block Gap Event(IRQSTAT[BGE]) are also set.
379 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
380 * and re-issue the entire read transaction from beginning.
382 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
384 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
385 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
390 applicable = (intmask & SDHCI_INT_DATA_END) &&
391 (intmask & SDHCI_INT_BLK_GAP) &&
392 (esdhc->vendor_ver == VENDOR_V_23);
396 host->data->error = 0;
397 dmastart = sg_dma_address(host->data->sg);
398 dmanow = dmastart + host->data->bytes_xfered;
400 * Force update to the next DMA block boundary.
402 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
403 SDHCI_DEFAULT_BOUNDARY_SIZE;
404 host->data->bytes_xfered = dmanow - dmastart;
405 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
408 static int esdhc_of_enable_dma(struct sdhci_host *host)
412 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
413 value |= ESDHC_DMA_SNOOP;
414 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
418 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
420 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
421 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
423 if (esdhc->peripheral_clock)
424 return esdhc->peripheral_clock;
426 return pltfm_host->clock;
429 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
431 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
432 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
435 if (esdhc->peripheral_clock)
436 clock = esdhc->peripheral_clock;
438 clock = pltfm_host->clock;
439 return clock / 256 / 16;
442 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
444 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
445 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
451 host->mmc->actual_clock = 0;
456 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
457 if (esdhc->vendor_ver < VENDOR_V_23)
461 * Limit SD clock to 167MHz for ls1046a according to its datasheet
463 if (clock > 167000000 &&
464 of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
468 * Limit SD clock to 125MHz for ls1012a according to its datasheet
470 if (clock > 125000000 &&
471 of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
474 /* Workaround to reduce the clock frequency for p1010 esdhc */
475 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
476 if (clock > 20000000)
478 if (clock > 40000000)
482 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
483 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
484 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
485 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
487 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
490 while (host->max_clk / pre_div / div > clock && div < 16)
493 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
494 clock, host->max_clk / pre_div / div);
495 host->mmc->actual_clock = host->max_clk / pre_div / div;
499 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
500 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
501 | (div << ESDHC_DIVIDER_SHIFT)
502 | (pre_div << ESDHC_PREDIV_SHIFT));
503 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
506 timeout = ktime_add_ms(ktime_get(), 20);
507 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) {
508 if (ktime_after(ktime_get(), timeout)) {
509 pr_err("%s: Internal clock never stabilised.\n",
510 mmc_hostname(host->mmc));
516 temp |= ESDHC_CLOCK_SDCLKEN;
517 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
520 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
524 ctrl = sdhci_readl(host, ESDHC_PROCTL);
525 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
527 case MMC_BUS_WIDTH_8:
528 ctrl |= ESDHC_CTRL_8BITBUS;
531 case MMC_BUS_WIDTH_4:
532 ctrl |= ESDHC_CTRL_4BITBUS;
539 sdhci_writel(host, ctrl, ESDHC_PROCTL);
542 static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
547 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
550 val |= ESDHC_CLOCK_SDCLKEN;
552 val &= ~ESDHC_CLOCK_SDCLKEN;
554 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
557 timeout = ktime_add_ms(ktime_get(), 20);
558 val = ESDHC_CLOCK_STABLE;
559 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) {
560 if (ktime_after(ktime_get(), timeout)) {
561 pr_err("%s: Internal clock never stabilised.\n",
562 mmc_hostname(host->mmc));
569 static void esdhc_reset(struct sdhci_host *host, u8 mask)
571 sdhci_reset(host, mask);
573 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
574 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
577 /* The SCFG, Supplemental Configuration Unit, provides SoC specific
578 * configuration and status registers for the device. There is a
579 * SDHC IO VSEL control register on SCFG for some platforms. It's
580 * used to support SDHC IO voltage switching.
582 static const struct of_device_id scfg_device_ids[] = {
583 { .compatible = "fsl,t1040-scfg", },
584 { .compatible = "fsl,ls1012a-scfg", },
585 { .compatible = "fsl,ls1046a-scfg", },
589 /* SDHC IO VSEL control register definition */
590 #define SCFG_SDHCIOVSELCR 0x408
591 #define SDHCIOVSELCR_TGLEN 0x80000000
592 #define SDHCIOVSELCR_VSELVAL 0x60000000
593 #define SDHCIOVSELCR_SDHC_VS 0x00000001
595 static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
598 struct sdhci_host *host = mmc_priv(mmc);
599 struct device_node *scfg_node;
600 void __iomem *scfg_base = NULL;
605 * Signal Voltage Switching is only applicable for Host Controllers
608 if (host->version < SDHCI_SPEC_300)
611 val = sdhci_readl(host, ESDHC_PROCTL);
613 switch (ios->signal_voltage) {
614 case MMC_SIGNAL_VOLTAGE_330:
615 val &= ~ESDHC_VOLT_SEL;
616 sdhci_writel(host, val, ESDHC_PROCTL);
618 case MMC_SIGNAL_VOLTAGE_180:
619 scfg_node = of_find_matching_node(NULL, scfg_device_ids);
621 scfg_base = of_iomap(scfg_node, 0);
623 sdhciovselcr = SDHCIOVSELCR_TGLEN |
624 SDHCIOVSELCR_VSELVAL;
625 iowrite32be(sdhciovselcr,
626 scfg_base + SCFG_SDHCIOVSELCR);
628 val |= ESDHC_VOLT_SEL;
629 sdhci_writel(host, val, ESDHC_PROCTL);
632 sdhciovselcr = SDHCIOVSELCR_TGLEN |
633 SDHCIOVSELCR_SDHC_VS;
634 iowrite32be(sdhciovselcr,
635 scfg_base + SCFG_SDHCIOVSELCR);
638 val |= ESDHC_VOLT_SEL;
639 sdhci_writel(host, val, ESDHC_PROCTL);
647 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
649 struct sdhci_host *host = mmc_priv(mmc);
652 /* Use tuning block for tuning procedure */
653 esdhc_clock_enable(host, false);
654 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
655 val |= ESDHC_FLUSH_ASYNC_FIFO;
656 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
658 val = sdhci_readl(host, ESDHC_TBCTL);
660 sdhci_writel(host, val, ESDHC_TBCTL);
661 esdhc_clock_enable(host, true);
663 return sdhci_execute_tuning(mmc, opcode);
666 #ifdef CONFIG_PM_SLEEP
667 static u32 esdhc_proctl;
668 static int esdhc_of_suspend(struct device *dev)
670 struct sdhci_host *host = dev_get_drvdata(dev);
672 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
674 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
675 mmc_retune_needed(host->mmc);
677 return sdhci_suspend_host(host);
680 static int esdhc_of_resume(struct device *dev)
682 struct sdhci_host *host = dev_get_drvdata(dev);
683 int ret = sdhci_resume_host(host);
686 /* Isn't this already done by sdhci_resume_host() ? --rmk */
687 esdhc_of_enable_dma(host);
688 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
694 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
698 static const struct sdhci_ops sdhci_esdhc_be_ops = {
699 .read_l = esdhc_be_readl,
700 .read_w = esdhc_be_readw,
701 .read_b = esdhc_be_readb,
702 .write_l = esdhc_be_writel,
703 .write_w = esdhc_be_writew,
704 .write_b = esdhc_be_writeb,
705 .set_clock = esdhc_of_set_clock,
706 .enable_dma = esdhc_of_enable_dma,
707 .get_max_clock = esdhc_of_get_max_clock,
708 .get_min_clock = esdhc_of_get_min_clock,
709 .adma_workaround = esdhc_of_adma_workaround,
710 .set_bus_width = esdhc_pltfm_set_bus_width,
711 .reset = esdhc_reset,
712 .set_uhs_signaling = sdhci_set_uhs_signaling,
715 static const struct sdhci_ops sdhci_esdhc_le_ops = {
716 .read_l = esdhc_le_readl,
717 .read_w = esdhc_le_readw,
718 .read_b = esdhc_le_readb,
719 .write_l = esdhc_le_writel,
720 .write_w = esdhc_le_writew,
721 .write_b = esdhc_le_writeb,
722 .set_clock = esdhc_of_set_clock,
723 .enable_dma = esdhc_of_enable_dma,
724 .get_max_clock = esdhc_of_get_max_clock,
725 .get_min_clock = esdhc_of_get_min_clock,
726 .adma_workaround = esdhc_of_adma_workaround,
727 .set_bus_width = esdhc_pltfm_set_bus_width,
728 .reset = esdhc_reset,
729 .set_uhs_signaling = sdhci_set_uhs_signaling,
732 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
733 .quirks = ESDHC_DEFAULT_QUIRKS |
735 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
737 SDHCI_QUIRK_NO_CARD_NO_RESET |
738 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
739 .ops = &sdhci_esdhc_be_ops,
742 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
743 .quirks = ESDHC_DEFAULT_QUIRKS |
744 SDHCI_QUIRK_NO_CARD_NO_RESET |
745 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
746 .ops = &sdhci_esdhc_le_ops,
749 static struct soc_device_attribute soc_incorrect_hostver[] = {
750 { .family = "QorIQ T4240", .revision = "1.0", },
751 { .family = "QorIQ T4240", .revision = "2.0", },
755 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
757 struct sdhci_pltfm_host *pltfm_host;
758 struct sdhci_esdhc *esdhc;
759 struct device_node *np;
764 pltfm_host = sdhci_priv(host);
765 esdhc = sdhci_pltfm_priv(pltfm_host);
767 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
768 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
769 SDHCI_VENDOR_VER_SHIFT;
770 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
771 if (soc_device_match(soc_incorrect_hostver))
772 esdhc->quirk_incorrect_hostver = true;
774 esdhc->quirk_incorrect_hostver = false;
776 np = pdev->dev.of_node;
777 clk = of_clk_get(np, 0);
780 * esdhc->peripheral_clock would be assigned with a value
781 * which is eSDHC base clock when use periperal clock.
782 * For ls1046a, the clock value got by common clk API is
783 * peripheral clock while the eSDHC base clock is 1/2
786 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
787 esdhc->peripheral_clock = clk_get_rate(clk) / 2;
789 esdhc->peripheral_clock = clk_get_rate(clk);
794 if (esdhc->peripheral_clock) {
795 esdhc_clock_enable(host, false);
796 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
797 val |= ESDHC_PERIPHERAL_CLK_SEL;
798 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
799 esdhc_clock_enable(host, true);
803 static int sdhci_esdhc_probe(struct platform_device *pdev)
805 struct sdhci_host *host;
806 struct device_node *np;
807 struct sdhci_pltfm_host *pltfm_host;
808 struct sdhci_esdhc *esdhc;
811 np = pdev->dev.of_node;
813 if (of_property_read_bool(np, "little-endian"))
814 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
815 sizeof(struct sdhci_esdhc));
817 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
818 sizeof(struct sdhci_esdhc));
821 return PTR_ERR(host);
823 host->mmc_host_ops.start_signal_voltage_switch =
824 esdhc_signal_voltage_switch;
825 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
826 host->tuning_delay = 1;
828 esdhc_init(pdev, host);
830 sdhci_get_of_property(pdev);
832 pltfm_host = sdhci_priv(host);
833 esdhc = sdhci_pltfm_priv(pltfm_host);
834 if (esdhc->vendor_ver == VENDOR_V_22)
835 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
837 if (esdhc->vendor_ver > VENDOR_V_22)
838 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
840 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
841 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
842 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
843 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
844 of_device_is_compatible(np, "fsl,t1040-esdhc"))
845 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
847 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
848 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
850 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
852 * Freescale messed up with P2020 as it has a non-standard
853 * host control register
855 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
858 /* call to generic mmc_of_parse to support additional capabilities */
859 ret = mmc_of_parse(host->mmc);
863 mmc_of_parse_voltage(np, &host->ocr_mask);
865 ret = sdhci_add_host(host);
871 sdhci_pltfm_free(pdev);
875 static const struct of_device_id sdhci_esdhc_of_match[] = {
876 { .compatible = "fsl,mpc8379-esdhc" },
877 { .compatible = "fsl,mpc8536-esdhc" },
878 { .compatible = "fsl,esdhc" },
881 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
883 static struct platform_driver sdhci_esdhc_driver = {
885 .name = "sdhci-esdhc",
886 .of_match_table = sdhci_esdhc_of_match,
887 .pm = &esdhc_of_dev_pm_ops,
889 .probe = sdhci_esdhc_probe,
890 .remove = sdhci_pltfm_unregister,
893 module_platform_driver(sdhci_esdhc_driver);
895 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
896 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
897 "Anton Vorontsov <avorontsov@ru.mvista.com>");
898 MODULE_LICENSE("GPL v2");