drivers/mmc/host/sdhci-pci-core.c

   1 /*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
   2  *
   3  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or (at
   8  * your option) any later version.
   9  *
  10  * Thanks to the following companies for their support:
  11  *
  12  *     - JMicron (hardware and technical support)
  13  */
  14
  15 #include <linux/string.h>
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/device.h>
  23 #include <linux/mmc/host.h>
  24 #include <linux/mmc/mmc.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/io.h>
  27 #include <linux/gpio.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/mmc/slot-gpio.h>
  30 #include <linux/mmc/sdhci-pci-data.h>
  31 #include <linux/acpi.h>
  32
  33 #include "sdhci.h"
  34 #include "sdhci-pci.h"
  35 #include "sdhci-pci-o2micro.h"
  36
  37 static int sdhci_pci_enable_dma(struct sdhci_host *host);
  38 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width);
  39 static void sdhci_pci_hw_reset(struct sdhci_host *host);
  40
  41 #ifdef CONFIG_PM_SLEEP
  42 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
  43 {
  44         int i, ret;
  45
  46         for (i = 0; i < chip->num_slots; i++) {
  47                 struct sdhci_pci_slot *slot = chip->slots[i];
  48                 struct sdhci_host *host;
  49
  50                 if (!slot)
  51                         continue;
  52
  53                 host = slot->host;
  54
  55                 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
  56                         mmc_retune_needed(host->mmc);
  57
  58                 ret = sdhci_suspend_host(host);
  59                 if (ret)
  60                         goto err_pci_suspend;
  61
  62                 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
  63                         sdhci_enable_irq_wakeups(host);
  64         }
  65
  66         return 0;
  67
  68 err_pci_suspend:
  69         while (--i >= 0)
  70                 sdhci_resume_host(chip->slots[i]->host);
  71         return ret;
  72 }
  73
  74 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
  75 {
  76         mmc_pm_flag_t pm_flags = 0;
  77         int i;
  78
  79         for (i = 0; i < chip->num_slots; i++) {
  80                 struct sdhci_pci_slot *slot = chip->slots[i];
  81
  82                 if (slot)
  83                         pm_flags |= slot->host->mmc->pm_flags;
  84         }
  85
  86         return device_init_wakeup(&chip->pdev->dev,
  87                                   (pm_flags & MMC_PM_KEEP_POWER) &&
  88                                   (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
  89 }
  90
  91 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
  92 {
  93         int ret;
  94
  95         ret = __sdhci_pci_suspend_host(chip);
  96         if (ret)
  97                 return ret;
  98
  99         sdhci_pci_init_wakeup(chip);
 100
 101         return 0;
 102 }
 103
 104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
 105 {
 106         struct sdhci_pci_slot *slot;
 107         int i, ret;
 108
 109         for (i = 0; i < chip->num_slots; i++) {
 110                 slot = chip->slots[i];
 111                 if (!slot)
 112                         continue;
 113
 114                 ret = sdhci_resume_host(slot->host);
 115                 if (ret)
 116                         return ret;
 117         }
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 #ifdef CONFIG_PM
 124 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
 125 {
 126         struct sdhci_pci_slot *slot;
 127         struct sdhci_host *host;
 128         int i, ret;
 129
 130         for (i = 0; i < chip->num_slots; i++) {
 131                 slot = chip->slots[i];
 132                 if (!slot)
 133                         continue;
 134
 135                 host = slot->host;
 136
 137                 ret = sdhci_runtime_suspend_host(host);
 138                 if (ret)
 139                         goto err_pci_runtime_suspend;
 140
 141                 if (chip->rpm_retune &&
 142                     host->tuning_mode != SDHCI_TUNING_MODE_3)
 143                         mmc_retune_needed(host->mmc);
 144         }
 145
 146         return 0;
 147
 148 err_pci_runtime_suspend:
 149         while (--i >= 0)
 150                 sdhci_runtime_resume_host(chip->slots[i]->host);
 151         return ret;
 152 }
 153
 154 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
 155 {
 156         struct sdhci_pci_slot *slot;
 157         int i, ret;
 158
 159         for (i = 0; i < chip->num_slots; i++) {
 160                 slot = chip->slots[i];
 161                 if (!slot)
 162                         continue;
 163
 164                 ret = sdhci_runtime_resume_host(slot->host);
 165                 if (ret)
 166                         return ret;
 167         }
 168
 169         return 0;
 170 }
 171 #endif
 172
 173 /*****************************************************************************\
 174  *                                                                           *
 175  * Hardware specific quirk handling                                          *
 176  *                                                                           *
 177 \*****************************************************************************/
 178
 179 static int ricoh_probe(struct sdhci_pci_chip *chip)
 180 {
 181         if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
 182             chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
 183                 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
 184         return 0;
 185 }
 186
 187 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
 188 {
 189         slot->host->caps =
 190                 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
 191                         & SDHCI_TIMEOUT_CLK_MASK) |
 192
 193                 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
 194                         & SDHCI_CLOCK_BASE_MASK) |
 195
 196                 SDHCI_TIMEOUT_CLK_UNIT |
 197                 SDHCI_CAN_VDD_330 |
 198                 SDHCI_CAN_DO_HISPD |
 199                 SDHCI_CAN_DO_SDMA;
 200         return 0;
 201 }
 202
 203 #ifdef CONFIG_PM_SLEEP
 204 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
 205 {
 206         /* Apply a delay to allow controller to settle */
 207         /* Otherwise it becomes confused if card state changed
 208                 during suspend */
 209         msleep(500);
 210         return sdhci_pci_resume_host(chip);
 211 }
 212 #endif
 213
 214 static const struct sdhci_pci_fixes sdhci_ricoh = {
 215         .probe          = ricoh_probe,
 216         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 217                           SDHCI_QUIRK_FORCE_DMA |
 218                           SDHCI_QUIRK_CLOCK_BEFORE_RESET,
 219 };
 220
 221 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
 222         .probe_slot     = ricoh_mmc_probe_slot,
 223 #ifdef CONFIG_PM_SLEEP
 224         .resume         = ricoh_mmc_resume,
 225 #endif
 226         .quirks         = SDHCI_QUIRK_32BIT_DMA_ADDR |
 227                           SDHCI_QUIRK_CLOCK_BEFORE_RESET |
 228                           SDHCI_QUIRK_NO_CARD_NO_RESET |
 229                           SDHCI_QUIRK_MISSING_CAPS
 230 };
 231
 232 static const struct sdhci_pci_fixes sdhci_ene_712 = {
 233         .quirks         = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 234                           SDHCI_QUIRK_BROKEN_DMA,
 235 };
 236
 237 static const struct sdhci_pci_fixes sdhci_ene_714 = {
 238         .quirks         = SDHCI_QUIRK_SINGLE_POWER_WRITE |
 239                           SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
 240                           SDHCI_QUIRK_BROKEN_DMA,
 241 };
 242
 243 static const struct sdhci_pci_fixes sdhci_cafe = {
 244         .quirks         = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 245                           SDHCI_QUIRK_NO_BUSY_IRQ |
 246                           SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 247                           SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
 248 };
 249
 250 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
 251         .quirks         = SDHCI_QUIRK_NO_HISPD_BIT,
 252 };
 253
 254 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
 255 {
 256         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 257         return 0;
 258 }
 259
 260 /*
 261  * ADMA operation is disabled for Moorestown platform due to
 262  * hardware bugs.
 263  */
 264 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
 265 {
 266         /*
 267          * slots number is fixed here for MRST as SDIO3/5 are never used and
 268          * have hardware bugs.
 269          */
 270         chip->num_slots = 1;
 271         return 0;
 272 }
 273
 274 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
 275 {
 276         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 277         return 0;
 278 }
 279
 280 #ifdef CONFIG_PM
 281
 282 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
 283 {
 284         struct sdhci_pci_slot *slot = dev_id;
 285         struct sdhci_host *host = slot->host;
 286
 287         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 288         return IRQ_HANDLED;
 289 }
 290
 291 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
 292 {
 293         int err, irq, gpio = slot->cd_gpio;
 294
 295         slot->cd_gpio = -EINVAL;
 296         slot->cd_irq = -EINVAL;
 297
 298         if (!gpio_is_valid(gpio))
 299                 return;
 300
 301         err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
 302         if (err < 0)
 303                 goto out;
 304
 305         err = gpio_direction_input(gpio);
 306         if (err < 0)
 307                 goto out_free;
 308
 309         irq = gpio_to_irq(gpio);
 310         if (irq < 0)
 311                 goto out_free;
 312
 313         err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
 314                           IRQF_TRIGGER_FALLING, "sd_cd", slot);
 315         if (err)
 316                 goto out_free;
 317
 318         slot->cd_gpio = gpio;
 319         slot->cd_irq = irq;
 320
 321         return;
 322
 323 out_free:
 324         devm_gpio_free(&slot->chip->pdev->dev, gpio);
 325 out:
 326         dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
 327 }
 328
 329 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
 330 {
 331         if (slot->cd_irq >= 0)
 332                 free_irq(slot->cd_irq, slot);
 333 }
 334
 335 #else
 336
 337 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
 338 {
 339 }
 340
 341 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
 342 {
 343 }
 344
 345 #endif
 346
 347 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
 348 {
 349         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
 350         slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
 351                                   MMC_CAP2_HC_ERASE_SZ;
 352         return 0;
 353 }
 354
 355 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
 356 {
 357         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
 358         return 0;
 359 }
 360
 361 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
 362         .quirks         = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
 363         .probe_slot     = mrst_hc_probe_slot,
 364 };
 365
 366 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
 367         .quirks         = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
 368         .probe          = mrst_hc_probe,
 369 };
 370
 371 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
 372         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 373         .allow_runtime_pm = true,
 374         .own_cd_for_runtime_pm = true,
 375 };
 376
 377 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
 378         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 379         .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
 380         .allow_runtime_pm = true,
 381         .probe_slot     = mfd_sdio_probe_slot,
 382 };
 383
 384 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
 385         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 386         .allow_runtime_pm = true,
 387         .probe_slot     = mfd_emmc_probe_slot,
 388 };
 389
 390 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
 391         .quirks         = SDHCI_QUIRK_BROKEN_ADMA,
 392         .probe_slot     = pch_hc_probe_slot,
 393 };
 394
 395 enum {
 396         INTEL_DSM_FNS           =  0,
 397         INTEL_DSM_DRV_STRENGTH  =  9,
 398         INTEL_DSM_D3_RETUNE     = 10,
 399 };
 400
 401 struct intel_host {
 402         u32     dsm_fns;
 403         int     drv_strength;
 404         bool    d3_retune;
 405 };
 406
 407 const u8 intel_dsm_uuid[] = {
 408         0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46,
 409         0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61,
 410 };
 411
 412 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
 413                        unsigned int fn, u32 *result)
 414 {
 415         union acpi_object *obj;
 416         int err = 0;
 417         size_t len;
 418
 419         obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL);
 420         if (!obj)
 421                 return -EOPNOTSUPP;
 422
 423         if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
 424                 err = -EINVAL;
 425                 goto out;
 426         }
 427
 428         len = min_t(size_t, obj->buffer.length, 4);
 429
 430         *result = 0;
 431         memcpy(result, obj->buffer.pointer, len);
 432 out:
 433         ACPI_FREE(obj);
 434
 435         return err;
 436 }
 437
 438 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
 439                      unsigned int fn, u32 *result)
 440 {
 441         if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
 442                 return -EOPNOTSUPP;
 443
 444         return __intel_dsm(intel_host, dev, fn, result);
 445 }
 446
 447 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
 448                            struct mmc_host *mmc)
 449 {
 450         int err;
 451         u32 val;
 452
 453         err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
 454         if (err) {
 455                 pr_debug("%s: DSM not supported, error %d\n",
 456                          mmc_hostname(mmc), err);
 457                 return;
 458         }
 459
 460         pr_debug("%s: DSM function mask %#x\n",
 461                  mmc_hostname(mmc), intel_host->dsm_fns);
 462
 463         err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
 464         intel_host->drv_strength = err ? 0 : val;
 465
 466         err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
 467         intel_host->d3_retune = err ? true : !!val;
 468 }
 469
 470 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
 471 {
 472         u8 reg;
 473
 474         reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
 475         reg |= 0x10;
 476         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 477         /* For eMMC, minimum is 1us but give it 9us for good measure */
 478         udelay(9);
 479         reg &= ~0x10;
 480         sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 481         /* For eMMC, minimum is 200us but give it 300us for good measure */
 482         usleep_range(300, 1000);
 483 }
 484
 485 static int intel_select_drive_strength(struct mmc_card *card,
 486                                        unsigned int max_dtr, int host_drv,
 487                                        int card_drv, int *drv_type)
 488 {
 489         struct sdhci_host *host = mmc_priv(card->host);
 490         struct sdhci_pci_slot *slot = sdhci_priv(host);
 491         struct intel_host *intel_host = sdhci_pci_priv(slot);
 492
 493         return intel_host->drv_strength;
 494 }
 495
 496 static int bxt_get_cd(struct mmc_host *mmc)
 497 {
 498         int gpio_cd = mmc_gpio_get_cd(mmc);
 499         struct sdhci_host *host = mmc_priv(mmc);
 500         unsigned long flags;
 501         int ret = 0;
 502
 503         if (!gpio_cd)
 504                 return 0;
 505
 506         spin_lock_irqsave(&host->lock, flags);
 507
 508         if (host->flags & SDHCI_DEVICE_DEAD)
 509                 goto out;
 510
 511         ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
 512 out:
 513         spin_unlock_irqrestore(&host->lock, flags);
 514
 515         return ret;
 516 }
 517
 518 #define SDHCI_INTEL_PWR_TIMEOUT_CNT     20
 519 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY  100
 520
 521 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
 522                                   unsigned short vdd)
 523 {
 524         int cntr;
 525         u8 reg;
 526
 527         sdhci_set_power(host, mode, vdd);
 528
 529         if (mode == MMC_POWER_OFF)
 530                 return;
 531
 532         /*
 533          * Bus power might not enable after D3 -> D0 transition due to the
 534          * present state not yet having propagated. Retry for up to 2ms.
 535          */
 536         for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
 537                 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
 538                 if (reg & SDHCI_POWER_ON)
 539                         break;
 540                 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
 541                 reg |= SDHCI_POWER_ON;
 542                 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
 543         }
 544 }
 545
 546 static const struct sdhci_ops sdhci_intel_byt_ops = {
 547         .set_clock              = sdhci_set_clock,
 548         .set_power              = sdhci_intel_set_power,
 549         .enable_dma             = sdhci_pci_enable_dma,
 550         .set_bus_width          = sdhci_pci_set_bus_width,
 551         .reset                  = sdhci_reset,
 552         .set_uhs_signaling      = sdhci_set_uhs_signaling,
 553         .hw_reset               = sdhci_pci_hw_reset,
 554 };
 555
 556 static void byt_read_dsm(struct sdhci_pci_slot *slot)
 557 {
 558         struct intel_host *intel_host = sdhci_pci_priv(slot);
 559         struct device *dev = &slot->chip->pdev->dev;
 560         struct mmc_host *mmc = slot->host->mmc;
 561
 562         intel_dsm_init(intel_host, dev, mmc);
 563         slot->chip->rpm_retune = intel_host->d3_retune;
 564 }
 565
 566 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
 567 {
 568         byt_read_dsm(slot);
 569         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
 570                                  MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
 571                                  MMC_CAP_CMD_DURING_TFR |
 572                                  MMC_CAP_WAIT_WHILE_BUSY;
 573         slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
 574         slot->hw_reset = sdhci_pci_int_hw_reset;
 575         if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
 576                 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
 577         slot->host->mmc_host_ops.select_drive_strength =
 578                                                 intel_select_drive_strength;
 579         return 0;
 580 }
 581
 582 #ifdef CONFIG_ACPI
 583 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
 584 {
 585         acpi_status status;
 586         unsigned long long max_freq;
 587
 588         status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
 589                                        "MXFQ", NULL, &max_freq);
 590         if (ACPI_FAILURE(status)) {
 591                 dev_err(&slot->chip->pdev->dev,
 592                         "MXFQ not found in acpi table\n");
 593                 return -EINVAL;
 594         }
 595
 596         slot->host->mmc->f_max = max_freq * 1000000;
 597
 598         return 0;
 599 }
 600 #else
 601 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
 602 {
 603         return 0;
 604 }
 605 #endif
 606
 607 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 608 {
 609         int err;
 610
 611         byt_read_dsm(slot);
 612
 613         err = ni_set_max_freq(slot);
 614         if (err)
 615                 return err;
 616
 617         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
 618                                  MMC_CAP_WAIT_WHILE_BUSY;
 619         return 0;
 620 }
 621
 622 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 623 {
 624         byt_read_dsm(slot);
 625         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
 626                                  MMC_CAP_WAIT_WHILE_BUSY;
 627         return 0;
 628 }
 629
 630 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
 631 {
 632         byt_read_dsm(slot);
 633         slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
 634                                  MMC_CAP_AGGRESSIVE_PM;
 635         slot->cd_idx = 0;
 636         slot->cd_override_level = true;
 637         if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
 638             slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
 639             slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
 640             slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
 641                 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
 642
 643         return 0;
 644 }
 645
 646 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
 647         .allow_runtime_pm = true,
 648         .probe_slot     = byt_emmc_probe_slot,
 649         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 650         .quirks2        = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 651                           SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
 652                           SDHCI_QUIRK2_STOP_WITH_TC,
 653         .ops            = &sdhci_intel_byt_ops,
 654         .priv_size      = sizeof(struct intel_host),
 655 };
 656
 657 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
 658         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 659         .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
 660                           SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 661         .allow_runtime_pm = true,
 662         .probe_slot     = ni_byt_sdio_probe_slot,
 663         .ops            = &sdhci_intel_byt_ops,
 664         .priv_size      = sizeof(struct intel_host),
 665 };
 666
 667 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
 668         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 669         .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
 670                         SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 671         .allow_runtime_pm = true,
 672         .probe_slot     = byt_sdio_probe_slot,
 673         .ops            = &sdhci_intel_byt_ops,
 674         .priv_size      = sizeof(struct intel_host),
 675 };
 676
 677 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
 678         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 679         .quirks2        = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
 680                           SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 681                           SDHCI_QUIRK2_STOP_WITH_TC,
 682         .allow_runtime_pm = true,
 683         .own_cd_for_runtime_pm = true,
 684         .probe_slot     = byt_sd_probe_slot,
 685         .ops            = &sdhci_intel_byt_ops,
 686         .priv_size      = sizeof(struct intel_host),
 687 };
 688
 689 /* Define Host controllers for Intel Merrifield platform */
 690 #define INTEL_MRFLD_EMMC_0      0
 691 #define INTEL_MRFLD_EMMC_1      1
 692 #define INTEL_MRFLD_SD          2
 693 #define INTEL_MRFLD_SDIO        3
 694
 695 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
 696 {
 697         unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
 698
 699         switch (func) {
 700         case INTEL_MRFLD_EMMC_0:
 701         case INTEL_MRFLD_EMMC_1:
 702                 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
 703                                          MMC_CAP_8_BIT_DATA |
 704                                          MMC_CAP_1_8V_DDR;
 705                 break;
 706         case INTEL_MRFLD_SD:
 707                 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
 708                 break;
 709         case INTEL_MRFLD_SDIO:
 710                 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
 711                                          MMC_CAP_POWER_OFF_CARD;
 712                 break;
 713         default:
 714                 return -ENODEV;
 715         }
 716         return 0;
 717 }
 718
 719 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
 720         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 721         .quirks2        = SDHCI_QUIRK2_BROKEN_HS200 |
 722                         SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 723         .allow_runtime_pm = true,
 724         .probe_slot     = intel_mrfld_mmc_probe_slot,
 725 };
 726
 727 /* O2Micro extra registers */
 728 #define O2_SD_LOCK_WP           0xD3
 729 #define O2_SD_MULTI_VCC3V       0xEE
 730 #define O2_SD_CLKREQ            0xEC
 731 #define O2_SD_CAPS              0xE0
 732 #define O2_SD_ADMA1             0xE2
 733 #define O2_SD_ADMA2             0xE7
 734 #define O2_SD_INF_MOD           0xF1
 735
 736 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
 737 {
 738         u8 scratch;
 739         int ret;
 740
 741         ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
 742         if (ret)
 743                 return ret;
 744
 745         /*
 746          * Turn PMOS on [bit 0], set over current detection to 2.4 V
 747          * [bit 1:2] and enable over current debouncing [bit 6].
 748          */
 749         if (on)
 750                 scratch |= 0x47;
 751         else
 752                 scratch &= ~0x47;
 753
 754         return pci_write_config_byte(chip->pdev, 0xAE, scratch);
 755 }
 756
 757 static int jmicron_probe(struct sdhci_pci_chip *chip)
 758 {
 759         int ret;
 760         u16 mmcdev = 0;
 761
 762         if (chip->pdev->revision == 0) {
 763                 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
 764                           SDHCI_QUIRK_32BIT_DMA_SIZE |
 765                           SDHCI_QUIRK_32BIT_ADMA_SIZE |
 766                           SDHCI_QUIRK_RESET_AFTER_REQUEST |
 767                           SDHCI_QUIRK_BROKEN_SMALL_PIO;
 768         }
 769
 770         /*
 771          * JMicron chips can have two interfaces to the same hardware
 772          * in order to work around limitations in Microsoft's driver.
 773          * We need to make sure we only bind to one of them.
 774          *
 775          * This code assumes two things:
 776          *
 777          * 1. The PCI code adds subfunctions in order.
 778          *
 779          * 2. The MMC interface has a lower subfunction number
 780          *    than the SD interface.
 781          */
 782         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
 783                 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
 784         else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
 785                 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
 786
 787         if (mmcdev) {
 788                 struct pci_dev *sd_dev;
 789
 790                 sd_dev = NULL;
 791                 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
 792                                                 mmcdev, sd_dev)) != NULL) {
 793                         if ((PCI_SLOT(chip->pdev->devfn) ==
 794                                 PCI_SLOT(sd_dev->devfn)) &&
 795                                 (chip->pdev->bus == sd_dev->bus))
 796                                 break;
 797                 }
 798
 799                 if (sd_dev) {
 800                         pci_dev_put(sd_dev);
 801                         dev_info(&chip->pdev->dev, "Refusing to bind to "
 802                                 "secondary interface.\n");
 803                         return -ENODEV;
 804                 }
 805         }
 806
 807         /*
 808          * JMicron chips need a bit of a nudge to enable the power
 809          * output pins.
 810          */
 811         ret = jmicron_pmos(chip, 1);
 812         if (ret) {
 813                 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
 814                 return ret;
 815         }
 816
 817         /* quirk for unsable RO-detection on JM388 chips */
 818         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
 819             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
 820                 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
 821
 822         return 0;
 823 }
 824
 825 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
 826 {
 827         u8 scratch;
 828
 829         scratch = readb(host->ioaddr + 0xC0);
 830
 831         if (on)
 832                 scratch |= 0x01;
 833         else
 834                 scratch &= ~0x01;
 835
 836         writeb(scratch, host->ioaddr + 0xC0);
 837 }
 838
 839 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
 840 {
 841         if (slot->chip->pdev->revision == 0) {
 842                 u16 version;
 843
 844                 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
 845                 version = (version & SDHCI_VENDOR_VER_MASK) >>
 846                         SDHCI_VENDOR_VER_SHIFT;
 847
 848                 /*
 849                  * Older versions of the chip have lots of nasty glitches
 850                  * in the ADMA engine. It's best just to avoid it
 851                  * completely.
 852                  */
 853                 if (version < 0xAC)
 854                         slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
 855         }
 856
 857         /* JM388 MMC doesn't support 1.8V while SD supports it */
 858         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
 859                 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
 860                         MMC_VDD_29_30 | MMC_VDD_30_31 |
 861                         MMC_VDD_165_195; /* allow 1.8V */
 862                 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
 863                         MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
 864         }
 865
 866         /*
 867          * The secondary interface requires a bit set to get the
 868          * interrupts.
 869          */
 870         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
 871             slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
 872                 jmicron_enable_mmc(slot->host, 1);
 873
 874         slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
 875
 876         return 0;
 877 }
 878
 879 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
 880 {
 881         if (dead)
 882                 return;
 883
 884         if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
 885             slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
 886                 jmicron_enable_mmc(slot->host, 0);
 887 }
 888
 889 #ifdef CONFIG_PM_SLEEP
 890 static int jmicron_suspend(struct sdhci_pci_chip *chip)
 891 {
 892         int i, ret;
 893
 894         ret = __sdhci_pci_suspend_host(chip);
 895         if (ret)
 896                 return ret;
 897
 898         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
 899             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
 900                 for (i = 0; i < chip->num_slots; i++)
 901                         jmicron_enable_mmc(chip->slots[i]->host, 0);
 902         }
 903
 904         sdhci_pci_init_wakeup(chip);
 905
 906         return 0;
 907 }
 908
 909 static int jmicron_resume(struct sdhci_pci_chip *chip)
 910 {
 911         int ret, i;
 912
 913         if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
 914             chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
 915                 for (i = 0; i < chip->num_slots; i++)
 916                         jmicron_enable_mmc(chip->slots[i]->host, 1);
 917         }
 918
 919         ret = jmicron_pmos(chip, 1);
 920         if (ret) {
 921                 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
 922                 return ret;
 923         }
 924
 925         return sdhci_pci_resume_host(chip);
 926 }
 927 #endif
 928
 929 static const struct sdhci_pci_fixes sdhci_o2 = {
 930         .probe = sdhci_pci_o2_probe,
 931         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 932         .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
 933         .probe_slot = sdhci_pci_o2_probe_slot,
 934 #ifdef CONFIG_PM_SLEEP
 935         .resume = sdhci_pci_o2_resume,
 936 #endif
 937 };
 938
 939 static const struct sdhci_pci_fixes sdhci_jmicron = {
 940         .probe          = jmicron_probe,
 941
 942         .probe_slot     = jmicron_probe_slot,
 943         .remove_slot    = jmicron_remove_slot,
 944
 945 #ifdef CONFIG_PM_SLEEP
 946         .suspend        = jmicron_suspend,
 947         .resume         = jmicron_resume,
 948 #endif
 949 };
 950
 951 /* SysKonnect CardBus2SDIO extra registers */
 952 #define SYSKT_CTRL              0x200
 953 #define SYSKT_RDFIFO_STAT       0x204
 954 #define SYSKT_WRFIFO_STAT       0x208
 955 #define SYSKT_POWER_DATA        0x20c
 956 #define   SYSKT_POWER_330       0xef
 957 #define   SYSKT_POWER_300       0xf8
 958 #define   SYSKT_POWER_184       0xcc
 959 #define SYSKT_POWER_CMD         0x20d
 960 #define   SYSKT_POWER_START     (1 << 7)
 961 #define SYSKT_POWER_STATUS      0x20e
 962 #define   SYSKT_POWER_STATUS_OK (1 << 0)
 963 #define SYSKT_BOARD_REV         0x210
 964 #define SYSKT_CHIP_REV          0x211
 965 #define SYSKT_CONF_DATA         0x212
 966 #define   SYSKT_CONF_DATA_1V8   (1 << 2)
 967 #define   SYSKT_CONF_DATA_2V5   (1 << 1)
 968 #define   SYSKT_CONF_DATA_3V3   (1 << 0)
 969
 970 static int syskt_probe(struct sdhci_pci_chip *chip)
 971 {
 972         if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
 973                 chip->pdev->class &= ~0x0000FF;
 974                 chip->pdev->class |= PCI_SDHCI_IFDMA;
 975         }
 976         return 0;
 977 }
 978
 979 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
 980 {
 981         int tm, ps;
 982
 983         u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
 984         u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
 985         dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
 986                                          "board rev %d.%d, chip rev %d.%d\n",
 987                                          board_rev >> 4, board_rev & 0xf,
 988                                          chip_rev >> 4,  chip_rev & 0xf);
 989         if (chip_rev >= 0x20)
 990                 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
 991
 992         writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
 993         writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
 994         udelay(50);
 995         tm = 10;  /* Wait max 1 ms */
 996         do {
 997                 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
 998                 if (ps & SYSKT_POWER_STATUS_OK)
 999                         break;
1000                 udelay(100);
1001         } while (--tm);
1002         if (!tm) {
1003                 dev_err(&slot->chip->pdev->dev,
1004                         "power regulator never stabilized");
1005                 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1006                 return -ENODEV;
1007         }
1008
1009         return 0;
1010 }
1011
1012 static const struct sdhci_pci_fixes sdhci_syskt = {
1013         .quirks         = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1014         .probe          = syskt_probe,
1015         .probe_slot     = syskt_probe_slot,
1016 };
1017
1018 static int via_probe(struct sdhci_pci_chip *chip)
1019 {
1020         if (chip->pdev->revision == 0x10)
1021                 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1022
1023         return 0;
1024 }
1025
1026 static const struct sdhci_pci_fixes sdhci_via = {
1027         .probe          = via_probe,
1028 };
1029
1030 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1031 {
1032         slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1033         return 0;
1034 }
1035
1036 static const struct sdhci_pci_fixes sdhci_rtsx = {
1037         .quirks2        = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1038                         SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1039                         SDHCI_QUIRK2_BROKEN_DDR50,
1040         .probe_slot     = rtsx_probe_slot,
1041 };
1042
1043 /*AMD chipset generation*/
1044 enum amd_chipset_gen {
1045         AMD_CHIPSET_BEFORE_ML,
1046         AMD_CHIPSET_CZ,
1047         AMD_CHIPSET_NL,
1048         AMD_CHIPSET_UNKNOWN,
1049 };
1050
1051 /* AMD registers */
1052 #define AMD_SD_AUTO_PATTERN             0xB8
1053 #define AMD_MSLEEP_DURATION             4
1054 #define AMD_SD_MISC_CONTROL             0xD0
1055 #define AMD_MAX_TUNE_VALUE              0x0B
1056 #define AMD_AUTO_TUNE_SEL               0x10800
1057 #define AMD_FIFO_PTR                    0x30
1058 #define AMD_BIT_MASK                    0x1F
1059
1060 static void amd_tuning_reset(struct sdhci_host *host)
1061 {
1062         unsigned int val;
1063
1064         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1065         val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1066         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1067
1068         val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1069         val &= ~SDHCI_CTRL_EXEC_TUNING;
1070         sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1071 }
1072
1073 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1074 {
1075         unsigned int val;
1076
1077         pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1078         val &= ~AMD_BIT_MASK;
1079         val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1080         pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1081 }
1082
1083 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1084 {
1085         unsigned int val;
1086
1087         pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1088         val |= AMD_FIFO_PTR;
1089         pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1090 }
1091
1092 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1093 {
1094         struct sdhci_pci_slot *slot = sdhci_priv(host);
1095         struct pci_dev *pdev = slot->chip->pdev;
1096         u8 valid_win = 0;
1097         u8 valid_win_max = 0;
1098         u8 valid_win_end = 0;
1099         u8 ctrl, tune_around;
1100
1101         amd_tuning_reset(host);
1102
1103         for (tune_around = 0; tune_around < 12; tune_around++) {
1104                 amd_config_tuning_phase(pdev, tune_around);
1105
1106                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1107                         valid_win = 0;
1108                         msleep(AMD_MSLEEP_DURATION);
1109                         ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1110                         sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1111                 } else if (++valid_win > valid_win_max) {
1112                         valid_win_max = valid_win;
1113                         valid_win_end = tune_around;
1114                 }
1115         }
1116
1117         if (!valid_win_max) {
1118                 dev_err(&pdev->dev, "no tuning point found\n");
1119                 return -EIO;
1120         }
1121
1122         amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1123
1124         amd_enable_manual_tuning(pdev);
1125
1126         host->mmc->retune_period = 0;
1127
1128         return 0;
1129 }
1130
1131 static int amd_probe(struct sdhci_pci_chip *chip)
1132 {
1133         struct pci_dev  *smbus_dev;
1134         enum amd_chipset_gen gen;
1135
1136         smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1137                         PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1138         if (smbus_dev) {
1139                 gen = AMD_CHIPSET_BEFORE_ML;
1140         } else {
1141                 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1142                                 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1143                 if (smbus_dev) {
1144                         if (smbus_dev->revision < 0x51)
1145                                 gen = AMD_CHIPSET_CZ;
1146                         else
1147                                 gen = AMD_CHIPSET_NL;
1148                 } else {
1149                         gen = AMD_CHIPSET_UNKNOWN;
1150                 }
1151         }
1152
1153         if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1154                 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1155
1156         return 0;
1157 }
1158
1159 static const struct sdhci_ops amd_sdhci_pci_ops = {
1160         .set_clock                      = sdhci_set_clock,
1161         .enable_dma                     = sdhci_pci_enable_dma,
1162         .set_bus_width                  = sdhci_pci_set_bus_width,
1163         .reset                          = sdhci_reset,
1164         .set_uhs_signaling              = sdhci_set_uhs_signaling,
1165         .platform_execute_tuning        = amd_execute_tuning,
1166 };
1167
1168 static const struct sdhci_pci_fixes sdhci_amd = {
1169         .probe          = amd_probe,
1170         .ops            = &amd_sdhci_pci_ops,
1171 };
1172
1173 static const struct pci_device_id pci_ids[] = {
1174         {
1175                 .vendor         = PCI_VENDOR_ID_RICOH,
1176                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
1177                 .subvendor      = PCI_ANY_ID,
1178                 .subdevice      = PCI_ANY_ID,
1179                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh,
1180         },
1181
1182         {
1183                 .vendor         = PCI_VENDOR_ID_RICOH,
1184                 .device         = 0x843,
1185                 .subvendor      = PCI_ANY_ID,
1186                 .subdevice      = PCI_ANY_ID,
1187                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
1188         },
1189
1190         {
1191                 .vendor         = PCI_VENDOR_ID_RICOH,
1192                 .device         = 0xe822,
1193                 .subvendor      = PCI_ANY_ID,
1194                 .subdevice      = PCI_ANY_ID,
1195                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
1196         },
1197
1198         {
1199                 .vendor         = PCI_VENDOR_ID_RICOH,
1200                 .device         = 0xe823,
1201                 .subvendor      = PCI_ANY_ID,
1202                 .subdevice      = PCI_ANY_ID,
1203                 .driver_data    = (kernel_ulong_t)&sdhci_ricoh_mmc,
1204         },
1205
1206         {
1207                 .vendor         = PCI_VENDOR_ID_ENE,
1208                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
1209                 .subvendor      = PCI_ANY_ID,
1210                 .subdevice      = PCI_ANY_ID,
1211                 .driver_data    = (kernel_ulong_t)&sdhci_ene_712,
1212         },
1213
1214         {
1215                 .vendor         = PCI_VENDOR_ID_ENE,
1216                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
1217                 .subvendor      = PCI_ANY_ID,
1218                 .subdevice      = PCI_ANY_ID,
1219                 .driver_data    = (kernel_ulong_t)&sdhci_ene_712,
1220         },
1221
1222         {
1223                 .vendor         = PCI_VENDOR_ID_ENE,
1224                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
1225                 .subvendor      = PCI_ANY_ID,
1226                 .subdevice      = PCI_ANY_ID,
1227                 .driver_data    = (kernel_ulong_t)&sdhci_ene_714,
1228         },
1229
1230         {
1231                 .vendor         = PCI_VENDOR_ID_ENE,
1232                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
1233                 .subvendor      = PCI_ANY_ID,
1234                 .subdevice      = PCI_ANY_ID,
1235                 .driver_data    = (kernel_ulong_t)&sdhci_ene_714,
1236         },
1237
1238         {
1239                 .vendor         = PCI_VENDOR_ID_MARVELL,
1240                 .device         = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
1241                 .subvendor      = PCI_ANY_ID,
1242                 .subdevice      = PCI_ANY_ID,
1243                 .driver_data    = (kernel_ulong_t)&sdhci_cafe,
1244         },
1245
1246         {
1247                 .vendor         = PCI_VENDOR_ID_JMICRON,
1248                 .device         = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
1249                 .subvendor      = PCI_ANY_ID,
1250                 .subdevice      = PCI_ANY_ID,
1251                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
1252         },
1253
1254         {
1255                 .vendor         = PCI_VENDOR_ID_JMICRON,
1256                 .device         = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
1257                 .subvendor      = PCI_ANY_ID,
1258                 .subdevice      = PCI_ANY_ID,
1259                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
1260         },
1261
1262         {
1263                 .vendor         = PCI_VENDOR_ID_JMICRON,
1264                 .device         = PCI_DEVICE_ID_JMICRON_JMB388_SD,
1265                 .subvendor      = PCI_ANY_ID,
1266                 .subdevice      = PCI_ANY_ID,
1267                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
1268         },
1269
1270         {
1271                 .vendor         = PCI_VENDOR_ID_JMICRON,
1272                 .device         = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
1273                 .subvendor      = PCI_ANY_ID,
1274                 .subdevice      = PCI_ANY_ID,
1275                 .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
1276         },
1277
1278         {
1279                 .vendor         = PCI_VENDOR_ID_SYSKONNECT,
1280                 .device         = 0x8000,
1281                 .subvendor      = PCI_ANY_ID,
1282                 .subdevice      = PCI_ANY_ID,
1283                 .driver_data    = (kernel_ulong_t)&sdhci_syskt,
1284         },
1285
1286         {
1287                 .vendor         = PCI_VENDOR_ID_VIA,
1288                 .device         = 0x95d0,
1289                 .subvendor      = PCI_ANY_ID,
1290                 .subdevice      = PCI_ANY_ID,
1291                 .driver_data    = (kernel_ulong_t)&sdhci_via,
1292         },
1293
1294         {
1295                 .vendor         = PCI_VENDOR_ID_REALTEK,
1296                 .device         = 0x5250,
1297                 .subvendor      = PCI_ANY_ID,
1298                 .subdevice      = PCI_ANY_ID,
1299                 .driver_data    = (kernel_ulong_t)&sdhci_rtsx,
1300         },
1301
1302         {
1303                 .vendor         = PCI_VENDOR_ID_INTEL,
1304                 .device         = PCI_DEVICE_ID_INTEL_QRK_SD,
1305                 .subvendor      = PCI_ANY_ID,
1306                 .subdevice      = PCI_ANY_ID,
1307                 .driver_data    = (kernel_ulong_t)&sdhci_intel_qrk,
1308         },
1309
1310         {
1311                 .vendor         = PCI_VENDOR_ID_INTEL,
1312                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD0,
1313                 .subvendor      = PCI_ANY_ID,
1314                 .subdevice      = PCI_ANY_ID,
1315                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
1316         },
1317
1318         {
1319                 .vendor         = PCI_VENDOR_ID_INTEL,
1320                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD1,
1321                 .subvendor      = PCI_ANY_ID,
1322                 .subdevice      = PCI_ANY_ID,
1323                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
1324         },
1325
1326         {
1327                 .vendor         = PCI_VENDOR_ID_INTEL,
1328                 .device         = PCI_DEVICE_ID_INTEL_MRST_SD2,
1329                 .subvendor      = PCI_ANY_ID,
1330                 .subdevice      = PCI_ANY_ID,
1331                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
1332         },
1333
1334         {
1335                 .vendor         = PCI_VENDOR_ID_INTEL,
1336                 .device         = PCI_DEVICE_ID_INTEL_MFD_SD,
1337                 .subvendor      = PCI_ANY_ID,
1338                 .subdevice      = PCI_ANY_ID,
1339                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1340         },
1341
1342         {
1343                 .vendor         = PCI_VENDOR_ID_INTEL,
1344                 .device         = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
1345                 .subvendor      = PCI_ANY_ID,
1346                 .subdevice      = PCI_ANY_ID,
1347                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1348         },
1349
1350         {
1351                 .vendor         = PCI_VENDOR_ID_INTEL,
1352                 .device         = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
1353                 .subvendor      = PCI_ANY_ID,
1354                 .subdevice      = PCI_ANY_ID,
1355                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1356         },
1357
1358         {
1359                 .vendor         = PCI_VENDOR_ID_INTEL,
1360                 .device         = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
1361                 .subvendor      = PCI_ANY_ID,
1362                 .subdevice      = PCI_ANY_ID,
1363                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1364         },
1365
1366         {
1367                 .vendor         = PCI_VENDOR_ID_INTEL,
1368                 .device         = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
1369                 .subvendor      = PCI_ANY_ID,
1370                 .subdevice      = PCI_ANY_ID,
1371                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1372         },
1373
1374         {
1375                 .vendor         = PCI_VENDOR_ID_INTEL,
1376                 .device         = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1377                 .subvendor      = PCI_ANY_ID,
1378                 .subdevice      = PCI_ANY_ID,
1379                 .driver_data    = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1380         },
1381
1382         {
1383                 .vendor         = PCI_VENDOR_ID_INTEL,
1384                 .device         = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1385                 .subvendor      = PCI_ANY_ID,
1386                 .subdevice      = PCI_ANY_ID,
1387                 .driver_data    = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1388         },
1389
1390         {
1391                 .vendor         = PCI_VENDOR_ID_INTEL,
1392                 .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1393                 .subvendor      = PCI_ANY_ID,
1394                 .subdevice      = PCI_ANY_ID,
1395                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1396         },
1397
1398         {
1399                 .vendor         = PCI_VENDOR_ID_INTEL,
1400                 .device         = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1401                 .subvendor      = PCI_VENDOR_ID_NI,
1402                 .subdevice      = 0x7884,
1403                 .driver_data    = (kernel_ulong_t)&sdhci_ni_byt_sdio,
1404         },
1405
1406         {
1407                 .vendor         = PCI_VENDOR_ID_INTEL,
1408                 .device         = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1409                 .subvendor      = PCI_ANY_ID,
1410                 .subdevice      = PCI_ANY_ID,
1411                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1412         },
1413
1414         {
1415                 .vendor         = PCI_VENDOR_ID_INTEL,
1416                 .device         = PCI_DEVICE_ID_INTEL_BYT_SD,
1417                 .subvendor      = PCI_ANY_ID,
1418                 .subdevice      = PCI_ANY_ID,
1419                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1420         },
1421
1422         {
1423                 .vendor         = PCI_VENDOR_ID_INTEL,
1424                 .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1425                 .subvendor      = PCI_ANY_ID,
1426                 .subdevice      = PCI_ANY_ID,
1427                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1428         },
1429
1430         {
1431                 .vendor         = PCI_VENDOR_ID_INTEL,
1432                 .device         = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1433                 .subvendor      = PCI_ANY_ID,
1434                 .subdevice      = PCI_ANY_ID,
1435                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1436         },
1437
1438         {
1439                 .vendor         = PCI_VENDOR_ID_INTEL,
1440                 .device         = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1441                 .subvendor      = PCI_ANY_ID,
1442                 .subdevice      = PCI_ANY_ID,
1443                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1444         },
1445
1446         {
1447                 .vendor         = PCI_VENDOR_ID_INTEL,
1448                 .device         = PCI_DEVICE_ID_INTEL_BSW_SD,
1449                 .subvendor      = PCI_ANY_ID,
1450                 .subdevice      = PCI_ANY_ID,
1451                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1452         },
1453
1454         {
1455                 .vendor         = PCI_VENDOR_ID_INTEL,
1456                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1457                 .subvendor      = PCI_ANY_ID,
1458                 .subdevice      = PCI_ANY_ID,
1459                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1460         },
1461
1462         {
1463                 .vendor         = PCI_VENDOR_ID_INTEL,
1464                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1465                 .subvendor      = PCI_ANY_ID,
1466                 .subdevice      = PCI_ANY_ID,
1467                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1468         },
1469
1470         {
1471                 .vendor         = PCI_VENDOR_ID_INTEL,
1472                 .device         = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1473                 .subvendor      = PCI_ANY_ID,
1474                 .subdevice      = PCI_ANY_ID,
1475                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1476         },
1477
1478         {
1479                 .vendor         = PCI_VENDOR_ID_INTEL,
1480                 .device         = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1481                 .subvendor      = PCI_ANY_ID,
1482                 .subdevice      = PCI_ANY_ID,
1483                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1484         },
1485
1486         {
1487                 .vendor         = PCI_VENDOR_ID_INTEL,
1488                 .device         = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1489                 .subvendor      = PCI_ANY_ID,
1490                 .subdevice      = PCI_ANY_ID,
1491                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1492         },
1493
1494         {
1495                 .vendor         = PCI_VENDOR_ID_INTEL,
1496                 .device         = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
1497                 .subvendor      = PCI_ANY_ID,
1498                 .subdevice      = PCI_ANY_ID,
1499                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
1500         },
1501
1502         {
1503                 .vendor         = PCI_VENDOR_ID_INTEL,
1504                 .device         = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1505                 .subvendor      = PCI_ANY_ID,
1506                 .subdevice      = PCI_ANY_ID,
1507                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1508         },
1509
1510         {
1511                 .vendor         = PCI_VENDOR_ID_INTEL,
1512                 .device         = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1513                 .subvendor      = PCI_ANY_ID,
1514                 .subdevice      = PCI_ANY_ID,
1515                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1516         },
1517
1518         {
1519                 .vendor         = PCI_VENDOR_ID_INTEL,
1520                 .device         = PCI_DEVICE_ID_INTEL_SPT_SD,
1521                 .subvendor      = PCI_ANY_ID,
1522                 .subdevice      = PCI_ANY_ID,
1523                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1524         },
1525
1526         {
1527                 .vendor         = PCI_VENDOR_ID_INTEL,
1528                 .device         = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1529                 .subvendor      = PCI_ANY_ID,
1530                 .subdevice      = PCI_ANY_ID,
1531                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1532         },
1533
1534         {
1535                 .vendor         = PCI_VENDOR_ID_INTEL,
1536                 .device         = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1537                 .subvendor      = PCI_ANY_ID,
1538                 .subdevice      = PCI_ANY_ID,
1539                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1540         },
1541
1542         {
1543                 .vendor         = PCI_VENDOR_ID_INTEL,
1544                 .device         = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1545                 .subvendor      = PCI_ANY_ID,
1546                 .subdevice      = PCI_ANY_ID,
1547                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1548         },
1549
1550         {
1551                 .vendor         = PCI_VENDOR_ID_INTEL,
1552                 .device         = PCI_DEVICE_ID_INTEL_BXT_SD,
1553                 .subvendor      = PCI_ANY_ID,
1554                 .subdevice      = PCI_ANY_ID,
1555                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1556         },
1557
1558         {
1559                 .vendor         = PCI_VENDOR_ID_INTEL,
1560                 .device         = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1561                 .subvendor      = PCI_ANY_ID,
1562                 .subdevice      = PCI_ANY_ID,
1563                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1564         },
1565
1566         {
1567                 .vendor         = PCI_VENDOR_ID_INTEL,
1568                 .device         = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1569                 .subvendor      = PCI_ANY_ID,
1570                 .subdevice      = PCI_ANY_ID,
1571                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1572         },
1573
1574         {
1575                 .vendor         = PCI_VENDOR_ID_INTEL,
1576                 .device         = PCI_DEVICE_ID_INTEL_BXTM_SD,
1577                 .subvendor      = PCI_ANY_ID,
1578                 .subdevice      = PCI_ANY_ID,
1579                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1580         },
1581
1582         {
1583                 .vendor         = PCI_VENDOR_ID_INTEL,
1584                 .device         = PCI_DEVICE_ID_INTEL_APL_EMMC,
1585                 .subvendor      = PCI_ANY_ID,
1586                 .subdevice      = PCI_ANY_ID,
1587                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1588         },
1589
1590         {
1591                 .vendor         = PCI_VENDOR_ID_INTEL,
1592                 .device         = PCI_DEVICE_ID_INTEL_APL_SDIO,
1593                 .subvendor      = PCI_ANY_ID,
1594                 .subdevice      = PCI_ANY_ID,
1595                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1596         },
1597
1598         {
1599                 .vendor         = PCI_VENDOR_ID_INTEL,
1600                 .device         = PCI_DEVICE_ID_INTEL_APL_SD,
1601                 .subvendor      = PCI_ANY_ID,
1602                 .subdevice      = PCI_ANY_ID,
1603                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1604         },
1605
1606         {
1607                 .vendor         = PCI_VENDOR_ID_INTEL,
1608                 .device         = PCI_DEVICE_ID_INTEL_GLK_EMMC,
1609                 .subvendor      = PCI_ANY_ID,
1610                 .subdevice      = PCI_ANY_ID,
1611                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1612         },
1613
1614         {
1615                 .vendor         = PCI_VENDOR_ID_INTEL,
1616                 .device         = PCI_DEVICE_ID_INTEL_GLK_SDIO,
1617                 .subvendor      = PCI_ANY_ID,
1618                 .subdevice      = PCI_ANY_ID,
1619                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1620         },
1621
1622         {
1623                 .vendor         = PCI_VENDOR_ID_INTEL,
1624                 .device         = PCI_DEVICE_ID_INTEL_GLK_SD,
1625                 .subvendor      = PCI_ANY_ID,
1626                 .subdevice      = PCI_ANY_ID,
1627                 .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
1628         },
1629
1630         {
1631                 .vendor         = PCI_VENDOR_ID_O2,
1632                 .device         = PCI_DEVICE_ID_O2_8120,
1633                 .subvendor      = PCI_ANY_ID,
1634                 .subdevice      = PCI_ANY_ID,
1635                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1636         },
1637
1638         {
1639                 .vendor         = PCI_VENDOR_ID_O2,
1640                 .device         = PCI_DEVICE_ID_O2_8220,
1641                 .subvendor      = PCI_ANY_ID,
1642                 .subdevice      = PCI_ANY_ID,
1643                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1644         },
1645
1646         {
1647                 .vendor         = PCI_VENDOR_ID_O2,
1648                 .device         = PCI_DEVICE_ID_O2_8221,
1649                 .subvendor      = PCI_ANY_ID,
1650                 .subdevice      = PCI_ANY_ID,
1651                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1652         },
1653
1654         {
1655                 .vendor         = PCI_VENDOR_ID_O2,
1656                 .device         = PCI_DEVICE_ID_O2_8320,
1657                 .subvendor      = PCI_ANY_ID,
1658                 .subdevice      = PCI_ANY_ID,
1659                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1660         },
1661
1662         {
1663                 .vendor         = PCI_VENDOR_ID_O2,
1664                 .device         = PCI_DEVICE_ID_O2_8321,
1665                 .subvendor      = PCI_ANY_ID,
1666                 .subdevice      = PCI_ANY_ID,
1667                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1668         },
1669
1670         {
1671                 .vendor         = PCI_VENDOR_ID_O2,
1672                 .device         = PCI_DEVICE_ID_O2_FUJIN2,
1673                 .subvendor      = PCI_ANY_ID,
1674                 .subdevice      = PCI_ANY_ID,
1675                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1676         },
1677
1678         {
1679                 .vendor         = PCI_VENDOR_ID_O2,
1680                 .device         = PCI_DEVICE_ID_O2_SDS0,
1681                 .subvendor      = PCI_ANY_ID,
1682                 .subdevice      = PCI_ANY_ID,
1683                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1684         },
1685
1686         {
1687                 .vendor         = PCI_VENDOR_ID_O2,
1688                 .device         = PCI_DEVICE_ID_O2_SDS1,
1689                 .subvendor      = PCI_ANY_ID,
1690                 .subdevice      = PCI_ANY_ID,
1691                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1692         },
1693
1694         {
1695                 .vendor         = PCI_VENDOR_ID_O2,
1696                 .device         = PCI_DEVICE_ID_O2_SEABIRD0,
1697                 .subvendor      = PCI_ANY_ID,
1698                 .subdevice      = PCI_ANY_ID,
1699                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1700         },
1701
1702         {
1703                 .vendor         = PCI_VENDOR_ID_O2,
1704                 .device         = PCI_DEVICE_ID_O2_SEABIRD1,
1705                 .subvendor      = PCI_ANY_ID,
1706                 .subdevice      = PCI_ANY_ID,
1707                 .driver_data    = (kernel_ulong_t)&sdhci_o2,
1708         },
1709         {
1710                 .vendor         = PCI_VENDOR_ID_AMD,
1711                 .device         = PCI_ANY_ID,
1712                 .class          = PCI_CLASS_SYSTEM_SDHCI << 8,
1713                 .class_mask     = 0xFFFF00,
1714                 .subvendor      = PCI_ANY_ID,
1715                 .subdevice      = PCI_ANY_ID,
1716                 .driver_data    = (kernel_ulong_t)&sdhci_amd,
1717         },
1718         {       /* Generic SD host controller */
1719                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1720         },
1721
1722         { /* end: all zeroes */ },
1723 };
1724
1725 MODULE_DEVICE_TABLE(pci, pci_ids);
1726
1727 /*****************************************************************************\
1728  *                                                                           *
1729  * SDHCI core callbacks                                                      *
1730  *                                                                           *
1731 \*****************************************************************************/
1732
1733 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1734 {
1735         struct sdhci_pci_slot *slot;
1736         struct pci_dev *pdev;
1737
1738         slot = sdhci_priv(host);
1739         pdev = slot->chip->pdev;
1740
1741         if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1742                 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1743                 (host->flags & SDHCI_USE_SDMA)) {
1744                 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1745                         "doesn't fully claim to support it.\n");
1746         }
1747
1748         pci_set_master(pdev);
1749
1750         return 0;
1751 }
1752
1753 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1754 {
1755         u8 ctrl;
1756
1757         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1758
1759         switch (width) {
1760         case MMC_BUS_WIDTH_8:
1761                 ctrl |= SDHCI_CTRL_8BITBUS;
1762                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1763                 break;
1764         case MMC_BUS_WIDTH_4:
1765                 ctrl |= SDHCI_CTRL_4BITBUS;
1766                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1767                 break;
1768         default:
1769                 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1770                 break;
1771         }
1772
1773         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1774 }
1775
1776 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1777 {
1778         struct sdhci_pci_slot *slot = sdhci_priv(host);
1779         int rst_n_gpio = slot->rst_n_gpio;
1780
1781         if (!gpio_is_valid(rst_n_gpio))
1782                 return;
1783         gpio_set_value_cansleep(rst_n_gpio, 0);
1784         /* For eMMC, minimum is 1us but give it 10us for good measure */
1785         udelay(10);
1786         gpio_set_value_cansleep(rst_n_gpio, 1);
1787         /* For eMMC, minimum is 200us but give it 300us for good measure */
1788         usleep_range(300, 1000);
1789 }
1790
1791 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1792 {
1793         struct sdhci_pci_slot *slot = sdhci_priv(host);
1794
1795         if (slot->hw_reset)
1796                 slot->hw_reset(host);
1797 }
1798
1799 static const struct sdhci_ops sdhci_pci_ops = {
1800         .set_clock      = sdhci_set_clock,
1801         .enable_dma     = sdhci_pci_enable_dma,
1802         .set_bus_width  = sdhci_pci_set_bus_width,
1803         .reset          = sdhci_reset,
1804         .set_uhs_signaling = sdhci_set_uhs_signaling,
1805         .hw_reset               = sdhci_pci_hw_reset,
1806 };
1807
1808 /*****************************************************************************\
1809  *                                                                           *
1810  * Suspend/resume                                                            *
1811  *                                                                           *
1812 \*****************************************************************************/
1813
1814 #ifdef CONFIG_PM_SLEEP
1815 static int sdhci_pci_suspend(struct device *dev)
1816 {
1817         struct pci_dev *pdev = to_pci_dev(dev);
1818         struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1819
1820         if (!chip)
1821                 return 0;
1822
1823         if (chip->fixes && chip->fixes->suspend)
1824                 return chip->fixes->suspend(chip);
1825
1826         return sdhci_pci_suspend_host(chip);
1827 }
1828
1829 static int sdhci_pci_resume(struct device *dev)
1830 {
1831         struct pci_dev *pdev = to_pci_dev(dev);
1832         struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1833
1834         if (!chip)
1835                 return 0;
1836
1837         if (chip->fixes && chip->fixes->resume)
1838                 return chip->fixes->resume(chip);
1839
1840         return sdhci_pci_resume_host(chip);
1841 }
1842 #endif
1843
1844 #ifdef CONFIG_PM
1845 static int sdhci_pci_runtime_suspend(struct device *dev)
1846 {
1847         struct pci_dev *pdev = to_pci_dev(dev);
1848         struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1849
1850         if (!chip)
1851                 return 0;
1852
1853         if (chip->fixes && chip->fixes->runtime_suspend)
1854                 return chip->fixes->runtime_suspend(chip);
1855
1856         return sdhci_pci_runtime_suspend_host(chip);
1857 }
1858
1859 static int sdhci_pci_runtime_resume(struct device *dev)
1860 {
1861         struct pci_dev *pdev = to_pci_dev(dev);
1862         struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1863
1864         if (!chip)
1865                 return 0;
1866
1867         if (chip->fixes && chip->fixes->runtime_resume)
1868                 return chip->fixes->runtime_resume(chip);
1869
1870         return sdhci_pci_runtime_resume_host(chip);
1871 }
1872 #endif
1873
1874 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1875         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1876         SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1877                         sdhci_pci_runtime_resume, NULL)
1878 };
1879
1880 /*****************************************************************************\
1881  *                                                                           *
1882  * Device probing/removal                                                    *
1883  *                                                                           *
1884 \*****************************************************************************/
1885
1886 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1887         struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1888         int slotno)
1889 {
1890         struct sdhci_pci_slot *slot;
1891         struct sdhci_host *host;
1892         int ret, bar = first_bar + slotno;
1893         size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1894
1895         if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1896                 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1897                 return ERR_PTR(-ENODEV);
1898         }
1899
1900         if (pci_resource_len(pdev, bar) < 0x100) {
1901                 dev_err(&pdev->dev, "Invalid iomem size. You may "
1902                         "experience problems.\n");
1903         }
1904
1905         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1906                 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1907                 return ERR_PTR(-ENODEV);
1908         }
1909
1910         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1911                 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1912                 return ERR_PTR(-ENODEV);
1913         }
1914
1915         host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1916         if (IS_ERR(host)) {
1917                 dev_err(&pdev->dev, "cannot allocate host\n");
1918                 return ERR_CAST(host);
1919         }
1920
1921         slot = sdhci_priv(host);
1922
1923         slot->chip = chip;
1924         slot->host = host;
1925         slot->rst_n_gpio = -EINVAL;
1926         slot->cd_gpio = -EINVAL;
1927         slot->cd_idx = -1;
1928
1929         /* Retrieve platform data if there is any */
1930         if (*sdhci_pci_get_data)
1931                 slot->data = sdhci_pci_get_data(pdev, slotno);
1932
1933         if (slot->data) {
1934                 if (slot->data->setup) {
1935                         ret = slot->data->setup(slot->data);
1936                         if (ret) {
1937                                 dev_err(&pdev->dev, "platform setup failed\n");
1938                                 goto free;
1939                         }
1940                 }
1941                 slot->rst_n_gpio = slot->data->rst_n_gpio;
1942                 slot->cd_gpio = slot->data->cd_gpio;
1943         }
1944
1945         host->hw_name = "PCI";
1946         host->ops = chip->fixes && chip->fixes->ops ?
1947                     chip->fixes->ops :
1948                     &sdhci_pci_ops;
1949         host->quirks = chip->quirks;
1950         host->quirks2 = chip->quirks2;
1951
1952         host->irq = pdev->irq;
1953
1954         ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1955         if (ret) {
1956                 dev_err(&pdev->dev, "cannot request region\n");
1957                 goto cleanup;
1958         }
1959
1960         host->ioaddr = pcim_iomap_table(pdev)[bar];
1961
1962         if (chip->fixes && chip->fixes->probe_slot) {
1963                 ret = chip->fixes->probe_slot(slot);
1964                 if (ret)
1965                         goto cleanup;
1966         }
1967
1968         if (gpio_is_valid(slot->rst_n_gpio)) {
1969                 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1970                         gpio_direction_output(slot->rst_n_gpio, 1);
1971                         slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1972                         slot->hw_reset = sdhci_pci_gpio_hw_reset;
1973                 } else {
1974                         dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1975                         slot->rst_n_gpio = -EINVAL;
1976                 }
1977         }
1978
1979         host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1980         host->mmc->slotno = slotno;
1981         host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1982
1983         if (slot->cd_idx >= 0) {
1984                 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1985                                            slot->cd_override_level, 0, NULL);
1986                 if (ret == -EPROBE_DEFER)
1987                         goto remove;
1988
1989                 if (ret) {
1990                         dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1991                         slot->cd_idx = -1;
1992                 }
1993         }
1994
1995         if (chip->fixes && chip->fixes->add_host)
1996                 ret = chip->fixes->add_host(slot);
1997         else
1998                 ret = sdhci_add_host(host);
1999         if (ret)
2000                 goto remove;
2001
2002         sdhci_pci_add_own_cd(slot);
2003
2004         /*
2005          * Check if the chip needs a separate GPIO for card detect to wake up
2006          * from runtime suspend.  If it is not there, don't allow runtime PM.
2007          * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
2008          */
2009         if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
2010             !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
2011                 chip->allow_runtime_pm = false;
2012
2013         return slot;
2014
2015 remove:
2016         if (chip->fixes && chip->fixes->remove_slot)
2017                 chip->fixes->remove_slot(slot, 0);
2018
2019 cleanup:
2020         if (slot->data && slot->data->cleanup)
2021                 slot->data->cleanup(slot->data);
2022
2023 free:
2024         sdhci_free_host(host);
2025
2026         return ERR_PTR(ret);
2027 }
2028
2029 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2030 {
2031         int dead;
2032         u32 scratch;
2033
2034         sdhci_pci_remove_own_cd(slot);
2035
2036         dead = 0;
2037         scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2038         if (scratch == (u32)-1)
2039                 dead = 1;
2040
2041         sdhci_remove_host(slot->host, dead);
2042
2043         if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2044                 slot->chip->fixes->remove_slot(slot, dead);
2045
2046         if (slot->data && slot->data->cleanup)
2047                 slot->data->cleanup(slot->data);
2048
2049         sdhci_free_host(slot->host);
2050 }
2051
2052 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2053 {
2054         pm_suspend_ignore_children(dev, 1);
2055         pm_runtime_set_autosuspend_delay(dev, 50);
2056         pm_runtime_use_autosuspend(dev);
2057         pm_runtime_allow(dev);
2058         /* Stay active until mmc core scans for a card */
2059         pm_runtime_put_noidle(dev);
2060 }
2061
2062 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2063 {
2064         pm_runtime_forbid(dev);
2065         pm_runtime_get_noresume(dev);
2066 }
2067
2068 static int sdhci_pci_probe(struct pci_dev *pdev,
2069                                      const struct pci_device_id *ent)
2070 {
2071         struct sdhci_pci_chip *chip;
2072         struct sdhci_pci_slot *slot;
2073
2074         u8 slots, first_bar;
2075         int ret, i;
2076
2077         BUG_ON(pdev == NULL);
2078         BUG_ON(ent == NULL);
2079
2080         dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2081                  (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2082
2083         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2084         if (ret)
2085                 return ret;
2086
2087         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2088         dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2089         if (slots == 0)
2090                 return -ENODEV;
2091
2092         BUG_ON(slots > MAX_SLOTS);
2093
2094         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2095         if (ret)
2096                 return ret;
2097
2098         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2099
2100         if (first_bar > 5) {
2101                 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2102                 return -ENODEV;
2103         }
2104
2105         ret = pcim_enable_device(pdev);
2106         if (ret)
2107                 return ret;
2108
2109         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2110         if (!chip)
2111                 return -ENOMEM;
2112
2113         chip->pdev = pdev;
2114         chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2115         if (chip->fixes) {
2116                 chip->quirks = chip->fixes->quirks;
2117                 chip->quirks2 = chip->fixes->quirks2;
2118                 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2119         }
2120         chip->num_slots = slots;
2121         chip->pm_retune = true;
2122         chip->rpm_retune = true;
2123
2124         pci_set_drvdata(pdev, chip);
2125
2126         if (chip->fixes && chip->fixes->probe) {
2127                 ret = chip->fixes->probe(chip);
2128                 if (ret)
2129                         return ret;
2130         }
2131
2132         slots = chip->num_slots;        /* Quirk may have changed this */
2133
2134         for (i = 0; i < slots; i++) {
2135                 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2136                 if (IS_ERR(slot)) {
2137                         for (i--; i >= 0; i--)
2138                                 sdhci_pci_remove_slot(chip->slots[i]);
2139                         return PTR_ERR(slot);
2140                 }
2141
2142                 chip->slots[i] = slot;
2143         }
2144
2145         if (chip->allow_runtime_pm)
2146                 sdhci_pci_runtime_pm_allow(&pdev->dev);
2147
2148         return 0;
2149 }
2150
2151 static void sdhci_pci_remove(struct pci_dev *pdev)
2152 {
2153         int i;
2154         struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2155
2156         if (chip->allow_runtime_pm)
2157                 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2158
2159         for (i = 0; i < chip->num_slots; i++)
2160                 sdhci_pci_remove_slot(chip->slots[i]);
2161 }
2162
2163 static struct pci_driver sdhci_driver = {
2164         .name =         "sdhci-pci",
2165         .id_table =     pci_ids,
2166         .probe =        sdhci_pci_probe,
2167         .remove =       sdhci_pci_remove,
2168         .driver =       {
2169                 .pm =   &sdhci_pci_pm_ops
2170         },
2171 };
2172
2173 module_pci_driver(sdhci_driver);
2174
2175 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2176 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2177 MODULE_LICENSE("GPL");