2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Mingwei Wang <mwwang@marvell.com>
6 * Philip Rakity <prakity@marvell.com>
7 * Mark Brown <markb@marvell.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
24 #include <linux/gpio.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/platform_data/pxa_sdhci.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
37 #include "sdhci-pltfm.h"
39 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A
40 #define SDCLK_SEL 0x100
41 #define SDCLK_DELAY_SHIFT 9
42 #define SDCLK_DELAY_MASK 0x1f
44 #define SD_CFG_FIFO_PARAM 0x100
45 #define SDCFG_GEN_PAD_CLK_ON (1<<6)
46 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
47 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
49 #define SD_SPI_MODE 0x108
50 #define SD_CE_ATA_1 0x10C
52 #define SD_CE_ATA_2 0x10E
53 #define SDCE_MISC_INT (1<<2)
54 #define SDCE_MISC_INT_EN (1<<1)
56 static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
58 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
59 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
61 if (mask == SDHCI_RESET_ALL) {
63 * tune timing of read data/command when crc error happen
64 * no performance impact
66 if (pdata && 0 != pdata->clk_delay_cycles) {
69 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
70 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
73 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
78 #define MAX_WAIT_COUNT 5
79 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
81 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
82 struct sdhci_pxa *pxa = pltfm_host->priv;
86 if (pxa->power_mode == MMC_POWER_UP
87 && power_mode == MMC_POWER_ON) {
89 dev_dbg(mmc_dev(host->mmc),
90 "%s: slot->power_mode = %d,"
91 "ios->power_mode = %d\n",
96 /* set we want notice of when 74 clocks are sent */
97 tmp = readw(host->ioaddr + SD_CE_ATA_2);
98 tmp |= SDCE_MISC_INT_EN;
99 writew(tmp, host->ioaddr + SD_CE_ATA_2);
101 /* start sending the 74 clocks */
102 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
103 tmp |= SDCFG_GEN_PAD_CLK_ON;
104 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
106 /* slowest speed is about 100KHz or 10usec per clock */
110 while (count++ < MAX_WAIT_COUNT) {
111 if ((readw(host->ioaddr + SD_CE_ATA_2)
112 & SDCE_MISC_INT) == 0)
117 if (count == MAX_WAIT_COUNT)
118 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
120 /* clear the interrupt bit if posted */
121 tmp = readw(host->ioaddr + SD_CE_ATA_2);
122 tmp |= SDCE_MISC_INT;
123 writew(tmp, host->ioaddr + SD_CE_ATA_2);
125 pxa->power_mode = power_mode;
128 static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
133 * Set V18_EN -- UHS modes do not work without this.
134 * does not change signaling voltage
136 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
138 /* Select Bus Speed Mode for host */
139 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
141 case MMC_TIMING_UHS_SDR12:
142 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
144 case MMC_TIMING_UHS_SDR25:
145 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
147 case MMC_TIMING_UHS_SDR50:
148 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
150 case MMC_TIMING_UHS_SDR104:
151 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
153 case MMC_TIMING_UHS_DDR50:
154 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
158 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
159 dev_dbg(mmc_dev(host->mmc),
160 "%s uhs = %d, ctrl_2 = %04X\n",
161 __func__, uhs, ctrl_2);
166 static struct sdhci_ops pxav3_sdhci_ops = {
167 .platform_reset_exit = pxav3_set_private_registers,
168 .set_uhs_signaling = pxav3_set_uhs_signaling,
169 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
173 static const struct of_device_id sdhci_pxav3_of_match[] = {
175 .compatible = "mrvl,pxav3-mmc",
179 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
181 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
183 struct sdhci_pxa_platdata *pdata;
184 struct device_node *np = dev->of_node;
186 u32 clk_delay_cycles;
187 enum of_gpio_flags gpio_flags;
189 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
193 if (of_find_property(np, "non-removable", NULL))
194 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
196 of_property_read_u32(np, "bus-width", &bus_width);
198 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
200 of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
201 if (clk_delay_cycles > 0)
202 pdata->clk_delay_cycles = clk_delay_cycles;
204 pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags);
205 if (gpio_flags != OF_GPIO_ACTIVE_LOW)
206 pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
211 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
217 static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
219 struct sdhci_pltfm_host *pltfm_host;
220 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
221 struct device *dev = &pdev->dev;
222 struct sdhci_host *host = NULL;
223 struct sdhci_pxa *pxa = NULL;
224 const struct of_device_id *match;
229 pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
233 host = sdhci_pltfm_init(pdev, NULL);
236 return PTR_ERR(host);
238 pltfm_host = sdhci_priv(host);
239 pltfm_host->priv = pxa;
241 clk = clk_get(dev, NULL);
243 dev_err(dev, "failed to get io clock\n");
247 pltfm_host->clk = clk;
248 clk_prepare_enable(clk);
250 host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
251 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
252 | SDHCI_QUIRK_32BIT_ADMA_SIZE;
254 /* enable 1/8V DDR capable */
255 host->mmc->caps |= MMC_CAP_1_8V_DDR;
257 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
259 pdata = pxav3_get_mmc_pdata(dev);
262 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
264 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
265 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
268 /* If slot design supports 8 bit data, indicate this to MMC. */
269 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
270 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
273 host->quirks |= pdata->quirks;
274 if (pdata->host_caps)
275 host->mmc->caps |= pdata->host_caps;
276 if (pdata->host_caps2)
277 host->mmc->caps2 |= pdata->host_caps2;
279 host->mmc->pm_caps |= pdata->pm_caps;
281 if (gpio_is_valid(pdata->ext_cd_gpio)) {
282 ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
284 dev_err(mmc_dev(host->mmc),
285 "failed to allocate card detect gpio\n");
291 host->ops = &pxav3_sdhci_ops;
293 ret = sdhci_add_host(host);
295 dev_err(&pdev->dev, "failed to add host\n");
299 platform_set_drvdata(pdev, host);
304 clk_disable_unprepare(clk);
306 mmc_gpio_free_cd(host->mmc);
309 sdhci_pltfm_free(pdev);
314 static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
316 struct sdhci_host *host = platform_get_drvdata(pdev);
317 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
318 struct sdhci_pxa *pxa = pltfm_host->priv;
319 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
321 sdhci_remove_host(host, 1);
323 clk_disable_unprepare(pltfm_host->clk);
324 clk_put(pltfm_host->clk);
326 if (gpio_is_valid(pdata->ext_cd_gpio))
327 mmc_gpio_free_cd(host->mmc);
329 sdhci_pltfm_free(pdev);
332 platform_set_drvdata(pdev, NULL);
337 static struct platform_driver sdhci_pxav3_driver = {
339 .name = "sdhci-pxav3",
341 .of_match_table = sdhci_pxav3_of_match,
343 .owner = THIS_MODULE,
344 .pm = SDHCI_PLTFM_PMOPS,
346 .probe = sdhci_pxav3_probe,
347 .remove = __devexit_p(sdhci_pxav3_remove),
350 module_platform_driver(sdhci_pxav3_driver);
352 MODULE_DESCRIPTION("SDHCI driver for pxav3");
353 MODULE_AUTHOR("Marvell International Ltd.");
354 MODULE_LICENSE("GPL v2");