1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
22 #include <linux/mmc/host.h>
24 #include <plat/sdhci.h>
25 #include <plat/regs-sdhci.h>
29 #define MAX_BUS_CLK (4)
32 * struct sdhci_s3c - S3C SDHCI instance
33 * @host: The SDHCI host created
34 * @pdev: The platform device we where created from.
35 * @ioarea: The resource created when we claimed the IO area.
36 * @pdata: The platform data for this controller.
37 * @cur_clk: The index of the current bus clock.
38 * @clk_io: The clock for the internal bus interface.
39 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
42 struct sdhci_host *host;
43 struct platform_device *pdev;
44 struct resource *ioarea;
45 struct s3c_sdhci_platdata *pdata;
49 struct clk *clk_bus[MAX_BUS_CLK];
52 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
54 return sdhci_priv(host);
58 * get_curclk - convert ctrl2 register to clock source number
59 * @ctrl2: Control2 register value.
61 static u32 get_curclk(u32 ctrl2)
63 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
64 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
69 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
71 struct sdhci_s3c *ourhost = to_s3c(host);
72 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
74 if (get_curclk(tmp) != ourhost->cur_clk) {
75 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
77 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
78 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
79 writel(tmp, host->ioaddr + 0x80);
84 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
85 * @host: The SDHCI host instance.
87 * Callback to return the maximum clock rate acheivable by the controller.
89 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
91 struct sdhci_s3c *ourhost = to_s3c(host);
93 unsigned int rate, max;
96 /* note, a reset will reset the clock source */
98 sdhci_s3c_check_sclk(host);
100 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
101 busclk = ourhost->clk_bus[clk];
105 rate = clk_get_rate(busclk);
113 static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
115 return sdhci_s3c_get_max_clk(host) / 1000000;
119 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
120 * @ourhost: Our SDHCI instance.
121 * @src: The source clock index.
122 * @wanted: The clock frequency wanted.
124 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
129 struct clk *clksrc = ourhost->clk_bus[src];
135 rate = clk_get_rate(clksrc);
137 for (div = 1; div < 256; div *= 2) {
138 if ((rate / div) <= wanted)
142 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
143 src, rate, wanted, rate / div);
145 return (wanted - (rate / div));
149 * sdhci_s3c_set_clock - callback on clock change
150 * @host: The SDHCI host being changed
151 * @clock: The clock rate being requested.
153 * When the card's clock is going to be changed, look at the new frequency
154 * and find the best clock source to go with it.
156 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
158 struct sdhci_s3c *ourhost = to_s3c(host);
159 unsigned int best = UINT_MAX;
165 /* don't bother if the clock is going off. */
169 for (src = 0; src < MAX_BUS_CLK; src++) {
170 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
177 dev_dbg(&ourhost->pdev->dev,
178 "selected source %d, clock %d, delta %d\n",
179 best_src, clock, best);
181 /* select the new clock source */
183 if (ourhost->cur_clk != best_src) {
184 struct clk *clk = ourhost->clk_bus[best_src];
186 /* turn clock off to card before changing clock source */
187 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
189 ourhost->cur_clk = best_src;
190 host->max_clk = clk_get_rate(clk);
191 host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
193 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
194 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
195 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
196 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
199 /* reconfigure the hardware for new clock rate */
206 if (ourhost->pdata->cfg_card)
207 (ourhost->pdata->cfg_card)(ourhost->pdev, host->ioaddr,
212 static struct sdhci_ops sdhci_s3c_ops = {
213 .get_max_clock = sdhci_s3c_get_max_clk,
214 .get_timeout_clock = sdhci_s3c_get_timeout_clk,
215 .set_clock = sdhci_s3c_set_clock,
218 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
220 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
221 struct device *dev = &pdev->dev;
222 struct sdhci_host *host;
223 struct sdhci_s3c *sc;
224 struct resource *res;
225 int ret, irq, ptr, clks;
228 dev_err(dev, "no device data specified\n");
232 irq = platform_get_irq(pdev, 0);
234 dev_err(dev, "no irq specified\n");
238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 dev_err(dev, "no memory specified\n");
244 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
246 dev_err(dev, "sdhci_alloc_host() failed\n");
247 return PTR_ERR(host);
250 sc = sdhci_priv(host);
256 platform_set_drvdata(pdev, host);
258 sc->clk_io = clk_get(dev, "hsmmc");
259 if (IS_ERR(sc->clk_io)) {
260 dev_err(dev, "failed to get io clock\n");
261 ret = PTR_ERR(sc->clk_io);
265 /* enable the local io clock and keep it running for the moment. */
266 clk_enable(sc->clk_io);
268 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
270 char *name = pdata->clocks[ptr];
275 clk = clk_get(dev, name);
277 dev_err(dev, "failed to get clock %s\n", name);
282 sc->clk_bus[ptr] = clk;
285 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
286 ptr, name, clk_get_rate(clk));
290 dev_err(dev, "failed to find any bus clocks\n");
295 sc->ioarea = request_mem_region(res->start, resource_size(res),
296 mmc_hostname(host->mmc));
298 dev_err(dev, "failed to reserve register area\n");
303 host->ioaddr = ioremap_nocache(res->start, resource_size(res));
305 dev_err(dev, "failed to map registers\n");
310 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
312 pdata->cfg_gpio(pdev, pdata->max_width);
314 host->hw_name = "samsung-hsmmc";
315 host->ops = &sdhci_s3c_ops;
319 /* Setup quirks for the controller */
321 /* Currently with ADMA enabled we are getting some length
322 * interrupts that are not being dealt with, do disable
323 * ADMA until this is sorted out. */
324 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
325 host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
327 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
329 /* we currently see overruns on errors, so disable the SDMA
330 * support as well. */
331 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
333 /* PIO currently has problems with multi-block IO */
334 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
336 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
338 /* It seems we do not get an DATA transfer complete on non-busy
339 * transfers, not sure if this is a problem with this specific
340 * SDHCI block, or a missing configuration that needs to be set. */
341 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
343 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
344 SDHCI_QUIRK_32BIT_DMA_SIZE);
346 ret = sdhci_add_host(host);
348 dev_err(dev, "sdhci_add_host() failed\n");
355 release_resource(sc->ioarea);
359 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
360 clk_disable(sc->clk_bus[ptr]);
361 clk_put(sc->clk_bus[ptr]);
365 clk_disable(sc->clk_io);
369 sdhci_free_host(host);
374 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
381 static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
383 struct sdhci_host *host = platform_get_drvdata(dev);
385 sdhci_suspend_host(host, pm);
389 static int sdhci_s3c_resume(struct platform_device *dev)
391 struct sdhci_host *host = platform_get_drvdata(dev);
393 sdhci_resume_host(host);
398 #define sdhci_s3c_suspend NULL
399 #define sdhci_s3c_resume NULL
402 static struct platform_driver sdhci_s3c_driver = {
403 .probe = sdhci_s3c_probe,
404 .remove = __devexit_p(sdhci_s3c_remove),
405 .suspend = sdhci_s3c_suspend,
406 .resume = sdhci_s3c_resume,
408 .owner = THIS_MODULE,
413 static int __init sdhci_s3c_init(void)
415 return platform_driver_register(&sdhci_s3c_driver);
418 static void __exit sdhci_s3c_exit(void)
420 platform_driver_unregister(&sdhci_s3c_driver);
423 module_init(sdhci_s3c_init);
424 module_exit(sdhci_s3c_exit);
426 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
427 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
428 MODULE_LICENSE("GPL v2");
429 MODULE_ALIAS("platform:s3c-sdhci");