1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform_data/mmc-sdhci-s3c.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
25 #include <linux/of_gpio.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/mmc/host.h>
31 #include "sdhci-s3c-regs.h"
34 #define MAX_BUS_CLK (4)
37 * struct sdhci_s3c - S3C SDHCI instance
38 * @host: The SDHCI host created
39 * @pdev: The platform device we where created from.
40 * @ioarea: The resource created when we claimed the IO area.
41 * @pdata: The platform data for this controller.
42 * @cur_clk: The index of the current bus clock.
43 * @clk_io: The clock for the internal bus interface.
44 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
47 struct sdhci_host *host;
48 struct platform_device *pdev;
49 struct resource *ioarea;
50 struct s3c_sdhci_platdata *pdata;
56 struct clk *clk_bus[MAX_BUS_CLK];
57 unsigned long clk_rates[MAX_BUS_CLK];
63 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
64 * @sdhci_quirks: sdhci host specific quirks.
66 * Specifies platform specific configuration of sdhci controller.
67 * Note: A structure for driver specific platform data is used for future
68 * expansion of its usage.
70 struct sdhci_s3c_drv_data {
71 unsigned int sdhci_quirks;
75 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
77 return sdhci_priv(host);
81 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
82 * @host: The SDHCI host instance.
84 * Callback to return the maximum clock rate acheivable by the controller.
86 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
88 struct sdhci_s3c *ourhost = to_s3c(host);
89 unsigned long rate, max = 0;
92 for (src = 0; src < MAX_BUS_CLK; src++) {
93 rate = ourhost->clk_rates[src];
102 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
103 * @ourhost: Our SDHCI instance.
104 * @src: The source clock index.
105 * @wanted: The clock frequency wanted.
107 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
112 struct clk *clksrc = ourhost->clk_bus[src];
119 * If controller uses a non-standard clock division, find the best clock
120 * speed possible with selected clock source and skip the division.
122 if (ourhost->no_divider) {
123 rate = clk_round_rate(clksrc, wanted);
124 return wanted - rate;
127 rate = ourhost->clk_rates[src];
129 for (shift = 0; shift <= 8; ++shift) {
130 if ((rate >> shift) <= wanted)
135 dev_dbg(&ourhost->pdev->dev,
136 "clk %d: rate %ld, min rate %lu > wanted %u\n",
137 src, rate, rate / 256, wanted);
141 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142 src, rate, wanted, rate >> shift);
144 return wanted - (rate >> shift);
148 * sdhci_s3c_set_clock - callback on clock change
149 * @host: The SDHCI host being changed
150 * @clock: The clock rate being requested.
152 * When the card's clock is going to be changed, look at the new frequency
153 * and find the best clock source to go with it.
155 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned int best = UINT_MAX;
164 host->mmc->actual_clock = 0;
166 /* don't bother if the clock is going off. */
168 sdhci_set_clock(host, clock);
172 for (src = 0; src < MAX_BUS_CLK; src++) {
173 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
180 dev_dbg(&ourhost->pdev->dev,
181 "selected source %d, clock %d, delta %d\n",
182 best_src, clock, best);
184 /* select the new clock source */
185 if (ourhost->cur_clk != best_src) {
186 struct clk *clk = ourhost->clk_bus[best_src];
188 clk_prepare_enable(clk);
189 if (ourhost->cur_clk >= 0)
190 clk_disable_unprepare(
191 ourhost->clk_bus[ourhost->cur_clk]);
193 ourhost->cur_clk = best_src;
194 host->max_clk = ourhost->clk_rates[best_src];
197 /* turn clock off to card before changing clock source */
198 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
200 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
201 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
202 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
203 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
205 /* reprogram default hardware configuration */
206 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
207 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
209 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
210 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
211 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
212 S3C_SDHCI_CTRL2_ENFBCLKRX |
213 S3C_SDHCI_CTRL2_DFCNT_NONE |
214 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
215 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
217 /* reconfigure the controller for new clock rate */
218 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
219 if (clock < 25 * 1000000)
220 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
221 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
223 sdhci_set_clock(host, clock);
227 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
228 * @host: The SDHCI host being queried
230 * To init mmc host properly a minimal clock value is needed. For high system
231 * bus clock's values the standard formula gives values out of allowed range.
232 * The clock still can be set to lower values, if clock source other then
233 * system bus is selected.
235 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
237 struct sdhci_s3c *ourhost = to_s3c(host);
238 unsigned long rate, min = ULONG_MAX;
241 for (src = 0; src < MAX_BUS_CLK; src++) {
242 rate = ourhost->clk_rates[src] / 256;
252 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
253 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
255 struct sdhci_s3c *ourhost = to_s3c(host);
256 unsigned long rate, max = 0;
259 for (src = 0; src < MAX_BUS_CLK; src++) {
262 clk = ourhost->clk_bus[src];
266 rate = clk_round_rate(clk, ULONG_MAX);
274 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
275 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
277 struct sdhci_s3c *ourhost = to_s3c(host);
278 unsigned long rate, min = ULONG_MAX;
281 for (src = 0; src < MAX_BUS_CLK; src++) {
284 clk = ourhost->clk_bus[src];
288 rate = clk_round_rate(clk, 0);
296 /* sdhci_cmu_set_clock - callback on clock change.*/
297 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
299 struct sdhci_s3c *ourhost = to_s3c(host);
300 struct device *dev = &ourhost->pdev->dev;
301 unsigned long timeout;
305 host->mmc->actual_clock = 0;
307 /* If the clock is going off, set to 0 at clock control register */
309 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
313 sdhci_s3c_set_clock(host, clock);
315 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
317 dev_err(dev, "%s: failed to set clock rate %uHz\n",
318 mmc_hostname(host->mmc), clock);
322 clk = SDHCI_CLOCK_INT_EN;
323 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
327 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
328 & SDHCI_CLOCK_INT_STABLE)) {
330 dev_err(dev, "%s: Internal clock never stabilised.\n",
331 mmc_hostname(host->mmc));
338 clk |= SDHCI_CLOCK_CARD_EN;
339 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
343 * sdhci_s3c_set_bus_width - support 8bit buswidth
344 * @host: The SDHCI host being queried
345 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
347 * We have 8-bit width support but is not a v3 controller.
348 * So we add platform_bus_width() and support 8bit width.
350 static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
354 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
357 case MMC_BUS_WIDTH_8:
358 ctrl |= SDHCI_CTRL_8BITBUS;
359 ctrl &= ~SDHCI_CTRL_4BITBUS;
361 case MMC_BUS_WIDTH_4:
362 ctrl |= SDHCI_CTRL_4BITBUS;
363 ctrl &= ~SDHCI_CTRL_8BITBUS;
366 ctrl &= ~SDHCI_CTRL_4BITBUS;
367 ctrl &= ~SDHCI_CTRL_8BITBUS;
371 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
374 static struct sdhci_ops sdhci_s3c_ops = {
375 .get_max_clock = sdhci_s3c_get_max_clk,
376 .set_clock = sdhci_s3c_set_clock,
377 .get_min_clock = sdhci_s3c_get_min_clock,
378 .set_bus_width = sdhci_s3c_set_bus_width,
379 .reset = sdhci_reset,
380 .set_uhs_signaling = sdhci_set_uhs_signaling,
384 static int sdhci_s3c_parse_dt(struct device *dev,
385 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
387 struct device_node *node = dev->of_node;
390 /* if the bus-width property is not specified, assume width as 1 */
391 if (of_property_read_u32(node, "bus-width", &max_width))
393 pdata->max_width = max_width;
395 /* get the card detection method */
396 if (of_get_property(node, "broken-cd", NULL)) {
397 pdata->cd_type = S3C_SDHCI_CD_NONE;
401 if (of_get_property(node, "non-removable", NULL)) {
402 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
406 if (of_get_named_gpio(node, "cd-gpios", 0))
409 /* assuming internal card detect that will be configured by pinctrl */
410 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
414 static int sdhci_s3c_parse_dt(struct device *dev,
415 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
421 static const struct of_device_id sdhci_s3c_dt_match[];
423 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
424 struct platform_device *pdev)
427 if (pdev->dev.of_node) {
428 const struct of_device_id *match;
429 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
430 return (struct sdhci_s3c_drv_data *)match->data;
433 return (struct sdhci_s3c_drv_data *)
434 platform_get_device_id(pdev)->driver_data;
437 static int sdhci_s3c_probe(struct platform_device *pdev)
439 struct s3c_sdhci_platdata *pdata;
440 struct sdhci_s3c_drv_data *drv_data;
441 struct device *dev = &pdev->dev;
442 struct sdhci_host *host;
443 struct sdhci_s3c *sc;
444 struct resource *res;
445 int ret, irq, ptr, clks;
447 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
448 dev_err(dev, "no device data specified\n");
452 irq = platform_get_irq(pdev, 0);
454 dev_err(dev, "no irq specified\n");
458 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
460 dev_err(dev, "sdhci_alloc_host() failed\n");
461 return PTR_ERR(host);
463 sc = sdhci_priv(host);
465 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
468 goto err_pdata_io_clk;
471 if (pdev->dev.of_node) {
472 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
474 goto err_pdata_io_clk;
476 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
477 sc->ext_cd_gpio = -1; /* invalid gpio number */
480 drv_data = sdhci_s3c_get_driver_data(pdev);
487 platform_set_drvdata(pdev, host);
489 sc->clk_io = devm_clk_get(dev, "hsmmc");
490 if (IS_ERR(sc->clk_io)) {
491 dev_err(dev, "failed to get io clock\n");
492 ret = PTR_ERR(sc->clk_io);
493 goto err_pdata_io_clk;
496 /* enable the local io clock and keep it running for the moment. */
497 clk_prepare_enable(sc->clk_io);
499 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
502 snprintf(name, 14, "mmc_busclk.%d", ptr);
503 sc->clk_bus[ptr] = devm_clk_get(dev, name);
504 if (IS_ERR(sc->clk_bus[ptr]))
508 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
510 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
511 ptr, name, sc->clk_rates[ptr]);
515 dev_err(dev, "failed to find any bus clocks\n");
520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
522 if (IS_ERR(host->ioaddr)) {
523 ret = PTR_ERR(host->ioaddr);
527 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
529 pdata->cfg_gpio(pdev, pdata->max_width);
531 host->hw_name = "samsung-hsmmc";
532 host->ops = &sdhci_s3c_ops;
537 /* Setup quirks for the controller */
538 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
539 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
541 host->quirks |= drv_data->sdhci_quirks;
542 sc->no_divider = drv_data->no_divider;
545 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
547 /* we currently see overruns on errors, so disable the SDMA
548 * support as well. */
549 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
551 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
553 /* It seems we do not get an DATA transfer complete on non-busy
554 * transfers, not sure if this is a problem with this specific
555 * SDHCI block, or a missing configuration that needs to be set. */
556 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
558 /* This host supports the Auto CMD12 */
559 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
561 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
562 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
564 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
565 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
566 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
568 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
569 host->mmc->caps = MMC_CAP_NONREMOVABLE;
571 switch (pdata->max_width) {
573 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
575 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
580 host->mmc->pm_caps |= pdata->pm_caps;
582 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
583 SDHCI_QUIRK_32BIT_DMA_SIZE);
585 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
586 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
589 * If controller does not have internal clock divider,
590 * we can use overriding functions instead of default.
592 if (sc->no_divider) {
593 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
594 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
595 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
598 /* It supports additional host capabilities if needed */
599 if (pdata->host_caps)
600 host->mmc->caps |= pdata->host_caps;
602 if (pdata->host_caps2)
603 host->mmc->caps2 |= pdata->host_caps2;
605 pm_runtime_enable(&pdev->dev);
606 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
607 pm_runtime_use_autosuspend(&pdev->dev);
608 pm_suspend_ignore_children(&pdev->dev, 1);
610 mmc_of_parse(host->mmc);
612 ret = sdhci_add_host(host);
614 dev_err(dev, "sdhci_add_host() failed\n");
619 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
620 clk_disable_unprepare(sc->clk_io);
625 pm_runtime_disable(&pdev->dev);
628 clk_disable_unprepare(sc->clk_io);
631 sdhci_free_host(host);
636 static int sdhci_s3c_remove(struct platform_device *pdev)
638 struct sdhci_host *host = platform_get_drvdata(pdev);
639 struct sdhci_s3c *sc = sdhci_priv(host);
642 free_irq(sc->ext_cd_irq, sc);
645 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
646 clk_prepare_enable(sc->clk_io);
648 sdhci_remove_host(host, 1);
650 pm_runtime_dont_use_autosuspend(&pdev->dev);
651 pm_runtime_disable(&pdev->dev);
653 clk_disable_unprepare(sc->clk_io);
655 sdhci_free_host(host);
660 #ifdef CONFIG_PM_SLEEP
661 static int sdhci_s3c_suspend(struct device *dev)
663 struct sdhci_host *host = dev_get_drvdata(dev);
665 return sdhci_suspend_host(host);
668 static int sdhci_s3c_resume(struct device *dev)
670 struct sdhci_host *host = dev_get_drvdata(dev);
672 return sdhci_resume_host(host);
677 static int sdhci_s3c_runtime_suspend(struct device *dev)
679 struct sdhci_host *host = dev_get_drvdata(dev);
680 struct sdhci_s3c *ourhost = to_s3c(host);
681 struct clk *busclk = ourhost->clk_io;
684 ret = sdhci_runtime_suspend_host(host);
686 if (ourhost->cur_clk >= 0)
687 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
688 clk_disable_unprepare(busclk);
692 static int sdhci_s3c_runtime_resume(struct device *dev)
694 struct sdhci_host *host = dev_get_drvdata(dev);
695 struct sdhci_s3c *ourhost = to_s3c(host);
696 struct clk *busclk = ourhost->clk_io;
699 clk_prepare_enable(busclk);
700 if (ourhost->cur_clk >= 0)
701 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
702 ret = sdhci_runtime_resume_host(host);
708 static const struct dev_pm_ops sdhci_s3c_pmops = {
709 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
710 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
714 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
717 #define SDHCI_S3C_PMOPS NULL
720 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
721 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
724 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
726 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
729 static struct platform_device_id sdhci_s3c_driver_ids[] = {
732 .driver_data = (kernel_ulong_t)NULL,
734 .name = "exynos4-sdhci",
735 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
739 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
742 static const struct of_device_id sdhci_s3c_dt_match[] = {
743 { .compatible = "samsung,s3c6410-sdhci", },
744 { .compatible = "samsung,exynos4210-sdhci",
745 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
748 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
751 static struct platform_driver sdhci_s3c_driver = {
752 .probe = sdhci_s3c_probe,
753 .remove = sdhci_s3c_remove,
754 .id_table = sdhci_s3c_driver_ids,
757 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
758 .pm = SDHCI_S3C_PMOPS,
762 module_platform_driver(sdhci_s3c_driver);
764 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
765 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
766 MODULE_LICENSE("GPL v2");
767 MODULE_ALIAS("platform:s3c-sdhci");