1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform_data/mmc-sdhci-s3c.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
25 #include <linux/of_gpio.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/mmc/host.h>
31 #include "sdhci-s3c-regs.h"
34 #define MAX_BUS_CLK (4)
36 /* Number of gpio's used is max data bus width + command and clock lines */
37 #define NUM_GPIOS(x) (x + 2)
40 * struct sdhci_s3c - S3C SDHCI instance
41 * @host: The SDHCI host created
42 * @pdev: The platform device we where created from.
43 * @ioarea: The resource created when we claimed the IO area.
44 * @pdata: The platform data for this controller.
45 * @cur_clk: The index of the current bus clock.
46 * @clk_io: The clock for the internal bus interface.
47 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
50 struct sdhci_host *host;
51 struct platform_device *pdev;
52 struct resource *ioarea;
53 struct s3c_sdhci_platdata *pdata;
59 struct clk *clk_bus[MAX_BUS_CLK];
63 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
64 * @sdhci_quirks: sdhci host specific quirks.
66 * Specifies platform specific configuration of sdhci controller.
67 * Note: A structure for driver specific platform data is used for future
68 * expansion of its usage.
70 struct sdhci_s3c_drv_data {
71 unsigned int sdhci_quirks;
74 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
76 return sdhci_priv(host);
80 * get_curclk - convert ctrl2 register to clock source number
81 * @ctrl2: Control2 register value.
83 static u32 get_curclk(u32 ctrl2)
85 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
86 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
91 static void sdhci_s3c_check_sclk(struct sdhci_host *host)
93 struct sdhci_s3c *ourhost = to_s3c(host);
94 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
96 if (get_curclk(tmp) != ourhost->cur_clk) {
97 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
99 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
100 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
101 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
106 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
107 * @host: The SDHCI host instance.
109 * Callback to return the maximum clock rate acheivable by the controller.
111 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
113 struct sdhci_s3c *ourhost = to_s3c(host);
115 unsigned int rate, max;
118 /* note, a reset will reset the clock source */
120 sdhci_s3c_check_sclk(host);
122 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
123 busclk = ourhost->clk_bus[clk];
127 rate = clk_get_rate(busclk);
136 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
137 * @ourhost: Our SDHCI instance.
138 * @src: The source clock index.
139 * @wanted: The clock frequency wanted.
141 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
146 struct clk *clksrc = ourhost->clk_bus[src];
153 * If controller uses a non-standard clock division, find the best clock
154 * speed possible with selected clock source and skip the division.
156 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
157 rate = clk_round_rate(clksrc, wanted);
158 return wanted - rate;
161 rate = clk_get_rate(clksrc);
163 for (div = 1; div < 256; div *= 2) {
164 if ((rate / div) <= wanted)
168 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
169 src, rate, wanted, rate / div);
171 return wanted - (rate / div);
175 * sdhci_s3c_set_clock - callback on clock change
176 * @host: The SDHCI host being changed
177 * @clock: The clock rate being requested.
179 * When the card's clock is going to be changed, look at the new frequency
180 * and find the best clock source to go with it.
182 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
184 struct sdhci_s3c *ourhost = to_s3c(host);
185 unsigned int best = UINT_MAX;
191 /* don't bother if the clock is going off. */
195 for (src = 0; src < MAX_BUS_CLK; src++) {
196 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
203 dev_dbg(&ourhost->pdev->dev,
204 "selected source %d, clock %d, delta %d\n",
205 best_src, clock, best);
207 /* select the new clock source */
208 if (ourhost->cur_clk != best_src) {
209 struct clk *clk = ourhost->clk_bus[best_src];
211 clk_prepare_enable(clk);
212 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
214 /* turn clock off to card before changing clock source */
215 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
217 ourhost->cur_clk = best_src;
218 host->max_clk = clk_get_rate(clk);
220 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
221 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
222 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
223 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
226 /* reprogram default hardware configuration */
227 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
228 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
230 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
231 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
232 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
233 S3C_SDHCI_CTRL2_ENFBCLKRX |
234 S3C_SDHCI_CTRL2_DFCNT_NONE |
235 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
236 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
238 /* reconfigure the controller for new clock rate */
239 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
240 if (clock < 25 * 1000000)
241 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
242 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
246 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
247 * @host: The SDHCI host being queried
249 * To init mmc host properly a minimal clock value is needed. For high system
250 * bus clock's values the standard formula gives values out of allowed range.
251 * The clock still can be set to lower values, if clock source other then
252 * system bus is selected.
254 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
256 struct sdhci_s3c *ourhost = to_s3c(host);
257 unsigned int delta, min = UINT_MAX;
260 for (src = 0; src < MAX_BUS_CLK; src++) {
261 delta = sdhci_s3c_consider_clock(ourhost, src, 0);
262 if (delta == UINT_MAX)
264 /* delta is a negative value in this case */
271 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
272 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
274 struct sdhci_s3c *ourhost = to_s3c(host);
276 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
279 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
280 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
282 struct sdhci_s3c *ourhost = to_s3c(host);
285 * initial clock can be in the frequency range of
286 * 100KHz-400KHz, so we set it as max value.
288 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
291 /* sdhci_cmu_set_clock - callback on clock change.*/
292 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
294 struct sdhci_s3c *ourhost = to_s3c(host);
295 struct device *dev = &ourhost->pdev->dev;
296 unsigned long timeout;
299 /* don't bother if the clock is going off */
303 sdhci_s3c_set_clock(host, clock);
305 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
309 clk = SDHCI_CLOCK_INT_EN;
310 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
314 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
315 & SDHCI_CLOCK_INT_STABLE)) {
317 dev_err(dev, "%s: Internal clock never stabilised.\n",
318 mmc_hostname(host->mmc));
325 clk |= SDHCI_CLOCK_CARD_EN;
326 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
330 * sdhci_s3c_platform_bus_width - support 8bit buswidth
331 * @host: The SDHCI host being queried
332 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
334 * We have 8-bit width support but is not a v3 controller.
335 * So we add platform_bus_width() and support 8bit width.
337 static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
341 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
344 case MMC_BUS_WIDTH_8:
345 ctrl |= SDHCI_CTRL_8BITBUS;
346 ctrl &= ~SDHCI_CTRL_4BITBUS;
348 case MMC_BUS_WIDTH_4:
349 ctrl |= SDHCI_CTRL_4BITBUS;
350 ctrl &= ~SDHCI_CTRL_8BITBUS;
353 ctrl &= ~SDHCI_CTRL_4BITBUS;
354 ctrl &= ~SDHCI_CTRL_8BITBUS;
358 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
363 static struct sdhci_ops sdhci_s3c_ops = {
364 .get_max_clock = sdhci_s3c_get_max_clk,
365 .set_clock = sdhci_s3c_set_clock,
366 .get_min_clock = sdhci_s3c_get_min_clock,
367 .platform_bus_width = sdhci_s3c_platform_bus_width,
370 static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
372 struct sdhci_host *host = platform_get_drvdata(dev);
373 #ifdef CONFIG_PM_RUNTIME
374 struct sdhci_s3c *sc = sdhci_priv(host);
379 spin_lock_irqsave(&host->lock, flags);
381 dev_dbg(&dev->dev, "card inserted.\n");
382 #ifdef CONFIG_PM_RUNTIME
383 clk_prepare_enable(sc->clk_io);
385 host->flags &= ~SDHCI_DEVICE_DEAD;
386 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
388 dev_dbg(&dev->dev, "card removed.\n");
389 host->flags |= SDHCI_DEVICE_DEAD;
390 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
391 #ifdef CONFIG_PM_RUNTIME
392 clk_disable_unprepare(sc->clk_io);
395 tasklet_schedule(&host->card_tasklet);
396 spin_unlock_irqrestore(&host->lock, flags);
400 static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
402 struct sdhci_s3c *sc = dev_id;
403 int status = gpio_get_value(sc->ext_cd_gpio);
404 if (sc->pdata->ext_cd_gpio_invert)
406 sdhci_s3c_notify_change(sc->pdev, status);
410 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
412 struct s3c_sdhci_platdata *pdata = sc->pdata;
413 struct device *dev = &sc->pdev->dev;
415 if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
416 sc->ext_cd_gpio = pdata->ext_cd_gpio;
417 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
418 if (sc->ext_cd_irq &&
419 request_threaded_irq(sc->ext_cd_irq, NULL,
420 sdhci_s3c_gpio_card_detect_thread,
421 IRQF_TRIGGER_RISING |
422 IRQF_TRIGGER_FALLING |
424 dev_name(dev), sc) == 0) {
425 int status = gpio_get_value(sc->ext_cd_gpio);
426 if (pdata->ext_cd_gpio_invert)
428 sdhci_s3c_notify_change(sc->pdev, status);
430 dev_warn(dev, "cannot request irq for card detect\n");
434 dev_err(dev, "cannot request gpio for card detect\n");
439 static int sdhci_s3c_parse_dt(struct device *dev,
440 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
442 struct device_node *node = dev->of_node;
443 struct sdhci_s3c *ourhost = to_s3c(host);
447 /* if the bus-width property is not specified, assume width as 1 */
448 if (of_property_read_u32(node, "bus-width", &max_width))
450 pdata->max_width = max_width;
452 /* get the card detection method */
453 if (of_get_property(node, "broken-cd", NULL)) {
454 pdata->cd_type = S3C_SDHCI_CD_NONE;
458 if (of_get_property(node, "non-removable", NULL)) {
459 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
463 gpio = of_get_named_gpio(node, "cd-gpios", 0);
464 if (gpio_is_valid(gpio)) {
465 pdata->cd_type = S3C_SDHCI_CD_GPIO;
466 pdata->ext_cd_gpio = gpio;
467 ourhost->ext_cd_gpio = -1;
468 if (of_get_property(node, "cd-inverted", NULL))
469 pdata->ext_cd_gpio_invert = 1;
471 } else if (gpio != -ENOENT) {
472 dev_err(dev, "invalid card detect gpio specified\n");
476 /* assuming internal card detect that will be configured by pinctrl */
477 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
481 static int sdhci_s3c_parse_dt(struct device *dev,
482 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
488 static const struct of_device_id sdhci_s3c_dt_match[];
490 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
491 struct platform_device *pdev)
494 if (pdev->dev.of_node) {
495 const struct of_device_id *match;
496 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
497 return (struct sdhci_s3c_drv_data *)match->data;
500 return (struct sdhci_s3c_drv_data *)
501 platform_get_device_id(pdev)->driver_data;
504 static int sdhci_s3c_probe(struct platform_device *pdev)
506 struct s3c_sdhci_platdata *pdata;
507 struct sdhci_s3c_drv_data *drv_data;
508 struct device *dev = &pdev->dev;
509 struct sdhci_host *host;
510 struct sdhci_s3c *sc;
511 struct resource *res;
512 int ret, irq, ptr, clks;
514 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
515 dev_err(dev, "no device data specified\n");
519 irq = platform_get_irq(pdev, 0);
521 dev_err(dev, "no irq specified\n");
525 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
527 dev_err(dev, "sdhci_alloc_host() failed\n");
528 return PTR_ERR(host);
530 sc = sdhci_priv(host);
532 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
535 goto err_pdata_io_clk;
538 if (pdev->dev.of_node) {
539 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
541 goto err_pdata_io_clk;
543 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
544 sc->ext_cd_gpio = -1; /* invalid gpio number */
547 drv_data = sdhci_s3c_get_driver_data(pdev);
553 platform_set_drvdata(pdev, host);
555 sc->clk_io = devm_clk_get(dev, "hsmmc");
556 if (IS_ERR(sc->clk_io)) {
557 dev_err(dev, "failed to get io clock\n");
558 ret = PTR_ERR(sc->clk_io);
559 goto err_pdata_io_clk;
562 /* enable the local io clock and keep it running for the moment. */
563 clk_prepare_enable(sc->clk_io);
565 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
569 snprintf(name, 14, "mmc_busclk.%d", ptr);
570 clk = devm_clk_get(dev, name);
575 sc->clk_bus[ptr] = clk;
578 * save current clock index to know which clock bus
579 * is used later in overriding functions.
583 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
584 ptr, name, clk_get_rate(clk));
588 dev_err(dev, "failed to find any bus clocks\n");
593 #ifndef CONFIG_PM_RUNTIME
594 clk_prepare_enable(sc->clk_bus[sc->cur_clk]);
597 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
598 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
599 if (IS_ERR(host->ioaddr)) {
600 ret = PTR_ERR(host->ioaddr);
604 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
606 pdata->cfg_gpio(pdev, pdata->max_width);
608 host->hw_name = "samsung-hsmmc";
609 host->ops = &sdhci_s3c_ops;
613 /* Setup quirks for the controller */
614 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
615 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
617 host->quirks |= drv_data->sdhci_quirks;
619 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
621 /* we currently see overruns on errors, so disable the SDMA
622 * support as well. */
623 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
625 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
627 /* It seems we do not get an DATA transfer complete on non-busy
628 * transfers, not sure if this is a problem with this specific
629 * SDHCI block, or a missing configuration that needs to be set. */
630 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
632 /* This host supports the Auto CMD12 */
633 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
635 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
636 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
638 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
639 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
640 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
642 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
643 host->mmc->caps = MMC_CAP_NONREMOVABLE;
645 switch (pdata->max_width) {
647 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
649 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
654 host->mmc->pm_caps |= pdata->pm_caps;
656 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
657 SDHCI_QUIRK_32BIT_DMA_SIZE);
659 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
660 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
663 * If controller does not have internal clock divider,
664 * we can use overriding functions instead of default.
666 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
667 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
668 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
669 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
672 /* It supports additional host capabilities if needed */
673 if (pdata->host_caps)
674 host->mmc->caps |= pdata->host_caps;
676 if (pdata->host_caps2)
677 host->mmc->caps2 |= pdata->host_caps2;
679 pm_runtime_enable(&pdev->dev);
680 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
681 pm_runtime_use_autosuspend(&pdev->dev);
682 pm_suspend_ignore_children(&pdev->dev, 1);
684 ret = sdhci_add_host(host);
686 dev_err(dev, "sdhci_add_host() failed\n");
687 pm_runtime_forbid(&pdev->dev);
688 pm_runtime_get_noresume(&pdev->dev);
692 /* The following two methods of card detection might call
693 sdhci_s3c_notify_change() immediately, so they can be called
694 only after sdhci_add_host(). Setup errors are ignored. */
695 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
696 pdata->ext_cd_init(&sdhci_s3c_notify_change);
697 if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
698 gpio_is_valid(pdata->ext_cd_gpio))
699 sdhci_s3c_setup_card_detect_gpio(sc);
701 #ifdef CONFIG_PM_RUNTIME
702 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
703 clk_disable_unprepare(sc->clk_io);
708 #ifndef CONFIG_PM_RUNTIME
709 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
713 clk_disable_unprepare(sc->clk_io);
716 sdhci_free_host(host);
721 static int sdhci_s3c_remove(struct platform_device *pdev)
723 struct sdhci_host *host = platform_get_drvdata(pdev);
724 struct sdhci_s3c *sc = sdhci_priv(host);
725 struct s3c_sdhci_platdata *pdata = sc->pdata;
727 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
728 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
731 free_irq(sc->ext_cd_irq, sc);
733 #ifdef CONFIG_PM_RUNTIME
734 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
735 clk_prepare_enable(sc->clk_io);
737 sdhci_remove_host(host, 1);
739 pm_runtime_dont_use_autosuspend(&pdev->dev);
740 pm_runtime_disable(&pdev->dev);
742 #ifndef CONFIG_PM_RUNTIME
743 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]);
745 clk_disable_unprepare(sc->clk_io);
747 sdhci_free_host(host);
748 platform_set_drvdata(pdev, NULL);
753 #ifdef CONFIG_PM_SLEEP
754 static int sdhci_s3c_suspend(struct device *dev)
756 struct sdhci_host *host = dev_get_drvdata(dev);
758 return sdhci_suspend_host(host);
761 static int sdhci_s3c_resume(struct device *dev)
763 struct sdhci_host *host = dev_get_drvdata(dev);
765 return sdhci_resume_host(host);
769 #ifdef CONFIG_PM_RUNTIME
770 static int sdhci_s3c_runtime_suspend(struct device *dev)
772 struct sdhci_host *host = dev_get_drvdata(dev);
773 struct sdhci_s3c *ourhost = to_s3c(host);
774 struct clk *busclk = ourhost->clk_io;
777 ret = sdhci_runtime_suspend_host(host);
779 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
780 clk_disable_unprepare(busclk);
784 static int sdhci_s3c_runtime_resume(struct device *dev)
786 struct sdhci_host *host = dev_get_drvdata(dev);
787 struct sdhci_s3c *ourhost = to_s3c(host);
788 struct clk *busclk = ourhost->clk_io;
791 clk_prepare_enable(busclk);
792 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
793 ret = sdhci_runtime_resume_host(host);
799 static const struct dev_pm_ops sdhci_s3c_pmops = {
800 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
801 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
805 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
808 #define SDHCI_S3C_PMOPS NULL
811 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
812 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
813 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
815 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
817 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
820 static struct platform_device_id sdhci_s3c_driver_ids[] = {
823 .driver_data = (kernel_ulong_t)NULL,
825 .name = "exynos4-sdhci",
826 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
830 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
833 static const struct of_device_id sdhci_s3c_dt_match[] = {
834 { .compatible = "samsung,s3c6410-sdhci", },
835 { .compatible = "samsung,exynos4210-sdhci",
836 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
839 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
842 static struct platform_driver sdhci_s3c_driver = {
843 .probe = sdhci_s3c_probe,
844 .remove = sdhci_s3c_remove,
845 .id_table = sdhci_s3c_driver_ids,
847 .owner = THIS_MODULE,
849 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
850 .pm = SDHCI_S3C_PMOPS,
854 module_platform_driver(sdhci_s3c_driver);
856 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
857 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
858 MODULE_LICENSE("GPL v2");
859 MODULE_ALIAS("platform:s3c-sdhci");