2 * Copyright (C) 2010 Google, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/clk.h>
23 #include <linux/of_device.h>
24 #include <linux/reset.h>
25 #include <linux/mmc/card.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/gpio/consumer.h>
31 #include "sdhci-pltfm.h"
33 /* Tegra SDHOST controller vendor register definitions */
34 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
35 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
36 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
37 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
38 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
39 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
41 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
42 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
43 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
44 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
45 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
47 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
48 #define SDHCI_AUTO_CAL_START BIT(31)
49 #define SDHCI_AUTO_CAL_ENABLE BIT(29)
51 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
52 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
53 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
54 #define NVQUIRK_ENABLE_SDR50 BIT(3)
55 #define NVQUIRK_ENABLE_SDR104 BIT(4)
56 #define NVQUIRK_ENABLE_DDR50 BIT(5)
57 #define NVQUIRK_HAS_PADCALIB BIT(6)
59 struct sdhci_tegra_soc_data {
60 const struct sdhci_pltfm_data *pdata;
65 const struct sdhci_tegra_soc_data *soc_data;
66 struct gpio_desc *power_gpio;
68 bool pad_calib_required;
70 struct reset_control *rst;
73 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
75 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
76 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
77 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
79 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
80 (reg == SDHCI_HOST_VERSION))) {
81 /* Erratum: Version register is invalid in HW. */
82 return SDHCI_SPEC_200;
85 return readw(host->ioaddr + reg);
88 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
90 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
93 case SDHCI_TRANSFER_MODE:
95 * Postpone this write, we must do it together with a
96 * command write that is down below.
98 pltfm_host->xfer_mode_shadow = val;
101 writel((val << 16) | pltfm_host->xfer_mode_shadow,
102 host->ioaddr + SDHCI_TRANSFER_MODE);
106 writew(val, host->ioaddr + reg);
109 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
112 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
113 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
115 /* Seems like we're getting spurious timeout and crc errors, so
116 * disable signalling of them. In case of real errors software
117 * timers should take care of eventually detecting them.
119 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
120 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
122 writel(val, host->ioaddr + reg);
124 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
125 (reg == SDHCI_INT_ENABLE))) {
126 /* Erratum: Must enable block gap interrupt detection */
127 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
128 if (val & SDHCI_INT_CARD_INT)
132 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
136 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
138 return mmc_gpio_get_ro(host->mmc);
141 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
144 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
145 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
146 u32 misc_ctrl, clk_ctrl;
148 sdhci_reset(host, mask);
150 if (!(mask & SDHCI_RESET_ALL))
153 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
154 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
156 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
157 SDHCI_MISC_CTRL_ENABLE_SDR50 |
158 SDHCI_MISC_CTRL_ENABLE_DDR50 |
159 SDHCI_MISC_CTRL_ENABLE_SDR104);
161 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
164 * If the board does not define a regulator for the SDHCI
165 * IO voltage, then don't advertise support for UHS modes
166 * even if the device supports it because the IO voltage
167 * cannot be configured.
169 if (!IS_ERR(host->mmc->supply.vqmmc)) {
170 /* Erratum: Enable SDHCI spec v3.00 support */
171 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
172 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
173 /* Advertise UHS modes as supported by host */
174 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
175 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
176 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
177 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
178 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
179 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
180 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
181 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
184 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
185 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
187 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
188 tegra_host->pad_calib_required = true;
190 tegra_host->ddr_signaling = false;
193 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
197 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
198 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
199 (bus_width == MMC_BUS_WIDTH_8)) {
200 ctrl &= ~SDHCI_CTRL_4BITBUS;
201 ctrl |= SDHCI_CTRL_8BITBUS;
203 ctrl &= ~SDHCI_CTRL_8BITBUS;
204 if (bus_width == MMC_BUS_WIDTH_4)
205 ctrl |= SDHCI_CTRL_4BITBUS;
207 ctrl &= ~SDHCI_CTRL_4BITBUS;
209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
212 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
218 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
219 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
220 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
223 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
225 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
226 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
227 unsigned long host_clk;
230 return sdhci_set_clock(host, clock);
232 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
233 clk_set_rate(pltfm_host->clk, host_clk);
234 host->max_clk = clk_get_rate(pltfm_host->clk);
236 sdhci_set_clock(host, clock);
238 if (tegra_host->pad_calib_required) {
239 tegra_sdhci_pad_autocalib(host);
240 tegra_host->pad_calib_required = false;
244 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
248 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
250 if (timing == MMC_TIMING_UHS_DDR50)
251 tegra_host->ddr_signaling = true;
253 return sdhci_set_uhs_signaling(host, timing);
256 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
258 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
261 * DDR modes require the host to run at double the card frequency, so
262 * the maximum rate we can support is half of the module input clock.
264 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
267 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
271 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
272 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
273 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
274 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
277 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
279 unsigned int min, max;
282 * Start search for minimum tap value at 10, as smaller values are
283 * may wrongly be reported as working but fail at higher speeds,
284 * according to the TRM.
288 tegra_sdhci_set_tap(host, min);
289 if (!mmc_send_tuning(host->mmc, opcode, NULL))
294 /* Find the maximum tap value that still passes. */
297 tegra_sdhci_set_tap(host, max);
298 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
305 /* The TRM states the ideal tap value is at 75% in the passing range. */
306 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
308 return mmc_send_tuning(host->mmc, opcode, NULL);
311 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
313 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
314 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
315 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
317 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
318 tegra_host->pad_calib_required = true;
321 static const struct sdhci_ops tegra_sdhci_ops = {
322 .get_ro = tegra_sdhci_get_ro,
323 .read_w = tegra_sdhci_readw,
324 .write_l = tegra_sdhci_writel,
325 .set_clock = tegra_sdhci_set_clock,
326 .set_bus_width = tegra_sdhci_set_bus_width,
327 .reset = tegra_sdhci_reset,
328 .platform_execute_tuning = tegra_sdhci_execute_tuning,
329 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
330 .voltage_switch = tegra_sdhci_voltage_switch,
331 .get_max_clock = tegra_sdhci_get_max_clock,
334 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
335 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
336 SDHCI_QUIRK_SINGLE_POWER_WRITE |
337 SDHCI_QUIRK_NO_HISPD_BIT |
338 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
339 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
340 .ops = &tegra_sdhci_ops,
343 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
344 .pdata = &sdhci_tegra20_pdata,
345 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
346 NVQUIRK_ENABLE_BLOCK_GAP_DET,
349 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
350 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
351 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
352 SDHCI_QUIRK_SINGLE_POWER_WRITE |
353 SDHCI_QUIRK_NO_HISPD_BIT |
354 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
355 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
356 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
357 .ops = &tegra_sdhci_ops,
360 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
361 .pdata = &sdhci_tegra30_pdata,
362 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
363 NVQUIRK_ENABLE_SDR50 |
364 NVQUIRK_ENABLE_SDR104 |
365 NVQUIRK_HAS_PADCALIB,
368 static const struct sdhci_ops tegra114_sdhci_ops = {
369 .get_ro = tegra_sdhci_get_ro,
370 .read_w = tegra_sdhci_readw,
371 .write_w = tegra_sdhci_writew,
372 .write_l = tegra_sdhci_writel,
373 .set_clock = tegra_sdhci_set_clock,
374 .set_bus_width = tegra_sdhci_set_bus_width,
375 .reset = tegra_sdhci_reset,
376 .platform_execute_tuning = tegra_sdhci_execute_tuning,
377 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
378 .voltage_switch = tegra_sdhci_voltage_switch,
379 .get_max_clock = tegra_sdhci_get_max_clock,
382 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
383 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
384 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
385 SDHCI_QUIRK_SINGLE_POWER_WRITE |
386 SDHCI_QUIRK_NO_HISPD_BIT |
387 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
388 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
389 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
390 .ops = &tegra114_sdhci_ops,
393 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
394 .pdata = &sdhci_tegra114_pdata,
397 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
398 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
399 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
400 SDHCI_QUIRK_SINGLE_POWER_WRITE |
401 SDHCI_QUIRK_NO_HISPD_BIT |
402 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
403 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
404 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
406 * The TRM states that the SD/MMC controller found on
407 * Tegra124 can address 34 bits (the maximum supported by
408 * the Tegra memory controller), but tests show that DMA
409 * to or from above 4 GiB doesn't work. This is possibly
410 * caused by missing programming, though it's not obvious
411 * what sequence is required. Mark 64-bit DMA broken for
412 * now to fix this for existing users (e.g. Nyan boards).
414 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
415 .ops = &tegra114_sdhci_ops,
418 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
419 .pdata = &sdhci_tegra124_pdata,
422 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
423 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
424 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
425 SDHCI_QUIRK_SINGLE_POWER_WRITE |
426 SDHCI_QUIRK_NO_HISPD_BIT |
427 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
428 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
429 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
430 .ops = &tegra114_sdhci_ops,
433 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
434 .pdata = &sdhci_tegra210_pdata,
437 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
438 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
439 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
440 SDHCI_QUIRK_SINGLE_POWER_WRITE |
441 SDHCI_QUIRK_NO_HISPD_BIT |
442 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
443 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
444 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
445 .ops = &tegra114_sdhci_ops,
448 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
449 .pdata = &sdhci_tegra186_pdata,
452 static const struct of_device_id sdhci_tegra_dt_match[] = {
453 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
454 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
455 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
456 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
457 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
458 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
461 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
463 static int sdhci_tegra_probe(struct platform_device *pdev)
465 const struct of_device_id *match;
466 const struct sdhci_tegra_soc_data *soc_data;
467 struct sdhci_host *host;
468 struct sdhci_pltfm_host *pltfm_host;
469 struct sdhci_tegra *tegra_host;
473 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
476 soc_data = match->data;
478 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
480 return PTR_ERR(host);
481 pltfm_host = sdhci_priv(host);
483 tegra_host = sdhci_pltfm_priv(pltfm_host);
484 tegra_host->ddr_signaling = false;
485 tegra_host->pad_calib_required = false;
486 tegra_host->soc_data = soc_data;
488 rc = mmc_of_parse(host->mmc);
492 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
493 host->mmc->caps |= MMC_CAP_1_8V_DDR;
495 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
497 if (IS_ERR(tegra_host->power_gpio)) {
498 rc = PTR_ERR(tegra_host->power_gpio);
502 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
504 dev_err(mmc_dev(host->mmc), "clk err\n");
508 clk_prepare_enable(clk);
509 pltfm_host->clk = clk;
511 tegra_host->rst = devm_reset_control_get(&pdev->dev, "sdhci");
512 if (IS_ERR(tegra_host->rst)) {
513 rc = PTR_ERR(tegra_host->rst);
514 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
518 rc = reset_control_assert(tegra_host->rst);
522 usleep_range(2000, 4000);
524 rc = reset_control_deassert(tegra_host->rst);
528 usleep_range(2000, 4000);
530 rc = sdhci_add_host(host);
537 reset_control_assert(tegra_host->rst);
539 clk_disable_unprepare(pltfm_host->clk);
543 sdhci_pltfm_free(pdev);
547 static int sdhci_tegra_remove(struct platform_device *pdev)
549 struct sdhci_host *host = platform_get_drvdata(pdev);
550 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
551 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
553 sdhci_remove_host(host, 0);
555 reset_control_assert(tegra_host->rst);
556 usleep_range(2000, 4000);
557 clk_disable_unprepare(pltfm_host->clk);
559 sdhci_pltfm_free(pdev);
564 static struct platform_driver sdhci_tegra_driver = {
566 .name = "sdhci-tegra",
567 .of_match_table = sdhci_tegra_dt_match,
568 .pm = &sdhci_pltfm_pmops,
570 .probe = sdhci_tegra_probe,
571 .remove = sdhci_tegra_remove,
574 module_platform_driver(sdhci_tegra_driver);
576 MODULE_DESCRIPTION("SDHCI driver for Tegra");
577 MODULE_AUTHOR("Google, Inc.");
578 MODULE_LICENSE("GPL v2");