drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 #define ADMA_SIZE       ((128 * 2 + 1) * 4)
  48
  49 static unsigned int debug_quirks = 0;
  50 static unsigned int debug_quirks2;
  51
  52 static void sdhci_finish_data(struct sdhci_host *);
  53
  54 static void sdhci_finish_command(struct sdhci_host *);
  55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  56 static void sdhci_tuning_timer(unsigned long data);
  57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  58
  59 #ifdef CONFIG_PM_RUNTIME
  60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  64 #else
  65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  66 {
  67         return 0;
  68 }
  69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  70 {
  71         return 0;
  72 }
  73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  74 {
  75 }
  76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  77 {
  78 }
  79 #endif
  80
  81 static void sdhci_dumpregs(struct sdhci_host *host)
  82 {
  83         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  84                 mmc_hostname(host->mmc));
  85
  86         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  87                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  88                 sdhci_readw(host, SDHCI_HOST_VERSION));
  89         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  90                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  91                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  92         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  93                 sdhci_readl(host, SDHCI_ARGUMENT),
  94                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  95         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  97                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  98         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  99                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 100                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 101         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 102                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 103                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 104         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 105                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 106                 sdhci_readl(host, SDHCI_INT_STATUS));
 107         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 108                 sdhci_readl(host, SDHCI_INT_ENABLE),
 109                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 110         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 111                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 112                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 113         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 114                 sdhci_readl(host, SDHCI_CAPABILITIES),
 115                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 116         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 117                 sdhci_readw(host, SDHCI_COMMAND),
 118                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 119         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 120                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 121
 122         if (host->flags & SDHCI_USE_ADMA)
 123                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 124                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 125                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 126
 127         pr_debug(DRIVER_NAME ": ===========================================\n");
 128 }
 129
 130 /*****************************************************************************\
 131  *                                                                           *
 132  * Low level functions                                                       *
 133  *                                                                           *
 134 \*****************************************************************************/
 135
 136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 137 {
 138         u32 present;
 139
 140         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 141             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 142                 return;
 143
 144         if (enable) {
 145                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 146                                       SDHCI_CARD_PRESENT;
 147
 148                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 149                                        SDHCI_INT_CARD_INSERT;
 150         } else {
 151                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 152         }
 153
 154         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 155         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 156 }
 157
 158 static void sdhci_enable_card_detection(struct sdhci_host *host)
 159 {
 160         sdhci_set_card_detection(host, true);
 161 }
 162
 163 static void sdhci_disable_card_detection(struct sdhci_host *host)
 164 {
 165         sdhci_set_card_detection(host, false);
 166 }
 167
 168 void sdhci_reset(struct sdhci_host *host, u8 mask)
 169 {
 170         unsigned long timeout;
 171
 172         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 173
 174         if (mask & SDHCI_RESET_ALL) {
 175                 host->clock = 0;
 176                 /* Reset-all turns off SD Bus Power */
 177                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 178                         sdhci_runtime_pm_bus_off(host);
 179         }
 180
 181         /* Wait max 100 ms */
 182         timeout = 100;
 183
 184         /* hw clears the bit when it's done */
 185         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 186                 if (timeout == 0) {
 187                         pr_err("%s: Reset 0x%x never completed.\n",
 188                                 mmc_hostname(host->mmc), (int)mask);
 189                         sdhci_dumpregs(host);
 190                         return;
 191                 }
 192                 timeout--;
 193                 mdelay(1);
 194         }
 195 }
 196 EXPORT_SYMBOL_GPL(sdhci_reset);
 197
 198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 199 {
 200         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 201                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 202                         SDHCI_CARD_PRESENT))
 203                         return;
 204         }
 205
 206         host->ops->reset(host, mask);
 207
 208         if (mask & SDHCI_RESET_ALL) {
 209                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 210                         if (host->ops->enable_dma)
 211                                 host->ops->enable_dma(host);
 212                 }
 213
 214                 /* Resetting the controller clears many */
 215                 host->preset_enabled = false;
 216         }
 217 }
 218
 219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 220
 221 static void sdhci_init(struct sdhci_host *host, int soft)
 222 {
 223         if (soft)
 224                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 225         else
 226                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 227
 228         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 229                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 230                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 231                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 232                     SDHCI_INT_RESPONSE;
 233
 234         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 235         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 236
 237         if (soft) {
 238                 /* force clock reconfiguration */
 239                 host->clock = 0;
 240                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 241         }
 242 }
 243
 244 static void sdhci_reinit(struct sdhci_host *host)
 245 {
 246         sdhci_init(host, 0);
 247         /*
 248          * Retuning stuffs are affected by different cards inserted and only
 249          * applicable to UHS-I cards. So reset these fields to their initial
 250          * value when card is removed.
 251          */
 252         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 253                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 254
 255                 del_timer_sync(&host->tuning_timer);
 256                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 257                 host->mmc->max_blk_count =
 258                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 259         }
 260         sdhci_enable_card_detection(host);
 261 }
 262
 263 static void sdhci_activate_led(struct sdhci_host *host)
 264 {
 265         u8 ctrl;
 266
 267         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 268         ctrl |= SDHCI_CTRL_LED;
 269         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 270 }
 271
 272 static void sdhci_deactivate_led(struct sdhci_host *host)
 273 {
 274         u8 ctrl;
 275
 276         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 277         ctrl &= ~SDHCI_CTRL_LED;
 278         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 279 }
 280
 281 #ifdef SDHCI_USE_LEDS_CLASS
 282 static void sdhci_led_control(struct led_classdev *led,
 283         enum led_brightness brightness)
 284 {
 285         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&host->lock, flags);
 289
 290         if (host->runtime_suspended)
 291                 goto out;
 292
 293         if (brightness == LED_OFF)
 294                 sdhci_deactivate_led(host);
 295         else
 296                 sdhci_activate_led(host);
 297 out:
 298         spin_unlock_irqrestore(&host->lock, flags);
 299 }
 300 #endif
 301
 302 /*****************************************************************************\
 303  *                                                                           *
 304  * Core functions                                                            *
 305  *                                                                           *
 306 \*****************************************************************************/
 307
 308 static void sdhci_read_block_pio(struct sdhci_host *host)
 309 {
 310         unsigned long flags;
 311         size_t blksize, len, chunk;
 312         u32 uninitialized_var(scratch);
 313         u8 *buf;
 314
 315         DBG("PIO reading\n");
 316
 317         blksize = host->data->blksz;
 318         chunk = 0;
 319
 320         local_irq_save(flags);
 321
 322         while (blksize) {
 323                 if (!sg_miter_next(&host->sg_miter))
 324                         BUG();
 325
 326                 len = min(host->sg_miter.length, blksize);
 327
 328                 blksize -= len;
 329                 host->sg_miter.consumed = len;
 330
 331                 buf = host->sg_miter.addr;
 332
 333                 while (len) {
 334                         if (chunk == 0) {
 335                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 336                                 chunk = 4;
 337                         }
 338
 339                         *buf = scratch & 0xFF;
 340
 341                         buf++;
 342                         scratch >>= 8;
 343                         chunk--;
 344                         len--;
 345                 }
 346         }
 347
 348         sg_miter_stop(&host->sg_miter);
 349
 350         local_irq_restore(flags);
 351 }
 352
 353 static void sdhci_write_block_pio(struct sdhci_host *host)
 354 {
 355         unsigned long flags;
 356         size_t blksize, len, chunk;
 357         u32 scratch;
 358         u8 *buf;
 359
 360         DBG("PIO writing\n");
 361
 362         blksize = host->data->blksz;
 363         chunk = 0;
 364         scratch = 0;
 365
 366         local_irq_save(flags);
 367
 368         while (blksize) {
 369                 if (!sg_miter_next(&host->sg_miter))
 370                         BUG();
 371
 372                 len = min(host->sg_miter.length, blksize);
 373
 374                 blksize -= len;
 375                 host->sg_miter.consumed = len;
 376
 377                 buf = host->sg_miter.addr;
 378
 379                 while (len) {
 380                         scratch |= (u32)*buf << (chunk * 8);
 381
 382                         buf++;
 383                         chunk++;
 384                         len--;
 385
 386                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 387                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 388                                 chunk = 0;
 389                                 scratch = 0;
 390                         }
 391                 }
 392         }
 393
 394         sg_miter_stop(&host->sg_miter);
 395
 396         local_irq_restore(flags);
 397 }
 398
 399 static void sdhci_transfer_pio(struct sdhci_host *host)
 400 {
 401         u32 mask;
 402
 403         BUG_ON(!host->data);
 404
 405         if (host->blocks == 0)
 406                 return;
 407
 408         if (host->data->flags & MMC_DATA_READ)
 409                 mask = SDHCI_DATA_AVAILABLE;
 410         else
 411                 mask = SDHCI_SPACE_AVAILABLE;
 412
 413         /*
 414          * Some controllers (JMicron JMB38x) mess up the buffer bits
 415          * for transfers < 4 bytes. As long as it is just one block,
 416          * we can ignore the bits.
 417          */
 418         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 419                 (host->data->blocks == 1))
 420                 mask = ~0;
 421
 422         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 423                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 424                         udelay(100);
 425
 426                 if (host->data->flags & MMC_DATA_READ)
 427                         sdhci_read_block_pio(host);
 428                 else
 429                         sdhci_write_block_pio(host);
 430
 431                 host->blocks--;
 432                 if (host->blocks == 0)
 433                         break;
 434         }
 435
 436         DBG("PIO transfer complete.\n");
 437 }
 438
 439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 440 {
 441         local_irq_save(*flags);
 442         return kmap_atomic(sg_page(sg)) + sg->offset;
 443 }
 444
 445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 446 {
 447         kunmap_atomic(buffer);
 448         local_irq_restore(*flags);
 449 }
 450
 451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 452 {
 453         __le32 *dataddr = (__le32 __force *)(desc + 4);
 454         __le16 *cmdlen = (__le16 __force *)desc;
 455
 456         /* SDHCI specification says ADMA descriptors should be 4 byte
 457          * aligned, so using 16 or 32bit operations should be safe. */
 458
 459         cmdlen[0] = cpu_to_le16(cmd);
 460         cmdlen[1] = cpu_to_le16(len);
 461
 462         dataddr[0] = cpu_to_le32(addr);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         u8 *desc;
 471         u8 *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, 128 * 4, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & 0x3);
 496
 497         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 498                 data->sg, data->sg_len, direction);
 499         if (host->sg_count == 0)
 500                 goto unmap_align;
 501
 502         desc = host->adma_desc;
 503         align = host->align_buffer;
 504
 505         align_addr = host->align_addr;
 506
 507         for_each_sg(data->sg, sg, host->sg_count, i) {
 508                 addr = sg_dma_address(sg);
 509                 len = sg_dma_len(sg);
 510
 511                 /*
 512                  * The SDHCI specification states that ADMA
 513                  * addresses must be 32-bit aligned. If they
 514                  * aren't, then we use a bounce buffer for
 515                  * the (up to three) bytes that screw up the
 516                  * alignment.
 517                  */
 518                 offset = (4 - (addr & 0x3)) & 0x3;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 523                                 memcpy(align, buffer, offset);
 524                                 sdhci_kunmap_atomic(buffer, &flags);
 525                         }
 526
 527                         /* tran, valid */
 528                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += 4;
 533                         align_addr += 4;
 534
 535                         desc += 8;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 /* tran, valid */
 544                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 545                 desc += 8;
 546
 547                 /*
 548                  * If this triggers then we have a calculation bug
 549                  * somewhere. :/
 550                  */
 551                 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
 552         }
 553
 554         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 555                 /*
 556                 * Mark the last descriptor as the terminating descriptor
 557                 */
 558                 if (desc != host->adma_desc) {
 559                         desc -= 8;
 560                         desc[0] |= 0x2; /* end */
 561                 }
 562         } else {
 563                 /*
 564                 * Add a terminating entry.
 565                 */
 566
 567                 /* nop, end, valid */
 568                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 569         }
 570
 571         /*
 572          * Resync align buffer as we might have changed it.
 573          */
 574         if (data->flags & MMC_DATA_WRITE) {
 575                 dma_sync_single_for_device(mmc_dev(host->mmc),
 576                         host->align_addr, 128 * 4, direction);
 577         }
 578
 579         return 0;
 580
 581 unmap_align:
 582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 583                 128 * 4, direction);
 584 fail:
 585         return -EINVAL;
 586 }
 587
 588 static void sdhci_adma_table_post(struct sdhci_host *host,
 589         struct mmc_data *data)
 590 {
 591         int direction;
 592
 593         struct scatterlist *sg;
 594         int i, size;
 595         u8 *align;
 596         char *buffer;
 597         unsigned long flags;
 598         bool has_unaligned;
 599
 600         if (data->flags & MMC_DATA_READ)
 601                 direction = DMA_FROM_DEVICE;
 602         else
 603                 direction = DMA_TO_DEVICE;
 604
 605         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 606                 128 * 4, direction);
 607
 608         /* Do a quick scan of the SG list for any unaligned mappings */
 609         has_unaligned = false;
 610         for_each_sg(data->sg, sg, host->sg_count, i)
 611                 if (sg_dma_address(sg) & 3) {
 612                         has_unaligned = true;
 613                         break;
 614                 }
 615
 616         if (has_unaligned && data->flags & MMC_DATA_READ) {
 617                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 618                         data->sg_len, direction);
 619
 620                 align = host->align_buffer;
 621
 622                 for_each_sg(data->sg, sg, host->sg_count, i) {
 623                         if (sg_dma_address(sg) & 0x3) {
 624                                 size = 4 - (sg_dma_address(sg) & 0x3);
 625
 626                                 buffer = sdhci_kmap_atomic(sg, &flags);
 627                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 628                                 memcpy(buffer, align, size);
 629                                 sdhci_kunmap_atomic(buffer, &flags);
 630
 631                                 align += 4;
 632                         }
 633                 }
 634         }
 635
 636         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 637                 data->sg_len, direction);
 638 }
 639
 640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 641 {
 642         u8 count;
 643         struct mmc_data *data = cmd->data;
 644         unsigned target_timeout, current_timeout;
 645
 646         /*
 647          * If the host controller provides us with an incorrect timeout
 648          * value, just skip the check and use 0xE.  The hardware may take
 649          * longer to time out, but that's much better than having a too-short
 650          * timeout value.
 651          */
 652         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 653                 return 0xE;
 654
 655         /* Unspecified timeout, assume max */
 656         if (!data && !cmd->busy_timeout)
 657                 return 0xE;
 658
 659         /* timeout in us */
 660         if (!data)
 661                 target_timeout = cmd->busy_timeout * 1000;
 662         else {
 663                 target_timeout = data->timeout_ns / 1000;
 664                 if (host->clock)
 665                         target_timeout += data->timeout_clks / host->clock;
 666         }
 667
 668         /*
 669          * Figure out needed cycles.
 670          * We do this in steps in order to fit inside a 32 bit int.
 671          * The first step is the minimum timeout, which will have a
 672          * minimum resolution of 6 bits:
 673          * (1) 2^13*1000 > 2^22,
 674          * (2) host->timeout_clk < 2^16
 675          *     =>
 676          *     (1) / (2) > 2^6
 677          */
 678         count = 0;
 679         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 680         while (current_timeout < target_timeout) {
 681                 count++;
 682                 current_timeout <<= 1;
 683                 if (count >= 0xF)
 684                         break;
 685         }
 686
 687         if (count >= 0xF) {
 688                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 689                     mmc_hostname(host->mmc), count, cmd->opcode);
 690                 count = 0xE;
 691         }
 692
 693         return count;
 694 }
 695
 696 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 697 {
 698         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 699         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 700
 701         if (host->flags & SDHCI_REQ_USE_DMA)
 702                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 703         else
 704                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 705
 706         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 707         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 708 }
 709
 710 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 711 {
 712         u8 count;
 713         u8 ctrl;
 714         struct mmc_data *data = cmd->data;
 715         int ret;
 716
 717         WARN_ON(host->data);
 718
 719         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 720                 count = sdhci_calc_timeout(host, cmd);
 721                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 722         }
 723
 724         if (!data)
 725                 return;
 726
 727         /* Sanity checks */
 728         BUG_ON(data->blksz * data->blocks > 524288);
 729         BUG_ON(data->blksz > host->mmc->max_blk_size);
 730         BUG_ON(data->blocks > 65535);
 731
 732         host->data = data;
 733         host->data_early = 0;
 734         host->data->bytes_xfered = 0;
 735
 736         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 737                 host->flags |= SDHCI_REQ_USE_DMA;
 738
 739         /*
 740          * FIXME: This doesn't account for merging when mapping the
 741          * scatterlist.
 742          */
 743         if (host->flags & SDHCI_REQ_USE_DMA) {
 744                 int broken, i;
 745                 struct scatterlist *sg;
 746
 747                 broken = 0;
 748                 if (host->flags & SDHCI_USE_ADMA) {
 749                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 750                                 broken = 1;
 751                 } else {
 752                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 753                                 broken = 1;
 754                 }
 755
 756                 if (unlikely(broken)) {
 757                         for_each_sg(data->sg, sg, data->sg_len, i) {
 758                                 if (sg->length & 0x3) {
 759                                         DBG("Reverting to PIO because of "
 760                                                 "transfer size (%d)\n",
 761                                                 sg->length);
 762                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 763                                         break;
 764                                 }
 765                         }
 766                 }
 767         }
 768
 769         /*
 770          * The assumption here being that alignment is the same after
 771          * translation to device address space.
 772          */
 773         if (host->flags & SDHCI_REQ_USE_DMA) {
 774                 int broken, i;
 775                 struct scatterlist *sg;
 776
 777                 broken = 0;
 778                 if (host->flags & SDHCI_USE_ADMA) {
 779                         /*
 780                          * As we use 3 byte chunks to work around
 781                          * alignment problems, we need to check this
 782                          * quirk.
 783                          */
 784                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 785                                 broken = 1;
 786                 } else {
 787                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 788                                 broken = 1;
 789                 }
 790
 791                 if (unlikely(broken)) {
 792                         for_each_sg(data->sg, sg, data->sg_len, i) {
 793                                 if (sg->offset & 0x3) {
 794                                         DBG("Reverting to PIO because of "
 795                                                 "bad alignment\n");
 796                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 797                                         break;
 798                                 }
 799                         }
 800                 }
 801         }
 802
 803         if (host->flags & SDHCI_REQ_USE_DMA) {
 804                 if (host->flags & SDHCI_USE_ADMA) {
 805                         ret = sdhci_adma_table_pre(host, data);
 806                         if (ret) {
 807                                 /*
 808                                  * This only happens when someone fed
 809                                  * us an invalid request.
 810                                  */
 811                                 WARN_ON(1);
 812                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 813                         } else {
 814                                 sdhci_writel(host, host->adma_addr,
 815                                         SDHCI_ADMA_ADDRESS);
 816                         }
 817                 } else {
 818                         int sg_cnt;
 819
 820                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 821                                         data->sg, data->sg_len,
 822                                         (data->flags & MMC_DATA_READ) ?
 823                                                 DMA_FROM_DEVICE :
 824                                                 DMA_TO_DEVICE);
 825                         if (sg_cnt == 0) {
 826                                 /*
 827                                  * This only happens when someone fed
 828                                  * us an invalid request.
 829                                  */
 830                                 WARN_ON(1);
 831                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 832                         } else {
 833                                 WARN_ON(sg_cnt != 1);
 834                                 sdhci_writel(host, sg_dma_address(data->sg),
 835                                         SDHCI_DMA_ADDRESS);
 836                         }
 837                 }
 838         }
 839
 840         /*
 841          * Always adjust the DMA selection as some controllers
 842          * (e.g. JMicron) can't do PIO properly when the selection
 843          * is ADMA.
 844          */
 845         if (host->version >= SDHCI_SPEC_200) {
 846                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 847                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 848                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 849                         (host->flags & SDHCI_USE_ADMA))
 850                         ctrl |= SDHCI_CTRL_ADMA32;
 851                 else
 852                         ctrl |= SDHCI_CTRL_SDMA;
 853                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 854         }
 855
 856         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 857                 int flags;
 858
 859                 flags = SG_MITER_ATOMIC;
 860                 if (host->data->flags & MMC_DATA_READ)
 861                         flags |= SG_MITER_TO_SG;
 862                 else
 863                         flags |= SG_MITER_FROM_SG;
 864                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 865                 host->blocks = data->blocks;
 866         }
 867
 868         sdhci_set_transfer_irqs(host);
 869
 870         /* Set the DMA boundary value and block size */
 871         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 872                 data->blksz), SDHCI_BLOCK_SIZE);
 873         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 874 }
 875
 876 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 877         struct mmc_command *cmd)
 878 {
 879         u16 mode;
 880         struct mmc_data *data = cmd->data;
 881
 882         if (data == NULL) {
 883                 /* clear Auto CMD settings for no data CMDs */
 884                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 885                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 886                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 887                 return;
 888         }
 889
 890         WARN_ON(!host->data);
 891
 892         mode = SDHCI_TRNS_BLK_CNT_EN;
 893         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 894                 mode |= SDHCI_TRNS_MULTI;
 895                 /*
 896                  * If we are sending CMD23, CMD12 never gets sent
 897                  * on successful completion (so no Auto-CMD12).
 898                  */
 899                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 900                         mode |= SDHCI_TRNS_AUTO_CMD12;
 901                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 902                         mode |= SDHCI_TRNS_AUTO_CMD23;
 903                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 904                 }
 905         }
 906
 907         if (data->flags & MMC_DATA_READ)
 908                 mode |= SDHCI_TRNS_READ;
 909         if (host->flags & SDHCI_REQ_USE_DMA)
 910                 mode |= SDHCI_TRNS_DMA;
 911
 912         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 913 }
 914
 915 static void sdhci_finish_data(struct sdhci_host *host)
 916 {
 917         struct mmc_data *data;
 918
 919         BUG_ON(!host->data);
 920
 921         data = host->data;
 922         host->data = NULL;
 923
 924         if (host->flags & SDHCI_REQ_USE_DMA) {
 925                 if (host->flags & SDHCI_USE_ADMA)
 926                         sdhci_adma_table_post(host, data);
 927                 else {
 928                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 929                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 930                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 931                 }
 932         }
 933
 934         /*
 935          * The specification states that the block count register must
 936          * be updated, but it does not specify at what point in the
 937          * data flow. That makes the register entirely useless to read
 938          * back so we have to assume that nothing made it to the card
 939          * in the event of an error.
 940          */
 941         if (data->error)
 942                 data->bytes_xfered = 0;
 943         else
 944                 data->bytes_xfered = data->blksz * data->blocks;
 945
 946         /*
 947          * Need to send CMD12 if -
 948          * a) open-ended multiblock transfer (no CMD23)
 949          * b) error in multiblock transfer
 950          */
 951         if (data->stop &&
 952             (data->error ||
 953              !host->mrq->sbc)) {
 954
 955                 /*
 956                  * The controller needs a reset of internal state machines
 957                  * upon error conditions.
 958                  */
 959                 if (data->error) {
 960                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 961                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 962                 }
 963
 964                 sdhci_send_command(host, data->stop);
 965         } else
 966                 tasklet_schedule(&host->finish_tasklet);
 967 }
 968
 969 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 970 {
 971         int flags;
 972         u32 mask;
 973         unsigned long timeout;
 974
 975         WARN_ON(host->cmd);
 976
 977         /* Wait max 10 ms */
 978         timeout = 10;
 979
 980         mask = SDHCI_CMD_INHIBIT;
 981         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 982                 mask |= SDHCI_DATA_INHIBIT;
 983
 984         /* We shouldn't wait for data inihibit for stop commands, even
 985            though they might use busy signaling */
 986         if (host->mrq->data && (cmd == host->mrq->data->stop))
 987                 mask &= ~SDHCI_DATA_INHIBIT;
 988
 989         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 990                 if (timeout == 0) {
 991                         pr_err("%s: Controller never released "
 992                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 993                         sdhci_dumpregs(host);
 994                         cmd->error = -EIO;
 995                         tasklet_schedule(&host->finish_tasklet);
 996                         return;
 997                 }
 998                 timeout--;
 999                 mdelay(1);
1000         }
1001
1002         timeout = jiffies;
1003         if (!cmd->data && cmd->busy_timeout > 9000)
1004                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1005         else
1006                 timeout += 10 * HZ;
1007         mod_timer(&host->timer, timeout);
1008
1009         host->cmd = cmd;
1010
1011         sdhci_prepare_data(host, cmd);
1012
1013         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1014
1015         sdhci_set_transfer_mode(host, cmd);
1016
1017         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1018                 pr_err("%s: Unsupported response type!\n",
1019                         mmc_hostname(host->mmc));
1020                 cmd->error = -EINVAL;
1021                 tasklet_schedule(&host->finish_tasklet);
1022                 return;
1023         }
1024
1025         if (!(cmd->flags & MMC_RSP_PRESENT))
1026                 flags = SDHCI_CMD_RESP_NONE;
1027         else if (cmd->flags & MMC_RSP_136)
1028                 flags = SDHCI_CMD_RESP_LONG;
1029         else if (cmd->flags & MMC_RSP_BUSY)
1030                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1031         else
1032                 flags = SDHCI_CMD_RESP_SHORT;
1033
1034         if (cmd->flags & MMC_RSP_CRC)
1035                 flags |= SDHCI_CMD_CRC;
1036         if (cmd->flags & MMC_RSP_OPCODE)
1037                 flags |= SDHCI_CMD_INDEX;
1038
1039         /* CMD19 is special in that the Data Present Select should be set */
1040         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1041             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1042                 flags |= SDHCI_CMD_DATA;
1043
1044         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1045 }
1046 EXPORT_SYMBOL_GPL(sdhci_send_command);
1047
1048 static void sdhci_finish_command(struct sdhci_host *host)
1049 {
1050         int i;
1051
1052         BUG_ON(host->cmd == NULL);
1053
1054         if (host->cmd->flags & MMC_RSP_PRESENT) {
1055                 if (host->cmd->flags & MMC_RSP_136) {
1056                         /* CRC is stripped so we need to do some shifting. */
1057                         for (i = 0;i < 4;i++) {
1058                                 host->cmd->resp[i] = sdhci_readl(host,
1059                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1060                                 if (i != 3)
1061                                         host->cmd->resp[i] |=
1062                                                 sdhci_readb(host,
1063                                                 SDHCI_RESPONSE + (3-i)*4-1);
1064                         }
1065                 } else {
1066                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1067                 }
1068         }
1069
1070         host->cmd->error = 0;
1071
1072         /* Finished CMD23, now send actual command. */
1073         if (host->cmd == host->mrq->sbc) {
1074                 host->cmd = NULL;
1075                 sdhci_send_command(host, host->mrq->cmd);
1076         } else {
1077
1078                 /* Processed actual command. */
1079                 if (host->data && host->data_early)
1080                         sdhci_finish_data(host);
1081
1082                 if (!host->cmd->data)
1083                         tasklet_schedule(&host->finish_tasklet);
1084
1085                 host->cmd = NULL;
1086         }
1087 }
1088
1089 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1090 {
1091         u16 preset = 0;
1092
1093         switch (host->timing) {
1094         case MMC_TIMING_UHS_SDR12:
1095                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1096                 break;
1097         case MMC_TIMING_UHS_SDR25:
1098                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1099                 break;
1100         case MMC_TIMING_UHS_SDR50:
1101                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1102                 break;
1103         case MMC_TIMING_UHS_SDR104:
1104         case MMC_TIMING_MMC_HS200:
1105                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1106                 break;
1107         case MMC_TIMING_UHS_DDR50:
1108                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1109                 break;
1110         default:
1111                 pr_warn("%s: Invalid UHS-I mode selected\n",
1112                         mmc_hostname(host->mmc));
1113                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1114                 break;
1115         }
1116         return preset;
1117 }
1118
1119 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1120 {
1121         int div = 0; /* Initialized for compiler warning */
1122         int real_div = div, clk_mul = 1;
1123         u16 clk = 0;
1124         unsigned long timeout;
1125
1126         host->mmc->actual_clock = 0;
1127
1128         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1129
1130         if (clock == 0)
1131                 return;
1132
1133         if (host->version >= SDHCI_SPEC_300) {
1134                 if (host->preset_enabled) {
1135                         u16 pre_val;
1136
1137                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1138                         pre_val = sdhci_get_preset_value(host);
1139                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1140                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1141                         if (host->clk_mul &&
1142                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1143                                 clk = SDHCI_PROG_CLOCK_MODE;
1144                                 real_div = div + 1;
1145                                 clk_mul = host->clk_mul;
1146                         } else {
1147                                 real_div = max_t(int, 1, div << 1);
1148                         }
1149                         goto clock_set;
1150                 }
1151
1152                 /*
1153                  * Check if the Host Controller supports Programmable Clock
1154                  * Mode.
1155                  */
1156                 if (host->clk_mul) {
1157                         for (div = 1; div <= 1024; div++) {
1158                                 if ((host->max_clk * host->clk_mul / div)
1159                                         <= clock)
1160                                         break;
1161                         }
1162                         /*
1163                          * Set Programmable Clock Mode in the Clock
1164                          * Control register.
1165                          */
1166                         clk = SDHCI_PROG_CLOCK_MODE;
1167                         real_div = div;
1168                         clk_mul = host->clk_mul;
1169                         div--;
1170                 } else {
1171                         /* Version 3.00 divisors must be a multiple of 2. */
1172                         if (host->max_clk <= clock)
1173                                 div = 1;
1174                         else {
1175                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1176                                      div += 2) {
1177                                         if ((host->max_clk / div) <= clock)
1178                                                 break;
1179                                 }
1180                         }
1181                         real_div = div;
1182                         div >>= 1;
1183                 }
1184         } else {
1185                 /* Version 2.00 divisors must be a power of 2. */
1186                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1187                         if ((host->max_clk / div) <= clock)
1188                                 break;
1189                 }
1190                 real_div = div;
1191                 div >>= 1;
1192         }
1193
1194 clock_set:
1195         if (real_div)
1196                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1197
1198         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1199         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1200                 << SDHCI_DIVIDER_HI_SHIFT;
1201         clk |= SDHCI_CLOCK_INT_EN;
1202         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1203
1204         /* Wait max 20 ms */
1205         timeout = 20;
1206         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1207                 & SDHCI_CLOCK_INT_STABLE)) {
1208                 if (timeout == 0) {
1209                         pr_err("%s: Internal clock never "
1210                                 "stabilised.\n", mmc_hostname(host->mmc));
1211                         sdhci_dumpregs(host);
1212                         return;
1213                 }
1214                 timeout--;
1215                 mdelay(1);
1216         }
1217
1218         clk |= SDHCI_CLOCK_CARD_EN;
1219         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1220 }
1221 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1222
1223 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1224                             unsigned short vdd)
1225 {
1226         struct mmc_host *mmc = host->mmc;
1227         u8 pwr = 0;
1228
1229         if (!IS_ERR(mmc->supply.vmmc)) {
1230                 spin_unlock_irq(&host->lock);
1231                 mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd);
1232                 spin_lock_irq(&host->lock);
1233                 return;
1234         }
1235
1236         if (mode != MMC_POWER_OFF) {
1237                 switch (1 << vdd) {
1238                 case MMC_VDD_165_195:
1239                         pwr = SDHCI_POWER_180;
1240                         break;
1241                 case MMC_VDD_29_30:
1242                 case MMC_VDD_30_31:
1243                         pwr = SDHCI_POWER_300;
1244                         break;
1245                 case MMC_VDD_32_33:
1246                 case MMC_VDD_33_34:
1247                         pwr = SDHCI_POWER_330;
1248                         break;
1249                 default:
1250                         BUG();
1251                 }
1252         }
1253
1254         if (host->pwr == pwr)
1255                 return;
1256
1257         host->pwr = pwr;
1258
1259         if (pwr == 0) {
1260                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1261                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1262                         sdhci_runtime_pm_bus_off(host);
1263                 vdd = 0;
1264         } else {
1265                 /*
1266                  * Spec says that we should clear the power reg before setting
1267                  * a new value. Some controllers don't seem to like this though.
1268                  */
1269                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1270                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1271
1272                 /*
1273                  * At least the Marvell CaFe chip gets confused if we set the
1274                  * voltage and set turn on power at the same time, so set the
1275                  * voltage first.
1276                  */
1277                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1278                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1279
1280                 pwr |= SDHCI_POWER_ON;
1281
1282                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1283
1284                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1285                         sdhci_runtime_pm_bus_on(host);
1286
1287                 /*
1288                  * Some controllers need an extra 10ms delay of 10ms before
1289                  * they can apply clock after applying power
1290                  */
1291                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1292                         mdelay(10);
1293         }
1294 }
1295
1296 /*****************************************************************************\
1297  *                                                                           *
1298  * MMC callbacks                                                             *
1299  *                                                                           *
1300 \*****************************************************************************/
1301
1302 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1303 {
1304         struct sdhci_host *host;
1305         int present;
1306         unsigned long flags;
1307         u32 tuning_opcode;
1308
1309         host = mmc_priv(mmc);
1310
1311         sdhci_runtime_pm_get(host);
1312
1313         spin_lock_irqsave(&host->lock, flags);
1314
1315         WARN_ON(host->mrq != NULL);
1316
1317 #ifndef SDHCI_USE_LEDS_CLASS
1318         sdhci_activate_led(host);
1319 #endif
1320
1321         /*
1322          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1323          * requests if Auto-CMD12 is enabled.
1324          */
1325         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1326                 if (mrq->stop) {
1327                         mrq->data->stop = NULL;
1328                         mrq->stop = NULL;
1329                 }
1330         }
1331
1332         host->mrq = mrq;
1333
1334         /*
1335          * Firstly check card presence from cd-gpio.  The return could
1336          * be one of the following possibilities:
1337          *     negative: cd-gpio is not available
1338          *     zero: cd-gpio is used, and card is removed
1339          *     one: cd-gpio is used, and card is present
1340          */
1341         present = mmc_gpio_get_cd(host->mmc);
1342         if (present < 0) {
1343                 /* If polling, assume that the card is always present. */
1344                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1345                         present = 1;
1346                 else
1347                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1348                                         SDHCI_CARD_PRESENT;
1349         }
1350
1351         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1352                 host->mrq->cmd->error = -ENOMEDIUM;
1353                 tasklet_schedule(&host->finish_tasklet);
1354         } else {
1355                 u32 present_state;
1356
1357                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1358                 /*
1359                  * Check if the re-tuning timer has already expired and there
1360                  * is no on-going data transfer. If so, we need to execute
1361                  * tuning procedure before sending command.
1362                  */
1363                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1364                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1365                         if (mmc->card) {
1366                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1367                                 tuning_opcode =
1368                                         mmc->card->type == MMC_TYPE_MMC ?
1369                                         MMC_SEND_TUNING_BLOCK_HS200 :
1370                                         MMC_SEND_TUNING_BLOCK;
1371
1372                                 /* Here we need to set the host->mrq to NULL,
1373                                  * in case the pending finish_tasklet
1374                                  * finishes it incorrectly.
1375                                  */
1376                                 host->mrq = NULL;
1377
1378                                 spin_unlock_irqrestore(&host->lock, flags);
1379                                 sdhci_execute_tuning(mmc, tuning_opcode);
1380                                 spin_lock_irqsave(&host->lock, flags);
1381
1382                                 /* Restore original mmc_request structure */
1383                                 host->mrq = mrq;
1384                         }
1385                 }
1386
1387                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1388                         sdhci_send_command(host, mrq->sbc);
1389                 else
1390                         sdhci_send_command(host, mrq->cmd);
1391         }
1392
1393         mmiowb();
1394         spin_unlock_irqrestore(&host->lock, flags);
1395 }
1396
1397 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1398 {
1399         u8 ctrl;
1400
1401         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1402         if (width == MMC_BUS_WIDTH_8) {
1403                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1404                 if (host->version >= SDHCI_SPEC_300)
1405                         ctrl |= SDHCI_CTRL_8BITBUS;
1406         } else {
1407                 if (host->version >= SDHCI_SPEC_300)
1408                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1409                 if (width == MMC_BUS_WIDTH_4)
1410                         ctrl |= SDHCI_CTRL_4BITBUS;
1411                 else
1412                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1413         }
1414         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415 }
1416 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1417
1418 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1419 {
1420         u16 ctrl_2;
1421
1422         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1423         /* Select Bus Speed Mode for host */
1424         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1425         if ((timing == MMC_TIMING_MMC_HS200) ||
1426             (timing == MMC_TIMING_UHS_SDR104))
1427                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1428         else if (timing == MMC_TIMING_UHS_SDR12)
1429                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1430         else if (timing == MMC_TIMING_UHS_SDR25)
1431                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1432         else if (timing == MMC_TIMING_UHS_SDR50)
1433                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1434         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1435                  (timing == MMC_TIMING_MMC_DDR52))
1436                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1437         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1438 }
1439 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1440
1441 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1442 {
1443         unsigned long flags;
1444         u8 ctrl;
1445         struct mmc_host *mmc = host->mmc;
1446
1447         spin_lock_irqsave(&host->lock, flags);
1448
1449         if (host->flags & SDHCI_DEVICE_DEAD) {
1450                 spin_unlock_irqrestore(&host->lock, flags);
1451                 if (!IS_ERR(mmc->supply.vmmc) &&
1452                     ios->power_mode == MMC_POWER_OFF)
1453                         mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0);
1454                 return;
1455         }
1456
1457         /*
1458          * Reset the chip on each power off.
1459          * Should clear out any weird states.
1460          */
1461         if (ios->power_mode == MMC_POWER_OFF) {
1462                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1463                 sdhci_reinit(host);
1464         }
1465
1466         if (host->version >= SDHCI_SPEC_300 &&
1467                 (ios->power_mode == MMC_POWER_UP) &&
1468                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1469                 sdhci_enable_preset_value(host, false);
1470
1471         if (!ios->clock || ios->clock != host->clock) {
1472                 host->ops->set_clock(host, ios->clock);
1473                 host->clock = ios->clock;
1474         }
1475
1476         sdhci_set_power(host, ios->power_mode, ios->vdd);
1477
1478         if (host->ops->platform_send_init_74_clocks)
1479                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1480
1481         host->ops->set_bus_width(host, ios->bus_width);
1482
1483         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1484
1485         if ((ios->timing == MMC_TIMING_SD_HS ||
1486              ios->timing == MMC_TIMING_MMC_HS)
1487             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1488                 ctrl |= SDHCI_CTRL_HISPD;
1489         else
1490                 ctrl &= ~SDHCI_CTRL_HISPD;
1491
1492         if (host->version >= SDHCI_SPEC_300) {
1493                 u16 clk, ctrl_2;
1494
1495                 /* In case of UHS-I modes, set High Speed Enable */
1496                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1497                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1498                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1499                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1500                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1501                     (ios->timing == MMC_TIMING_UHS_SDR25))
1502                         ctrl |= SDHCI_CTRL_HISPD;
1503
1504                 if (!host->preset_enabled) {
1505                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1506                         /*
1507                          * We only need to set Driver Strength if the
1508                          * preset value enable is not set.
1509                          */
1510                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1511                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1512                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1513                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1514                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1515                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1516
1517                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1518                 } else {
1519                         /*
1520                          * According to SDHC Spec v3.00, if the Preset Value
1521                          * Enable in the Host Control 2 register is set, we
1522                          * need to reset SD Clock Enable before changing High
1523                          * Speed Enable to avoid generating clock gliches.
1524                          */
1525
1526                         /* Reset SD Clock Enable */
1527                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1528                         clk &= ~SDHCI_CLOCK_CARD_EN;
1529                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1530
1531                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1532
1533                         /* Re-enable SD Clock */
1534                         host->ops->set_clock(host, host->clock);
1535                 }
1536
1537
1538                 /* Reset SD Clock Enable */
1539                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1540                 clk &= ~SDHCI_CLOCK_CARD_EN;
1541                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1542
1543                 host->ops->set_uhs_signaling(host, ios->timing);
1544                 host->timing = ios->timing;
1545
1546                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1547                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1548                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1549                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1550                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1551                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1552                         u16 preset;
1553
1554                         sdhci_enable_preset_value(host, true);
1555                         preset = sdhci_get_preset_value(host);
1556                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1557                                 >> SDHCI_PRESET_DRV_SHIFT;
1558                 }
1559
1560                 /* Re-enable SD Clock */
1561                 host->ops->set_clock(host, host->clock);
1562         } else
1563                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1564
1565         /*
1566          * Some (ENE) controllers go apeshit on some ios operation,
1567          * signalling timeout and CRC errors even on CMD0. Resetting
1568          * it on each ios seems to solve the problem.
1569          */
1570         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1571                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1572
1573         mmiowb();
1574         spin_unlock_irqrestore(&host->lock, flags);
1575 }
1576
1577 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1578 {
1579         struct sdhci_host *host = mmc_priv(mmc);
1580
1581         sdhci_runtime_pm_get(host);
1582         sdhci_do_set_ios(host, ios);
1583         sdhci_runtime_pm_put(host);
1584 }
1585
1586 static int sdhci_do_get_cd(struct sdhci_host *host)
1587 {
1588         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1589
1590         if (host->flags & SDHCI_DEVICE_DEAD)
1591                 return 0;
1592
1593         /* If polling/nonremovable, assume that the card is always present. */
1594         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1595             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1596                 return 1;
1597
1598         /* Try slot gpio detect */
1599         if (!IS_ERR_VALUE(gpio_cd))
1600                 return !!gpio_cd;
1601
1602         /* Host native card detect */
1603         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1604 }
1605
1606 static int sdhci_get_cd(struct mmc_host *mmc)
1607 {
1608         struct sdhci_host *host = mmc_priv(mmc);
1609         int ret;
1610
1611         sdhci_runtime_pm_get(host);
1612         ret = sdhci_do_get_cd(host);
1613         sdhci_runtime_pm_put(host);
1614         return ret;
1615 }
1616
1617 static int sdhci_check_ro(struct sdhci_host *host)
1618 {
1619         unsigned long flags;
1620         int is_readonly;
1621
1622         spin_lock_irqsave(&host->lock, flags);
1623
1624         if (host->flags & SDHCI_DEVICE_DEAD)
1625                 is_readonly = 0;
1626         else if (host->ops->get_ro)
1627                 is_readonly = host->ops->get_ro(host);
1628         else
1629                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1630                                 & SDHCI_WRITE_PROTECT);
1631
1632         spin_unlock_irqrestore(&host->lock, flags);
1633
1634         /* This quirk needs to be replaced by a callback-function later */
1635         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1636                 !is_readonly : is_readonly;
1637 }
1638
1639 #define SAMPLE_COUNT    5
1640
1641 static int sdhci_do_get_ro(struct sdhci_host *host)
1642 {
1643         int i, ro_count;
1644
1645         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1646                 return sdhci_check_ro(host);
1647
1648         ro_count = 0;
1649         for (i = 0; i < SAMPLE_COUNT; i++) {
1650                 if (sdhci_check_ro(host)) {
1651                         if (++ro_count > SAMPLE_COUNT / 2)
1652                                 return 1;
1653                 }
1654                 msleep(30);
1655         }
1656         return 0;
1657 }
1658
1659 static void sdhci_hw_reset(struct mmc_host *mmc)
1660 {
1661         struct sdhci_host *host = mmc_priv(mmc);
1662
1663         if (host->ops && host->ops->hw_reset)
1664                 host->ops->hw_reset(host);
1665 }
1666
1667 static int sdhci_get_ro(struct mmc_host *mmc)
1668 {
1669         struct sdhci_host *host = mmc_priv(mmc);
1670         int ret;
1671
1672         sdhci_runtime_pm_get(host);
1673         ret = sdhci_do_get_ro(host);
1674         sdhci_runtime_pm_put(host);
1675         return ret;
1676 }
1677
1678 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1679 {
1680         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1681                 if (enable)
1682                         host->ier |= SDHCI_INT_CARD_INT;
1683                 else
1684                         host->ier &= ~SDHCI_INT_CARD_INT;
1685
1686                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1687                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1688                 mmiowb();
1689         }
1690 }
1691
1692 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1693 {
1694         struct sdhci_host *host = mmc_priv(mmc);
1695         unsigned long flags;
1696
1697         sdhci_runtime_pm_get(host);
1698
1699         spin_lock_irqsave(&host->lock, flags);
1700         if (enable)
1701                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1702         else
1703                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1704
1705         sdhci_enable_sdio_irq_nolock(host, enable);
1706         spin_unlock_irqrestore(&host->lock, flags);
1707
1708         sdhci_runtime_pm_put(host);
1709 }
1710
1711 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1712                                                 struct mmc_ios *ios)
1713 {
1714         struct mmc_host *mmc = host->mmc;
1715         u16 ctrl;
1716         int ret;
1717
1718         /*
1719          * Signal Voltage Switching is only applicable for Host Controllers
1720          * v3.00 and above.
1721          */
1722         if (host->version < SDHCI_SPEC_300)
1723                 return 0;
1724
1725         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1726
1727         switch (ios->signal_voltage) {
1728         case MMC_SIGNAL_VOLTAGE_330:
1729                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1730                 ctrl &= ~SDHCI_CTRL_VDD_180;
1731                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1732
1733                 if (!IS_ERR(mmc->supply.vqmmc)) {
1734                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1735                                                     3600000);
1736                         if (ret) {
1737                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1738                                                 " failed\n", mmc_hostname(host->mmc));
1739                                 return -EIO;
1740                         }
1741                 }
1742                 /* Wait for 5ms */
1743                 usleep_range(5000, 5500);
1744
1745                 /* 3.3V regulator output should be stable within 5 ms */
1746                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1747                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1748                         return 0;
1749
1750                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1751                                 mmc_hostname(host->mmc));
1752
1753                 return -EAGAIN;
1754         case MMC_SIGNAL_VOLTAGE_180:
1755                 if (!IS_ERR(mmc->supply.vqmmc)) {
1756                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1757                                         1700000, 1950000);
1758                         if (ret) {
1759                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1760                                                 " failed\n", mmc_hostname(host->mmc));
1761                                 return -EIO;
1762                         }
1763                 }
1764
1765                 /*
1766                  * Enable 1.8V Signal Enable in the Host Control2
1767                  * register
1768                  */
1769                 ctrl |= SDHCI_CTRL_VDD_180;
1770                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1771
1772                 /* Wait for 5ms */
1773                 usleep_range(5000, 5500);
1774
1775                 /* 1.8V regulator output should be stable within 5 ms */
1776                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1777                 if (ctrl & SDHCI_CTRL_VDD_180)
1778                         return 0;
1779
1780                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1781                                 mmc_hostname(host->mmc));
1782
1783                 return -EAGAIN;
1784         case MMC_SIGNAL_VOLTAGE_120:
1785                 if (!IS_ERR(mmc->supply.vqmmc)) {
1786                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1787                                                     1300000);
1788                         if (ret) {
1789                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1790                                                 " failed\n", mmc_hostname(host->mmc));
1791                                 return -EIO;
1792                         }
1793                 }
1794                 return 0;
1795         default:
1796                 /* No signal voltage switch required */
1797                 return 0;
1798         }
1799 }
1800
1801 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1802         struct mmc_ios *ios)
1803 {
1804         struct sdhci_host *host = mmc_priv(mmc);
1805         int err;
1806
1807         if (host->version < SDHCI_SPEC_300)
1808                 return 0;
1809         sdhci_runtime_pm_get(host);
1810         err = sdhci_do_start_signal_voltage_switch(host, ios);
1811         sdhci_runtime_pm_put(host);
1812         return err;
1813 }
1814
1815 static int sdhci_card_busy(struct mmc_host *mmc)
1816 {
1817         struct sdhci_host *host = mmc_priv(mmc);
1818         u32 present_state;
1819
1820         sdhci_runtime_pm_get(host);
1821         /* Check whether DAT[3:0] is 0000 */
1822         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1823         sdhci_runtime_pm_put(host);
1824
1825         return !(present_state & SDHCI_DATA_LVL_MASK);
1826 }
1827
1828 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1829 {
1830         struct sdhci_host *host = mmc_priv(mmc);
1831         u16 ctrl;
1832         int tuning_loop_counter = MAX_TUNING_LOOP;
1833         int err = 0;
1834         unsigned long flags;
1835
1836         sdhci_runtime_pm_get(host);
1837         spin_lock_irqsave(&host->lock, flags);
1838
1839         /*
1840          * The Host Controller needs tuning only in case of SDR104 mode
1841          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1842          * Capabilities register.
1843          * If the Host Controller supports the HS200 mode then the
1844          * tuning function has to be executed.
1845          */
1846         switch (host->timing) {
1847         case MMC_TIMING_MMC_HS200:
1848         case MMC_TIMING_UHS_SDR104:
1849                 break;
1850
1851         case MMC_TIMING_UHS_SDR50:
1852                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1853                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1854                         break;
1855                 /* FALLTHROUGH */
1856
1857         default:
1858                 spin_unlock_irqrestore(&host->lock, flags);
1859                 sdhci_runtime_pm_put(host);
1860                 return 0;
1861         }
1862
1863         if (host->ops->platform_execute_tuning) {
1864                 spin_unlock_irqrestore(&host->lock, flags);
1865                 err = host->ops->platform_execute_tuning(host, opcode);
1866                 sdhci_runtime_pm_put(host);
1867                 return err;
1868         }
1869
1870         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1871         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1872         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1873
1874         /*
1875          * As per the Host Controller spec v3.00, tuning command
1876          * generates Buffer Read Ready interrupt, so enable that.
1877          *
1878          * Note: The spec clearly says that when tuning sequence
1879          * is being performed, the controller does not generate
1880          * interrupts other than Buffer Read Ready interrupt. But
1881          * to make sure we don't hit a controller bug, we _only_
1882          * enable Buffer Read Ready interrupt here.
1883          */
1884         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1885         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1886
1887         /*
1888          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1889          * of loops reaches 40 times or a timeout of 150ms occurs.
1890          */
1891         do {
1892                 struct mmc_command cmd = {0};
1893                 struct mmc_request mrq = {NULL};
1894
1895                 cmd.opcode = opcode;
1896                 cmd.arg = 0;
1897                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1898                 cmd.retries = 0;
1899                 cmd.data = NULL;
1900                 cmd.error = 0;
1901
1902                 if (tuning_loop_counter-- == 0)
1903                         break;
1904
1905                 mrq.cmd = &cmd;
1906                 host->mrq = &mrq;
1907
1908                 /*
1909                  * In response to CMD19, the card sends 64 bytes of tuning
1910                  * block to the Host Controller. So we set the block size
1911                  * to 64 here.
1912                  */
1913                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1914                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1915                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1916                                              SDHCI_BLOCK_SIZE);
1917                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1918                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1919                                              SDHCI_BLOCK_SIZE);
1920                 } else {
1921                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1922                                      SDHCI_BLOCK_SIZE);
1923                 }
1924
1925                 /*
1926                  * The tuning block is sent by the card to the host controller.
1927                  * So we set the TRNS_READ bit in the Transfer Mode register.
1928                  * This also takes care of setting DMA Enable and Multi Block
1929                  * Select in the same register to 0.
1930                  */
1931                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1932
1933                 sdhci_send_command(host, &cmd);
1934
1935                 host->cmd = NULL;
1936                 host->mrq = NULL;
1937
1938                 spin_unlock_irqrestore(&host->lock, flags);
1939                 /* Wait for Buffer Read Ready interrupt */
1940                 wait_event_interruptible_timeout(host->buf_ready_int,
1941                                         (host->tuning_done == 1),
1942                                         msecs_to_jiffies(50));
1943                 spin_lock_irqsave(&host->lock, flags);
1944
1945                 if (!host->tuning_done) {
1946                         pr_info(DRIVER_NAME ": Timeout waiting for "
1947                                 "Buffer Read Ready interrupt during tuning "
1948                                 "procedure, falling back to fixed sampling "
1949                                 "clock\n");
1950                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1951                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1952                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1953                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1954
1955                         err = -EIO;
1956                         goto out;
1957                 }
1958
1959                 host->tuning_done = 0;
1960
1961                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1962
1963                 /* eMMC spec does not require a delay between tuning cycles */
1964                 if (opcode == MMC_SEND_TUNING_BLOCK)
1965                         mdelay(1);
1966         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1967
1968         /*
1969          * The Host Driver has exhausted the maximum number of loops allowed,
1970          * so use fixed sampling frequency.
1971          */
1972         if (tuning_loop_counter < 0) {
1973                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1974                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1975         }
1976         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1977                 pr_info(DRIVER_NAME ": Tuning procedure"
1978                         " failed, falling back to fixed sampling"
1979                         " clock\n");
1980                 err = -EIO;
1981         }
1982
1983 out:
1984         /*
1985          * If this is the very first time we are here, we start the retuning
1986          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1987          * flag won't be set, we check this condition before actually starting
1988          * the timer.
1989          */
1990         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1991             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1992                 host->flags |= SDHCI_USING_RETUNING_TIMER;
1993                 mod_timer(&host->tuning_timer, jiffies +
1994                         host->tuning_count * HZ);
1995                 /* Tuning mode 1 limits the maximum data length to 4MB */
1996                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1997         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
1998                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1999                 /* Reload the new initial value for timer */
2000                 mod_timer(&host->tuning_timer, jiffies +
2001                           host->tuning_count * HZ);
2002         }
2003
2004         /*
2005          * In case tuning fails, host controllers which support re-tuning can
2006          * try tuning again at a later time, when the re-tuning timer expires.
2007          * So for these controllers, we return 0. Since there might be other
2008          * controllers who do not have this capability, we return error for
2009          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2010          * a retuning timer to do the retuning for the card.
2011          */
2012         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2013                 err = 0;
2014
2015         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2016         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2017         spin_unlock_irqrestore(&host->lock, flags);
2018         sdhci_runtime_pm_put(host);
2019
2020         return err;
2021 }
2022
2023
2024 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2025 {
2026         /* Host Controller v3.00 defines preset value registers */
2027         if (host->version < SDHCI_SPEC_300)
2028                 return;
2029
2030         /*
2031          * We only enable or disable Preset Value if they are not already
2032          * enabled or disabled respectively. Otherwise, we bail out.
2033          */
2034         if (host->preset_enabled != enable) {
2035                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2036
2037                 if (enable)
2038                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2039                 else
2040                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2041
2042                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2043
2044                 if (enable)
2045                         host->flags |= SDHCI_PV_ENABLED;
2046                 else
2047                         host->flags &= ~SDHCI_PV_ENABLED;
2048
2049                 host->preset_enabled = enable;
2050         }
2051 }
2052
2053 static void sdhci_card_event(struct mmc_host *mmc)
2054 {
2055         struct sdhci_host *host = mmc_priv(mmc);
2056         unsigned long flags;
2057
2058         /* First check if client has provided their own card event */
2059         if (host->ops->card_event)
2060                 host->ops->card_event(host);
2061
2062         spin_lock_irqsave(&host->lock, flags);
2063
2064         /* Check host->mrq first in case we are runtime suspended */
2065         if (host->mrq && !sdhci_do_get_cd(host)) {
2066                 pr_err("%s: Card removed during transfer!\n",
2067                         mmc_hostname(host->mmc));
2068                 pr_err("%s: Resetting controller.\n",
2069                         mmc_hostname(host->mmc));
2070
2071                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2072                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2073
2074                 host->mrq->cmd->error = -ENOMEDIUM;
2075                 tasklet_schedule(&host->finish_tasklet);
2076         }
2077
2078         spin_unlock_irqrestore(&host->lock, flags);
2079 }
2080
2081 static const struct mmc_host_ops sdhci_ops = {
2082         .request        = sdhci_request,
2083         .set_ios        = sdhci_set_ios,
2084         .get_cd         = sdhci_get_cd,
2085         .get_ro         = sdhci_get_ro,
2086         .hw_reset       = sdhci_hw_reset,
2087         .enable_sdio_irq = sdhci_enable_sdio_irq,
2088         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2089         .execute_tuning                 = sdhci_execute_tuning,
2090         .card_event                     = sdhci_card_event,
2091         .card_busy      = sdhci_card_busy,
2092 };
2093
2094 /*****************************************************************************\
2095  *                                                                           *
2096  * Tasklets                                                                  *
2097  *                                                                           *
2098 \*****************************************************************************/
2099
2100 static void sdhci_tasklet_finish(unsigned long param)
2101 {
2102         struct sdhci_host *host;
2103         unsigned long flags;
2104         struct mmc_request *mrq;
2105
2106         host = (struct sdhci_host*)param;
2107
2108         spin_lock_irqsave(&host->lock, flags);
2109
2110         /*
2111          * If this tasklet gets rescheduled while running, it will
2112          * be run again afterwards but without any active request.
2113          */
2114         if (!host->mrq) {
2115                 spin_unlock_irqrestore(&host->lock, flags);
2116                 return;
2117         }
2118
2119         del_timer(&host->timer);
2120
2121         mrq = host->mrq;
2122
2123         /*
2124          * The controller needs a reset of internal state machines
2125          * upon error conditions.
2126          */
2127         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2128             ((mrq->cmd && mrq->cmd->error) ||
2129                  (mrq->data && (mrq->data->error ||
2130                   (mrq->data->stop && mrq->data->stop->error))) ||
2131                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2132
2133                 /* Some controllers need this kick or reset won't work here */
2134                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2135                         /* This is to force an update */
2136                         host->ops->set_clock(host, host->clock);
2137
2138                 /* Spec says we should do both at the same time, but Ricoh
2139                    controllers do not like that. */
2140                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2141                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2142         }
2143
2144         host->mrq = NULL;
2145         host->cmd = NULL;
2146         host->data = NULL;
2147
2148 #ifndef SDHCI_USE_LEDS_CLASS
2149         sdhci_deactivate_led(host);
2150 #endif
2151
2152         mmiowb();
2153         spin_unlock_irqrestore(&host->lock, flags);
2154
2155         mmc_request_done(host->mmc, mrq);
2156         sdhci_runtime_pm_put(host);
2157 }
2158
2159 static void sdhci_timeout_timer(unsigned long data)
2160 {
2161         struct sdhci_host *host;
2162         unsigned long flags;
2163
2164         host = (struct sdhci_host*)data;
2165
2166         spin_lock_irqsave(&host->lock, flags);
2167
2168         if (host->mrq) {
2169                 pr_err("%s: Timeout waiting for hardware "
2170                         "interrupt.\n", mmc_hostname(host->mmc));
2171                 sdhci_dumpregs(host);
2172
2173                 if (host->data) {
2174                         host->data->error = -ETIMEDOUT;
2175                         sdhci_finish_data(host);
2176                 } else {
2177                         if (host->cmd)
2178                                 host->cmd->error = -ETIMEDOUT;
2179                         else
2180                                 host->mrq->cmd->error = -ETIMEDOUT;
2181
2182                         tasklet_schedule(&host->finish_tasklet);
2183                 }
2184         }
2185
2186         mmiowb();
2187         spin_unlock_irqrestore(&host->lock, flags);
2188 }
2189
2190 static void sdhci_tuning_timer(unsigned long data)
2191 {
2192         struct sdhci_host *host;
2193         unsigned long flags;
2194
2195         host = (struct sdhci_host *)data;
2196
2197         spin_lock_irqsave(&host->lock, flags);
2198
2199         host->flags |= SDHCI_NEEDS_RETUNING;
2200
2201         spin_unlock_irqrestore(&host->lock, flags);
2202 }
2203
2204 /*****************************************************************************\
2205  *                                                                           *
2206  * Interrupt handling                                                        *
2207  *                                                                           *
2208 \*****************************************************************************/
2209
2210 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2211 {
2212         BUG_ON(intmask == 0);
2213
2214         if (!host->cmd) {
2215                 pr_err("%s: Got command interrupt 0x%08x even "
2216                         "though no command operation was in progress.\n",
2217                         mmc_hostname(host->mmc), (unsigned)intmask);
2218                 sdhci_dumpregs(host);
2219                 return;
2220         }
2221
2222         if (intmask & SDHCI_INT_TIMEOUT)
2223                 host->cmd->error = -ETIMEDOUT;
2224         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2225                         SDHCI_INT_INDEX))
2226                 host->cmd->error = -EILSEQ;
2227
2228         if (host->cmd->error) {
2229                 tasklet_schedule(&host->finish_tasklet);
2230                 return;
2231         }
2232
2233         /*
2234          * The host can send and interrupt when the busy state has
2235          * ended, allowing us to wait without wasting CPU cycles.
2236          * Unfortunately this is overloaded on the "data complete"
2237          * interrupt, so we need to take some care when handling
2238          * it.
2239          *
2240          * Note: The 1.0 specification is a bit ambiguous about this
2241          *       feature so there might be some problems with older
2242          *       controllers.
2243          */
2244         if (host->cmd->flags & MMC_RSP_BUSY) {
2245                 if (host->cmd->data)
2246                         DBG("Cannot wait for busy signal when also "
2247                                 "doing a data transfer");
2248                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2249                         return;
2250
2251                 /* The controller does not support the end-of-busy IRQ,
2252                  * fall through and take the SDHCI_INT_RESPONSE */
2253         }
2254
2255         if (intmask & SDHCI_INT_RESPONSE)
2256                 sdhci_finish_command(host);
2257 }
2258
2259 #ifdef CONFIG_MMC_DEBUG
2260 static void sdhci_show_adma_error(struct sdhci_host *host)
2261 {
2262         const char *name = mmc_hostname(host->mmc);
2263         u8 *desc = host->adma_desc;
2264         __le32 *dma;
2265         __le16 *len;
2266         u8 attr;
2267
2268         sdhci_dumpregs(host);
2269
2270         while (true) {
2271                 dma = (__le32 *)(desc + 4);
2272                 len = (__le16 *)(desc + 2);
2273                 attr = *desc;
2274
2275                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2276                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2277
2278                 desc += 8;
2279
2280                 if (attr & 2)
2281                         break;
2282         }
2283 }
2284 #else
2285 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2286 #endif
2287
2288 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2289 {
2290         u32 command;
2291         BUG_ON(intmask == 0);
2292
2293         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2294         if (intmask & SDHCI_INT_DATA_AVAIL) {
2295                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2296                 if (command == MMC_SEND_TUNING_BLOCK ||
2297                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2298                         host->tuning_done = 1;
2299                         wake_up(&host->buf_ready_int);
2300                         return;
2301                 }
2302         }
2303
2304         if (!host->data) {
2305                 /*
2306                  * The "data complete" interrupt is also used to
2307                  * indicate that a busy state has ended. See comment
2308                  * above in sdhci_cmd_irq().
2309                  */
2310                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2311                         if (intmask & SDHCI_INT_DATA_END) {
2312                                 sdhci_finish_command(host);
2313                                 return;
2314                         }
2315                 }
2316
2317                 pr_err("%s: Got data interrupt 0x%08x even "
2318                         "though no data operation was in progress.\n",
2319                         mmc_hostname(host->mmc), (unsigned)intmask);
2320                 sdhci_dumpregs(host);
2321
2322                 return;
2323         }
2324
2325         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2326                 host->data->error = -ETIMEDOUT;
2327         else if (intmask & SDHCI_INT_DATA_END_BIT)
2328                 host->data->error = -EILSEQ;
2329         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2330                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2331                         != MMC_BUS_TEST_R)
2332                 host->data->error = -EILSEQ;
2333         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2334                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2335                 sdhci_show_adma_error(host);
2336                 host->data->error = -EIO;
2337                 if (host->ops->adma_workaround)
2338                         host->ops->adma_workaround(host, intmask);
2339         }
2340
2341         if (host->data->error)
2342                 sdhci_finish_data(host);
2343         else {
2344                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2345                         sdhci_transfer_pio(host);
2346
2347                 /*
2348                  * We currently don't do anything fancy with DMA
2349                  * boundaries, but as we can't disable the feature
2350                  * we need to at least restart the transfer.
2351                  *
2352                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2353                  * should return a valid address to continue from, but as
2354                  * some controllers are faulty, don't trust them.
2355                  */
2356                 if (intmask & SDHCI_INT_DMA_END) {
2357                         u32 dmastart, dmanow;
2358                         dmastart = sg_dma_address(host->data->sg);
2359                         dmanow = dmastart + host->data->bytes_xfered;
2360                         /*
2361                          * Force update to the next DMA block boundary.
2362                          */
2363                         dmanow = (dmanow &
2364                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2365                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2366                         host->data->bytes_xfered = dmanow - dmastart;
2367                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2368                                 " next 0x%08x\n",
2369                                 mmc_hostname(host->mmc), dmastart,
2370                                 host->data->bytes_xfered, dmanow);
2371                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2372                 }
2373
2374                 if (intmask & SDHCI_INT_DATA_END) {
2375                         if (host->cmd) {
2376                                 /*
2377                                  * Data managed to finish before the
2378                                  * command completed. Make sure we do
2379                                  * things in the proper order.
2380                                  */
2381                                 host->data_early = 1;
2382                         } else {
2383                                 sdhci_finish_data(host);
2384                         }
2385                 }
2386         }
2387 }
2388
2389 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2390 {
2391         irqreturn_t result = IRQ_NONE;
2392         struct sdhci_host *host = dev_id;
2393         u32 intmask, mask, unexpected = 0;
2394         int max_loops = 16;
2395
2396         spin_lock(&host->lock);
2397
2398         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2399                 spin_unlock(&host->lock);
2400                 return IRQ_NONE;
2401         }
2402
2403         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2404         if (!intmask || intmask == 0xffffffff) {
2405                 result = IRQ_NONE;
2406                 goto out;
2407         }
2408
2409         do {
2410                 /* Clear selected interrupts. */
2411                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2412                                   SDHCI_INT_BUS_POWER);
2413                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2414
2415                 DBG("*** %s got interrupt: 0x%08x\n",
2416                         mmc_hostname(host->mmc), intmask);
2417
2418                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2419                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2420                                       SDHCI_CARD_PRESENT;
2421
2422                         /*
2423                          * There is a observation on i.mx esdhc.  INSERT
2424                          * bit will be immediately set again when it gets
2425                          * cleared, if a card is inserted.  We have to mask
2426                          * the irq to prevent interrupt storm which will
2427                          * freeze the system.  And the REMOVE gets the
2428                          * same situation.
2429                          *
2430                          * More testing are needed here to ensure it works
2431                          * for other platforms though.
2432                          */
2433                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2434                                        SDHCI_INT_CARD_REMOVE);
2435                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2436                                                SDHCI_INT_CARD_INSERT;
2437                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2438                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2439
2440                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2441                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2442
2443                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2444                                                        SDHCI_INT_CARD_REMOVE);
2445                         result = IRQ_WAKE_THREAD;
2446                 }
2447
2448                 if (intmask & SDHCI_INT_CMD_MASK)
2449                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2450
2451                 if (intmask & SDHCI_INT_DATA_MASK)
2452                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2453
2454                 if (intmask & SDHCI_INT_BUS_POWER)
2455                         pr_err("%s: Card is consuming too much power!\n",
2456                                 mmc_hostname(host->mmc));
2457
2458                 if (intmask & SDHCI_INT_CARD_INT) {
2459                         sdhci_enable_sdio_irq_nolock(host, false);
2460                         host->thread_isr |= SDHCI_INT_CARD_INT;
2461                         result = IRQ_WAKE_THREAD;
2462                 }
2463
2464                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2465                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2466                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2467                              SDHCI_INT_CARD_INT);
2468
2469                 if (intmask) {
2470                         unexpected |= intmask;
2471                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2472                 }
2473
2474                 if (result == IRQ_NONE)
2475                         result = IRQ_HANDLED;
2476
2477                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2478         } while (intmask && --max_loops);
2479 out:
2480         spin_unlock(&host->lock);
2481
2482         if (unexpected) {
2483                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2484                            mmc_hostname(host->mmc), unexpected);
2485                 sdhci_dumpregs(host);
2486         }
2487
2488         return result;
2489 }
2490
2491 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2492 {
2493         struct sdhci_host *host = dev_id;
2494         unsigned long flags;
2495         u32 isr;
2496
2497         spin_lock_irqsave(&host->lock, flags);
2498         isr = host->thread_isr;
2499         host->thread_isr = 0;
2500         spin_unlock_irqrestore(&host->lock, flags);
2501
2502         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2503                 sdhci_card_event(host->mmc);
2504                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2505         }
2506
2507         if (isr & SDHCI_INT_CARD_INT) {
2508                 sdio_run_irqs(host->mmc);
2509
2510                 spin_lock_irqsave(&host->lock, flags);
2511                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2512                         sdhci_enable_sdio_irq_nolock(host, true);
2513                 spin_unlock_irqrestore(&host->lock, flags);
2514         }
2515
2516         return isr ? IRQ_HANDLED : IRQ_NONE;
2517 }
2518
2519 /*****************************************************************************\
2520  *                                                                           *
2521  * Suspend/resume                                                            *
2522  *                                                                           *
2523 \*****************************************************************************/
2524
2525 #ifdef CONFIG_PM
2526 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2527 {
2528         u8 val;
2529         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2530                         | SDHCI_WAKE_ON_INT;
2531
2532         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2533         val |= mask ;
2534         /* Avoid fake wake up */
2535         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2536                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2537         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2538 }
2539 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2540
2541 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2542 {
2543         u8 val;
2544         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2545                         | SDHCI_WAKE_ON_INT;
2546
2547         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2548         val &= ~mask;
2549         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2550 }
2551 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2552
2553 int sdhci_suspend_host(struct sdhci_host *host)
2554 {
2555         sdhci_disable_card_detection(host);
2556
2557         /* Disable tuning since we are suspending */
2558         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2559                 del_timer_sync(&host->tuning_timer);
2560                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2561         }
2562
2563         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2564                 host->ier = 0;
2565                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2566                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2567                 free_irq(host->irq, host);
2568         } else {
2569                 sdhci_enable_irq_wakeups(host);
2570                 enable_irq_wake(host->irq);
2571         }
2572         return 0;
2573 }
2574
2575 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2576
2577 int sdhci_resume_host(struct sdhci_host *host)
2578 {
2579         int ret = 0;
2580
2581         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2582                 if (host->ops->enable_dma)
2583                         host->ops->enable_dma(host);
2584         }
2585
2586         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2587                 ret = request_threaded_irq(host->irq, sdhci_irq,
2588                                            sdhci_thread_irq, IRQF_SHARED,
2589                                            mmc_hostname(host->mmc), host);
2590                 if (ret)
2591                         return ret;
2592         } else {
2593                 sdhci_disable_irq_wakeups(host);
2594                 disable_irq_wake(host->irq);
2595         }
2596
2597         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2598             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2599                 /* Card keeps power but host controller does not */
2600                 sdhci_init(host, 0);
2601                 host->pwr = 0;
2602                 host->clock = 0;
2603                 sdhci_do_set_ios(host, &host->mmc->ios);
2604         } else {
2605                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2606                 mmiowb();
2607         }
2608
2609         sdhci_enable_card_detection(host);
2610
2611         /* Set the re-tuning expiration flag */
2612         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2613                 host->flags |= SDHCI_NEEDS_RETUNING;
2614
2615         return ret;
2616 }
2617
2618 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2619 #endif /* CONFIG_PM */
2620
2621 #ifdef CONFIG_PM_RUNTIME
2622
2623 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2624 {
2625         return pm_runtime_get_sync(host->mmc->parent);
2626 }
2627
2628 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2629 {
2630         pm_runtime_mark_last_busy(host->mmc->parent);
2631         return pm_runtime_put_autosuspend(host->mmc->parent);
2632 }
2633
2634 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2635 {
2636         if (host->runtime_suspended || host->bus_on)
2637                 return;
2638         host->bus_on = true;
2639         pm_runtime_get_noresume(host->mmc->parent);
2640 }
2641
2642 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2643 {
2644         if (host->runtime_suspended || !host->bus_on)
2645                 return;
2646         host->bus_on = false;
2647         pm_runtime_put_noidle(host->mmc->parent);
2648 }
2649
2650 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2651 {
2652         unsigned long flags;
2653
2654         /* Disable tuning since we are suspending */
2655         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2656                 del_timer_sync(&host->tuning_timer);
2657                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2658         }
2659
2660         spin_lock_irqsave(&host->lock, flags);
2661         host->ier &= SDHCI_INT_CARD_INT;
2662         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2663         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2664         spin_unlock_irqrestore(&host->lock, flags);
2665
2666         synchronize_hardirq(host->irq);
2667
2668         spin_lock_irqsave(&host->lock, flags);
2669         host->runtime_suspended = true;
2670         spin_unlock_irqrestore(&host->lock, flags);
2671
2672         return 0;
2673 }
2674 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2675
2676 int sdhci_runtime_resume_host(struct sdhci_host *host)
2677 {
2678         unsigned long flags;
2679         int host_flags = host->flags;
2680
2681         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2682                 if (host->ops->enable_dma)
2683                         host->ops->enable_dma(host);
2684         }
2685
2686         sdhci_init(host, 0);
2687
2688         /* Force clock and power re-program */
2689         host->pwr = 0;
2690         host->clock = 0;
2691         sdhci_do_set_ios(host, &host->mmc->ios);
2692
2693         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2694         if ((host_flags & SDHCI_PV_ENABLED) &&
2695                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2696                 spin_lock_irqsave(&host->lock, flags);
2697                 sdhci_enable_preset_value(host, true);
2698                 spin_unlock_irqrestore(&host->lock, flags);
2699         }
2700
2701         /* Set the re-tuning expiration flag */
2702         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2703                 host->flags |= SDHCI_NEEDS_RETUNING;
2704
2705         spin_lock_irqsave(&host->lock, flags);
2706
2707         host->runtime_suspended = false;
2708
2709         /* Enable SDIO IRQ */
2710         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2711                 sdhci_enable_sdio_irq_nolock(host, true);
2712
2713         /* Enable Card Detection */
2714         sdhci_enable_card_detection(host);
2715
2716         spin_unlock_irqrestore(&host->lock, flags);
2717
2718         return 0;
2719 }
2720 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2721
2722 #endif
2723
2724 /*****************************************************************************\
2725  *                                                                           *
2726  * Device allocation/registration                                            *
2727  *                                                                           *
2728 \*****************************************************************************/
2729
2730 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2731         size_t priv_size)
2732 {
2733         struct mmc_host *mmc;
2734         struct sdhci_host *host;
2735
2736         WARN_ON(dev == NULL);
2737
2738         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2739         if (!mmc)
2740                 return ERR_PTR(-ENOMEM);
2741
2742         host = mmc_priv(mmc);
2743         host->mmc = mmc;
2744
2745         return host;
2746 }
2747
2748 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2749
2750 int sdhci_add_host(struct sdhci_host *host)
2751 {
2752         struct mmc_host *mmc;
2753         u32 caps[2] = {0, 0};
2754         u32 max_current_caps;
2755         unsigned int ocr_avail;
2756         int ret;
2757
2758         WARN_ON(host == NULL);
2759         if (host == NULL)
2760                 return -EINVAL;
2761
2762         mmc = host->mmc;
2763
2764         if (debug_quirks)
2765                 host->quirks = debug_quirks;
2766         if (debug_quirks2)
2767                 host->quirks2 = debug_quirks2;
2768
2769         sdhci_do_reset(host, SDHCI_RESET_ALL);
2770
2771         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2772         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2773                                 >> SDHCI_SPEC_VER_SHIFT;
2774         if (host->version > SDHCI_SPEC_300) {
2775                 pr_err("%s: Unknown controller version (%d). "
2776                         "You may experience problems.\n", mmc_hostname(mmc),
2777                         host->version);
2778         }
2779
2780         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2781                 sdhci_readl(host, SDHCI_CAPABILITIES);
2782
2783         if (host->version >= SDHCI_SPEC_300)
2784                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2785                         host->caps1 :
2786                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2787
2788         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2789                 host->flags |= SDHCI_USE_SDMA;
2790         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2791                 DBG("Controller doesn't have SDMA capability\n");
2792         else
2793                 host->flags |= SDHCI_USE_SDMA;
2794
2795         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2796                 (host->flags & SDHCI_USE_SDMA)) {
2797                 DBG("Disabling DMA as it is marked broken\n");
2798                 host->flags &= ~SDHCI_USE_SDMA;
2799         }
2800
2801         if ((host->version >= SDHCI_SPEC_200) &&
2802                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2803                 host->flags |= SDHCI_USE_ADMA;
2804
2805         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2806                 (host->flags & SDHCI_USE_ADMA)) {
2807                 DBG("Disabling ADMA as it is marked broken\n");
2808                 host->flags &= ~SDHCI_USE_ADMA;
2809         }
2810
2811         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2812                 if (host->ops->enable_dma) {
2813                         if (host->ops->enable_dma(host)) {
2814                                 pr_warning("%s: No suitable DMA "
2815                                         "available. Falling back to PIO.\n",
2816                                         mmc_hostname(mmc));
2817                                 host->flags &=
2818                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2819                         }
2820                 }
2821         }
2822
2823         if (host->flags & SDHCI_USE_ADMA) {
2824                 /*
2825                  * We need to allocate descriptors for all sg entries
2826                  * (128) and potentially one alignment transfer for
2827                  * each of those entries.
2828                  */
2829                 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2830                                                      ADMA_SIZE, &host->adma_addr,
2831                                                      GFP_KERNEL);
2832                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2833                 if (!host->adma_desc || !host->align_buffer) {
2834                         dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2835                                           host->adma_desc, host->adma_addr);
2836                         kfree(host->align_buffer);
2837                         pr_warning("%s: Unable to allocate ADMA "
2838                                 "buffers. Falling back to standard DMA.\n",
2839                                 mmc_hostname(mmc));
2840                         host->flags &= ~SDHCI_USE_ADMA;
2841                         host->adma_desc = NULL;
2842                         host->align_buffer = NULL;
2843                 } else if (host->adma_addr & 3) {
2844                         pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2845                                    mmc_hostname(mmc));
2846                         host->flags &= ~SDHCI_USE_ADMA;
2847                         dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2848                                           host->adma_desc, host->adma_addr);
2849                         kfree(host->align_buffer);
2850                         host->adma_desc = NULL;
2851                         host->align_buffer = NULL;
2852                 }
2853         }
2854
2855         /*
2856          * If we use DMA, then it's up to the caller to set the DMA
2857          * mask, but PIO does not need the hw shim so we set a new
2858          * mask here in that case.
2859          */
2860         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2861                 host->dma_mask = DMA_BIT_MASK(64);
2862                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2863         }
2864
2865         if (host->version >= SDHCI_SPEC_300)
2866                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2867                         >> SDHCI_CLOCK_BASE_SHIFT;
2868         else
2869                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2870                         >> SDHCI_CLOCK_BASE_SHIFT;
2871
2872         host->max_clk *= 1000000;
2873         if (host->max_clk == 0 || host->quirks &
2874                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2875                 if (!host->ops->get_max_clock) {
2876                         pr_err("%s: Hardware doesn't specify base clock "
2877                                "frequency.\n", mmc_hostname(mmc));
2878                         return -ENODEV;
2879                 }
2880                 host->max_clk = host->ops->get_max_clock(host);
2881         }
2882
2883         /*
2884          * In case of Host Controller v3.00, find out whether clock
2885          * multiplier is supported.
2886          */
2887         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2888                         SDHCI_CLOCK_MUL_SHIFT;
2889
2890         /*
2891          * In case the value in Clock Multiplier is 0, then programmable
2892          * clock mode is not supported, otherwise the actual clock
2893          * multiplier is one more than the value of Clock Multiplier
2894          * in the Capabilities Register.
2895          */
2896         if (host->clk_mul)
2897                 host->clk_mul += 1;
2898
2899         /*
2900          * Set host parameters.
2901          */
2902         mmc->ops = &sdhci_ops;
2903         mmc->f_max = host->max_clk;
2904         if (host->ops->get_min_clock)
2905                 mmc->f_min = host->ops->get_min_clock(host);
2906         else if (host->version >= SDHCI_SPEC_300) {
2907                 if (host->clk_mul) {
2908                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2909                         mmc->f_max = host->max_clk * host->clk_mul;
2910                 } else
2911                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2912         } else
2913                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2914
2915         host->timeout_clk =
2916                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2917         if (host->timeout_clk == 0) {
2918                 if (host->ops->get_timeout_clock) {
2919                         host->timeout_clk = host->ops->get_timeout_clock(host);
2920                 } else if (!(host->quirks &
2921                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2922                         pr_err("%s: Hardware doesn't specify timeout clock "
2923                                "frequency.\n", mmc_hostname(mmc));
2924                         return -ENODEV;
2925                 }
2926         }
2927         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2928                 host->timeout_clk *= 1000;
2929
2930         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2931                 host->timeout_clk = mmc->f_max / 1000;
2932
2933         mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2934
2935         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2936         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2937
2938         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2939                 host->flags |= SDHCI_AUTO_CMD12;
2940
2941         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2942         if ((host->version >= SDHCI_SPEC_300) &&
2943             ((host->flags & SDHCI_USE_ADMA) ||
2944              !(host->flags & SDHCI_USE_SDMA))) {
2945                 host->flags |= SDHCI_AUTO_CMD23;
2946                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2947         } else {
2948                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2949         }
2950
2951         /*
2952          * A controller may support 8-bit width, but the board itself
2953          * might not have the pins brought out.  Boards that support
2954          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2955          * their platform code before calling sdhci_add_host(), and we
2956          * won't assume 8-bit width for hosts without that CAP.
2957          */
2958         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2959                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2960
2961         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2962                 mmc->caps &= ~MMC_CAP_CMD23;
2963
2964         if (caps[0] & SDHCI_CAN_DO_HISPD)
2965                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2966
2967         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2968             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2969                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2970
2971         /* If there are external regulators, get them */
2972         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
2973                 return -EPROBE_DEFER;
2974
2975         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2976         if (!IS_ERR(mmc->supply.vqmmc)) {
2977                 ret = regulator_enable(mmc->supply.vqmmc);
2978                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
2979                                                     1950000))
2980                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2981                                         SDHCI_SUPPORT_SDR50 |
2982                                         SDHCI_SUPPORT_DDR50);
2983                 if (ret) {
2984                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2985                                 mmc_hostname(mmc), ret);
2986                         mmc->supply.vqmmc = NULL;
2987                 }
2988         }
2989
2990         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2991                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2992                        SDHCI_SUPPORT_DDR50);
2993
2994         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2995         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2996                        SDHCI_SUPPORT_DDR50))
2997                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2998
2999         /* SDR104 supports also implies SDR50 support */
3000         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3001                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3002                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3003                  * field can be promoted to support HS200.
3004                  */
3005                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3006                         mmc->caps2 |= MMC_CAP2_HS200;
3007         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3008                 mmc->caps |= MMC_CAP_UHS_SDR50;
3009
3010         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3011                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3012                 mmc->caps |= MMC_CAP_UHS_DDR50;
3013
3014         /* Does the host need tuning for SDR50? */
3015         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3016                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3017
3018         /* Does the host need tuning for SDR104 / HS200? */
3019         if (mmc->caps2 & MMC_CAP2_HS200)
3020                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3021
3022         /* Driver Type(s) (A, C, D) supported by the host */
3023         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3024                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3025         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3026                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3027         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3028                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3029
3030         /* Initial value for re-tuning timer count */
3031         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3032                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3033
3034         /*
3035          * In case Re-tuning Timer is not disabled, the actual value of
3036          * re-tuning timer will be 2 ^ (n - 1).
3037          */
3038         if (host->tuning_count)
3039                 host->tuning_count = 1 << (host->tuning_count - 1);
3040
3041         /* Re-tuning mode supported by the Host Controller */
3042         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3043                              SDHCI_RETUNING_MODE_SHIFT;
3044
3045         ocr_avail = 0;
3046
3047         /*
3048          * According to SD Host Controller spec v3.00, if the Host System
3049          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3050          * the value is meaningful only if Voltage Support in the Capabilities
3051          * register is set. The actual current value is 4 times the register
3052          * value.
3053          */
3054         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3055         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3056                 u32 curr = regulator_get_current_limit(mmc->supply.vmmc);
3057                 if (curr > 0) {
3058
3059                         /* convert to SDHCI_MAX_CURRENT format */
3060                         curr = curr/1000;  /* convert to mA */
3061                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3062
3063                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3064                         max_current_caps =
3065                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3066                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3067                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3068                 }
3069         }
3070
3071         if (caps[0] & SDHCI_CAN_VDD_330) {
3072                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3073
3074                 mmc->max_current_330 = ((max_current_caps &
3075                                    SDHCI_MAX_CURRENT_330_MASK) >>
3076                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3077                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3078         }
3079         if (caps[0] & SDHCI_CAN_VDD_300) {
3080                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3081
3082                 mmc->max_current_300 = ((max_current_caps &
3083                                    SDHCI_MAX_CURRENT_300_MASK) >>
3084                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3085                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3086         }
3087         if (caps[0] & SDHCI_CAN_VDD_180) {
3088                 ocr_avail |= MMC_VDD_165_195;
3089
3090                 mmc->max_current_180 = ((max_current_caps &
3091                                    SDHCI_MAX_CURRENT_180_MASK) >>
3092                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3093                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3094         }
3095
3096         /* If OCR set by external regulators, use it instead */
3097         if (mmc->ocr_avail)
3098                 ocr_avail = mmc->ocr_avail;
3099
3100         if (host->ocr_mask)
3101                 ocr_avail &= host->ocr_mask;
3102
3103         mmc->ocr_avail = ocr_avail;
3104         mmc->ocr_avail_sdio = ocr_avail;
3105         if (host->ocr_avail_sdio)
3106                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3107         mmc->ocr_avail_sd = ocr_avail;
3108         if (host->ocr_avail_sd)
3109                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3110         else /* normal SD controllers don't support 1.8V */
3111                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3112         mmc->ocr_avail_mmc = ocr_avail;
3113         if (host->ocr_avail_mmc)
3114                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3115
3116         if (mmc->ocr_avail == 0) {
3117                 pr_err("%s: Hardware doesn't report any "
3118                         "support voltages.\n", mmc_hostname(mmc));
3119                 return -ENODEV;
3120         }
3121
3122         spin_lock_init(&host->lock);
3123
3124         /*
3125          * Maximum number of segments. Depends on if the hardware
3126          * can do scatter/gather or not.
3127          */
3128         if (host->flags & SDHCI_USE_ADMA)
3129                 mmc->max_segs = 128;
3130         else if (host->flags & SDHCI_USE_SDMA)
3131                 mmc->max_segs = 1;
3132         else /* PIO */
3133                 mmc->max_segs = 128;
3134
3135         /*
3136          * Maximum number of sectors in one transfer. Limited by DMA boundary
3137          * size (512KiB).
3138          */
3139         mmc->max_req_size = 524288;
3140
3141         /*
3142          * Maximum segment size. Could be one segment with the maximum number
3143          * of bytes. When doing hardware scatter/gather, each entry cannot
3144          * be larger than 64 KiB though.
3145          */
3146         if (host->flags & SDHCI_USE_ADMA) {
3147                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3148                         mmc->max_seg_size = 65535;
3149                 else
3150                         mmc->max_seg_size = 65536;
3151         } else {
3152                 mmc->max_seg_size = mmc->max_req_size;
3153         }
3154
3155         /*
3156          * Maximum block size. This varies from controller to controller and
3157          * is specified in the capabilities register.
3158          */
3159         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3160                 mmc->max_blk_size = 2;
3161         } else {
3162                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3163                                 SDHCI_MAX_BLOCK_SHIFT;
3164                 if (mmc->max_blk_size >= 3) {
3165                         pr_warning("%s: Invalid maximum block size, "
3166                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3167                         mmc->max_blk_size = 0;
3168                 }
3169         }
3170
3171         mmc->max_blk_size = 512 << mmc->max_blk_size;
3172
3173         /*
3174          * Maximum block count.
3175          */
3176         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3177
3178         /*
3179          * Init tasklets.
3180          */
3181         tasklet_init(&host->finish_tasklet,
3182                 sdhci_tasklet_finish, (unsigned long)host);
3183
3184         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3185
3186         if (host->version >= SDHCI_SPEC_300) {
3187                 init_waitqueue_head(&host->buf_ready_int);
3188
3189                 /* Initialize re-tuning timer */
3190                 init_timer(&host->tuning_timer);
3191                 host->tuning_timer.data = (unsigned long)host;
3192                 host->tuning_timer.function = sdhci_tuning_timer;
3193         }
3194
3195         sdhci_init(host, 0);
3196
3197         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3198                                    IRQF_SHARED, mmc_hostname(mmc), host);
3199         if (ret) {
3200                 pr_err("%s: Failed to request IRQ %d: %d\n",
3201                        mmc_hostname(mmc), host->irq, ret);
3202                 goto untasklet;
3203         }
3204
3205 #ifdef CONFIG_MMC_DEBUG
3206         sdhci_dumpregs(host);
3207 #endif
3208
3209 #ifdef SDHCI_USE_LEDS_CLASS
3210         snprintf(host->led_name, sizeof(host->led_name),
3211                 "%s::", mmc_hostname(mmc));
3212         host->led.name = host->led_name;
3213         host->led.brightness = LED_OFF;
3214         host->led.default_trigger = mmc_hostname(mmc);
3215         host->led.brightness_set = sdhci_led_control;
3216
3217         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3218         if (ret) {
3219                 pr_err("%s: Failed to register LED device: %d\n",
3220                        mmc_hostname(mmc), ret);
3221                 goto reset;
3222         }
3223 #endif
3224
3225         mmiowb();
3226
3227         mmc_add_host(mmc);
3228
3229         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3230                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3231                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3232                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3233
3234         sdhci_enable_card_detection(host);
3235
3236         return 0;
3237
3238 #ifdef SDHCI_USE_LEDS_CLASS
3239 reset:
3240         sdhci_do_reset(host, SDHCI_RESET_ALL);
3241         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3242         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3243         free_irq(host->irq, host);
3244 #endif
3245 untasklet:
3246         tasklet_kill(&host->finish_tasklet);
3247
3248         return ret;
3249 }
3250
3251 EXPORT_SYMBOL_GPL(sdhci_add_host);
3252
3253 void sdhci_remove_host(struct sdhci_host *host, int dead)
3254 {
3255         struct mmc_host *mmc = host->mmc;
3256         unsigned long flags;
3257
3258         if (dead) {
3259                 spin_lock_irqsave(&host->lock, flags);
3260
3261                 host->flags |= SDHCI_DEVICE_DEAD;
3262
3263                 if (host->mrq) {
3264                         pr_err("%s: Controller removed during "
3265                                 " transfer!\n", mmc_hostname(host->mmc));
3266
3267                         host->mrq->cmd->error = -ENOMEDIUM;
3268                         tasklet_schedule(&host->finish_tasklet);
3269                 }
3270
3271                 spin_unlock_irqrestore(&host->lock, flags);
3272         }
3273
3274         sdhci_disable_card_detection(host);
3275
3276         mmc_remove_host(host->mmc);
3277
3278 #ifdef SDHCI_USE_LEDS_CLASS
3279         led_classdev_unregister(&host->led);
3280 #endif
3281
3282         if (!dead)
3283                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3284
3285         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3286         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3287         free_irq(host->irq, host);
3288
3289         del_timer_sync(&host->timer);
3290
3291         tasklet_kill(&host->finish_tasklet);
3292
3293         if (!IS_ERR(mmc->supply.vmmc))
3294                 regulator_disable(mmc->supply.vmmc);
3295
3296         if (!IS_ERR(mmc->supply.vqmmc))
3297                 regulator_disable(mmc->supply.vqmmc);
3298
3299         if (host->adma_desc)
3300                 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3301                                   host->adma_desc, host->adma_addr);
3302         kfree(host->align_buffer);
3303
3304         host->adma_desc = NULL;
3305         host->align_buffer = NULL;
3306 }
3307
3308 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3309
3310 void sdhci_free_host(struct sdhci_host *host)
3311 {
3312         mmc_free_host(host->mmc);
3313 }
3314
3315 EXPORT_SYMBOL_GPL(sdhci_free_host);
3316
3317 /*****************************************************************************\
3318  *                                                                           *
3319  * Driver init/exit                                                          *
3320  *                                                                           *
3321 \*****************************************************************************/
3322
3323 static int __init sdhci_drv_init(void)
3324 {
3325         pr_info(DRIVER_NAME
3326                 ": Secure Digital Host Controller Interface driver\n");
3327         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3328
3329         return 0;
3330 }
3331
3332 static void __exit sdhci_drv_exit(void)
3333 {
3334 }
3335
3336 module_init(sdhci_drv_init);
3337 module_exit(sdhci_drv_exit);
3338
3339 module_param(debug_quirks, uint, 0444);
3340 module_param(debug_quirks2, uint, 0444);
3341
3342 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3343 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3344 MODULE_LICENSE("GPL");
3345
3346 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3347 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");